diff -Nrcpad gcc-16-20260627/LAST_UPDATED gcc-16-20260704/LAST_UPDATED
*** gcc-16-20260627/LAST_UPDATED	Sat Jun 27 22:32:22 2026
--- gcc-16-20260704/LAST_UPDATED	Sat Jul  4 22:32:24 2026
***************
*** 1 ****
! Obtained from git: releases/gcc-16 revision 32c1d1988cc7f56f1a7a9e550936267de6b152c2
--- 1 ----
! Obtained from git: releases/gcc-16 revision 049dd97dd7e09a04a0492a6573fdc6a7645734b2
diff -Nrcpad gcc-16-20260627/MD5SUMS gcc-16-20260704/MD5SUMS
*** gcc-16-20260627/MD5SUMS	Sat Jun 27 22:32:27 2026
--- gcc-16-20260704/MD5SUMS	Sat Jul  4 22:32:29 2026
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-16-20260627.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-16-20260704.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
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*** 28,34 ****
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*** 824,831 ****
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--- 824,831 ----
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*************** e3dc2d270994bba222e70ec02479ac37  gcc/ad
*** 2921,2936 ****
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*************** eb23a07f1fb62ed39d1053619d51487b  gcc/ad
*** 2957,2963 ****
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*************** b218f741c2f54f950d065bb40f5125ea  gcc/co
*** 3466,3474 ****
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--- 3466,3474 ----
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*************** d3b8ce30c6110489fd0b57d6792f3f29  gcc/co
*** 3504,3510 ****
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--- 3504,3510 ----
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*** 3559,3565 ****
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--- 3559,3565 ----
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*** 3581,3587 ****
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--- 3581,3587 ----
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*** 4226,4232 ****
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  3af5d025bacebb10ac3eecc45363f3f5  gcc/config/i386/cetintrin.h
*************** ca79ed6b45db789c76673ad8ab56752f  gcc/co
*** 4255,4261 ****
  b5bf289667d7414f0f070d1d6195c05b  gcc/config/i386/djgpp.opt
  1b346c8cab1daa697ecd6c31e8e0e1d5  gcc/config/i386/djgpp.opt.urls
  6e6ed34837087e891dbe64159c7aceaf  gcc/config/i386/dragonfly.h
! 9a6a9e4051a54dbd274309dd1b2b21e4  gcc/config/i386/driver-i386.cc
  c3f8400c2cd15cc6fdc2c91d79a3039c  gcc/config/i386/driver-mingw32.cc
  f7e63c0c0bc7833d6119bebb9abe588d  gcc/config/i386/emmintrin.h
  9137411ae180f544dbdf04c71fa244bd  gcc/config/i386/enqcmdintrin.h
--- 4255,4261 ----
  b5bf289667d7414f0f070d1d6195c05b  gcc/config/i386/djgpp.opt
  1b346c8cab1daa697ecd6c31e8e0e1d5  gcc/config/i386/djgpp.opt.urls
  6e6ed34837087e891dbe64159c7aceaf  gcc/config/i386/dragonfly.h
! 54411bed22acbd3c66919279d3ea175d  gcc/config/i386/driver-i386.cc
  c3f8400c2cd15cc6fdc2c91d79a3039c  gcc/config/i386/driver-mingw32.cc
  f7e63c0c0bc7833d6119bebb9abe588d  gcc/config/i386/emmintrin.h
  9137411ae180f544dbdf04c71fa244bd  gcc/config/i386/enqcmdintrin.h
*************** b18770c338209a9276ef5d52a49bde7b  gcc/co
*** 4287,4304 ****
  0ba4d62f46027afe4bb4e8b65a9ab7c2  gcc/config/i386/i386-builtin.def
  8dbd55fdf807ba9b636b99fdf4277e4d  gcc/config/i386/i386-builtins.cc
  be7f06e3ea032dfb39fcda012c812683  gcc/config/i386/i386-builtins.h
! b4003ec8a83a5b025fb5f9d5334af62e  gcc/config/i386/i386-c.cc
  a0261d6cc006fb86b99f338bdc94ae04  gcc/config/i386/i386-d.cc
  e9c7eebd4e344796f248c93990aa5166  gcc/config/i386/i386-d.h
  5a4e3cda74f475c95f4340b87c3d0162  gcc/config/i386/i386-expand.cc
  386e1be7f608621b79970d4d036694f8  gcc/config/i386/i386-expand.h
! e0276b18d746ed8cead3e8f99f281a18  gcc/config/i386/i386-features.cc
  473c35b162be3bcf222c90a16f72b948  gcc/config/i386/i386-features.h
  dca59d9c03f5b12366f9a926169f396d  gcc/config/i386/i386-isa.def
  848d1b1aa8faaad07d31b78764004e7f  gcc/config/i386/i386-jit.cc
  d743703707286fafa2ce425b1d062ee0  gcc/config/i386/i386-jit.h
  31871dc86b95e35e45aee6cbaaddb18d  gcc/config/i386/i386-modes.def
! c20b5abeadf9bf0c148bd3cee43dabbf  gcc/config/i386/i386-options.cc
  106bb7043496820d393f0522178e1287  gcc/config/i386/i386-options.h
  2db6ec1e569468279f31d11379fe9d8f  gcc/config/i386/i386-opts.h
  9a75f0c116528508f4f48d128eceac38  gcc/config/i386/i386-passes.def
--- 4287,4304 ----
  0ba4d62f46027afe4bb4e8b65a9ab7c2  gcc/config/i386/i386-builtin.def
  8dbd55fdf807ba9b636b99fdf4277e4d  gcc/config/i386/i386-builtins.cc
  be7f06e3ea032dfb39fcda012c812683  gcc/config/i386/i386-builtins.h
! 16abb65175df4287dab5911bc51933d2  gcc/config/i386/i386-c.cc
  a0261d6cc006fb86b99f338bdc94ae04  gcc/config/i386/i386-d.cc
  e9c7eebd4e344796f248c93990aa5166  gcc/config/i386/i386-d.h
  5a4e3cda74f475c95f4340b87c3d0162  gcc/config/i386/i386-expand.cc
  386e1be7f608621b79970d4d036694f8  gcc/config/i386/i386-expand.h
! 3acf3a68fd0f86d37478034e149ab9b4  gcc/config/i386/i386-features.cc
  473c35b162be3bcf222c90a16f72b948  gcc/config/i386/i386-features.h
  dca59d9c03f5b12366f9a926169f396d  gcc/config/i386/i386-isa.def
  848d1b1aa8faaad07d31b78764004e7f  gcc/config/i386/i386-jit.cc
  d743703707286fafa2ce425b1d062ee0  gcc/config/i386/i386-jit.h
  31871dc86b95e35e45aee6cbaaddb18d  gcc/config/i386/i386-modes.def
! 8c7abf5f22844466fcc8c2eb87495f78  gcc/config/i386/i386-options.cc
  106bb7043496820d393f0522178e1287  gcc/config/i386/i386-options.h
  2db6ec1e569468279f31d11379fe9d8f  gcc/config/i386/i386-opts.h
  9a75f0c116528508f4f48d128eceac38  gcc/config/i386/i386-passes.def
*************** c20b5abeadf9bf0c148bd3cee43dabbf  gcc/co
*** 4306,4314 ****
  5b778b3296ea91dab0ca82338ca6828d  gcc/config/i386/i386-rust-and-jit.inc
  91b8b50cba997aef17a61929b5b55a87  gcc/config/i386/i386-rust.cc
  25b3947a11eb9ca52892133ddb36f3f2  gcc/config/i386/i386-rust.h
! afc4c9338540c25cc3d9d203b0a1b17e  gcc/config/i386/i386.cc
! 48d2fe2c9070db592c7e81e84c0702b8  gcc/config/i386/i386.h
! 4bc5501fc7dfa6908938e4d2b593736f  gcc/config/i386/i386.md
  f431cbff6410e63b4e2de0e11adf19fb  gcc/config/i386/i386.opt
  b9e680863ab278314c1f2990d2d04fcc  gcc/config/i386/i386.opt.urls
  7570cb8763bf53e7144db7d6cd97f846  gcc/config/i386/i386elf.h
--- 4306,4314 ----
  5b778b3296ea91dab0ca82338ca6828d  gcc/config/i386/i386-rust-and-jit.inc
  91b8b50cba997aef17a61929b5b55a87  gcc/config/i386/i386-rust.cc
  25b3947a11eb9ca52892133ddb36f3f2  gcc/config/i386/i386-rust.h
! 4b7f2e6ba75f5b26f3d864561130a6e0  gcc/config/i386/i386.cc
! 47906818c05f1b4d2cf82b08c400db14  gcc/config/i386/i386.h
! 00ec6ce9c3da79293c699e2e4c7e495a  gcc/config/i386/i386.md
  f431cbff6410e63b4e2de0e11adf19fb  gcc/config/i386/i386.opt
  b9e680863ab278314c1f2990d2d04fcc  gcc/config/i386/i386.opt.urls
  7570cb8763bf53e7144db7d6cd97f846  gcc/config/i386/i386elf.h
*************** db114ac74c87743a142214fddaad2687  gcc/co
*** 4371,4377 ****
  92210572b9f9f6481e4649a42d9ac3b0  gcc/config/i386/sm4intrin.h
  5298b8261e081859bbf068b710158e8f  gcc/config/i386/smmintrin.h
  5b7a5d6bd6f2cbb1ca44a113b598ee56  gcc/config/i386/sol2.h
! cb351fdc4bd2b8f16d5919d4df421608  gcc/config/i386/sse.md
  52e0114cb9ab8d55aac3c17d06657d71  gcc/config/i386/ssemath.h
  8a6ab9e02097018bc9f1c2b347d29cfa  gcc/config/i386/stringop.def
  a626b4e6cd3e15f4e9d5c769b6391243  gcc/config/i386/subst.md
--- 4371,4377 ----
  92210572b9f9f6481e4649a42d9ac3b0  gcc/config/i386/sm4intrin.h
  5298b8261e081859bbf068b710158e8f  gcc/config/i386/smmintrin.h
  5b7a5d6bd6f2cbb1ca44a113b598ee56  gcc/config/i386/sol2.h
! c7e21c40eebfbcec930c97816d8e1ba5  gcc/config/i386/sse.md
  52e0114cb9ab8d55aac3c17d06657d71  gcc/config/i386/ssemath.h
  8a6ab9e02097018bc9f1c2b347d29cfa  gcc/config/i386/stringop.def
  a626b4e6cd3e15f4e9d5c769b6391243  gcc/config/i386/subst.md
*************** b4cde95b709fc93c90bf4d6b3edc7fd0  gcc/co
*** 4419,4430 ****
  c2cfb83eb28cbbc487a62ee85650286e  gcc/config/i386/x-mingw32
  5d8e585db0fd38674f683b0e8aafb897  gcc/config/i386/x-mingw32-utf8
  c98679993951718aa4177acc76b998b3  gcc/config/i386/x86-64.h
! f6bbb5ec11c335e5bf727fa42672a721  gcc/config/i386/x86-tune-costs.h
  c22e895e5b7e6b98c7223b26982a5d20  gcc/config/i386/x86-tune-sched-atom.cc
  7bfce4f9fdee1dc1db1e668b10d9d8e2  gcc/config/i386/x86-tune-sched-bd.cc
  864e537089cc92c5002cefd76ede977a  gcc/config/i386/x86-tune-sched-core.cc
! 4fddfbe9b1f3fe846e29534aa8c76823  gcc/config/i386/x86-tune-sched.cc
! 65ae6067461a1868e9aab9ab87190f2d  gcc/config/i386/x86-tune.def
  75b1f0e8f79cfd04f898a4099aff669d  gcc/config/i386/x86gprintrin.h
  e5335d55cec73bd3270862ccac7a02e8  gcc/config/i386/x86intrin.h
  76f88cf5ac857d392ddb81b244c5b9b0  gcc/config/i386/xm-cygwin.h
--- 4419,4430 ----
  c2cfb83eb28cbbc487a62ee85650286e  gcc/config/i386/x-mingw32
  5d8e585db0fd38674f683b0e8aafb897  gcc/config/i386/x-mingw32-utf8
  c98679993951718aa4177acc76b998b3  gcc/config/i386/x86-64.h
! fcbc022d3715cc20df98008db69451fd  gcc/config/i386/x86-tune-costs.h
  c22e895e5b7e6b98c7223b26982a5d20  gcc/config/i386/x86-tune-sched-atom.cc
  7bfce4f9fdee1dc1db1e668b10d9d8e2  gcc/config/i386/x86-tune-sched-bd.cc
  864e537089cc92c5002cefd76ede977a  gcc/config/i386/x86-tune-sched-core.cc
! 32bfe52b71dd89980a3ca6adeeea9154  gcc/config/i386/x86-tune-sched.cc
! 798ee23e820c3fb8a3bfd2471736fd0b  gcc/config/i386/x86-tune.def
  75b1f0e8f79cfd04f898a4099aff669d  gcc/config/i386/x86gprintrin.h
  e5335d55cec73bd3270862ccac7a02e8  gcc/config/i386/x86intrin.h
  76f88cf5ac857d392ddb81b244c5b9b0  gcc/config/i386/xm-cygwin.h
*************** fc623524d75c7561f85f81615ecad0ac  gcc/co
*** 4545,4551 ****
  3cfb174db8bc99a9361e597a3e9bd35e  gcc/config/loongarch/loongarch-tune.h
  e9dd9aa1d7f42b839457347be97e4889  gcc/config/loongarch/loongarch.cc
  44710020cadd48029a693da29d33aaf0  gcc/config/loongarch/loongarch.h
! adc166d1f0d499682e5ce2d43178115d  gcc/config/loongarch/loongarch.md
  62f9bea81246c3dac622d969dabefc1b  gcc/config/loongarch/loongarch.opt
  387011bb9dde5e25493f3602b2fd17bb  gcc/config/loongarch/loongarch.opt.urls
  561a66379ab213d1901626005734b467  gcc/config/loongarch/lsx.md
--- 4545,4551 ----
  3cfb174db8bc99a9361e597a3e9bd35e  gcc/config/loongarch/loongarch-tune.h
  e9dd9aa1d7f42b839457347be97e4889  gcc/config/loongarch/loongarch.cc
  44710020cadd48029a693da29d33aaf0  gcc/config/loongarch/loongarch.h
! 28746b3b3b882fba7d3a3a75cd6516b3  gcc/config/loongarch/loongarch.md
  62f9bea81246c3dac622d969dabefc1b  gcc/config/loongarch/loongarch.opt
  387011bb9dde5e25493f3602b2fd17bb  gcc/config/loongarch/loongarch.opt.urls
  561a66379ab213d1901626005734b467  gcc/config/loongarch/lsx.md
*************** f83fd3bf0d9fbc30c9401eec549fdc2c  gcc/co
*** 5184,5190 ****
  161814e9f6f10782769302881ac26227  gcc/config/rs6000/bmiintrin.h
  ee17a95e2411ef6ef4f1588d17e2cf66  gcc/config/rs6000/cell.md
  837f16df42ea04e41a4450e7f9ebe42a  gcc/config/rs6000/constraints.md
! abeb41de7dfa216c254877ecd48052f1  gcc/config/rs6000/crypto.md
  841aa28da573ce031fe43ae0fb24bfd9  gcc/config/rs6000/darwin.h
  8c9c110a4faa8e47a4c4caef834d7c1d  gcc/config/rs6000/darwin.md
  8ef5306087b5e728b308cf63664b051d  gcc/config/rs6000/darwin.opt
--- 5184,5190 ----
  161814e9f6f10782769302881ac26227  gcc/config/rs6000/bmiintrin.h
  ee17a95e2411ef6ef4f1588d17e2cf66  gcc/config/rs6000/cell.md
  837f16df42ea04e41a4450e7f9ebe42a  gcc/config/rs6000/constraints.md
! 9dfea0dab8f972986488db93eb23fab1  gcc/config/rs6000/crypto.md
  841aa28da573ce031fe43ae0fb24bfd9  gcc/config/rs6000/darwin.h
  8c9c110a4faa8e47a4c4caef834d7c1d  gcc/config/rs6000/darwin.md
  8ef5306087b5e728b308cf63664b051d  gcc/config/rs6000/darwin.opt
*************** db237fc1717a4075e7b9480205a32fd5  gcc/co
*** 5244,5271 ****
  25ea383c1f398321c28d21896c9d79db  gcc/config/rs6000/predicates.md
  63ccc96ff2cef948c080eac4455d02b1  gcc/config/rs6000/rbtree.cc
  8ece9ca8167f5056fa411488a97c6131  gcc/config/rs6000/rbtree.h
! 952a15095d55ed13cac7857cfcd12d7e  gcc/config/rs6000/rs6000-builtin.cc
! 5f55438b54e629713ba06eeb9a75bd37  gcc/config/rs6000/rs6000-builtins.def
! 15e52baa355b0c3b725c3e6e55524af0  gcc/config/rs6000/rs6000-c.cc
  c97babd518212b16f2837b9b1d5d8359  gcc/config/rs6000/rs6000-call.cc
  4579aba833c122ad0e6a91b573653e2c  gcc/config/rs6000/rs6000-cpus.def
  7b860836fdc33cdfdd29f6348a553096  gcc/config/rs6000/rs6000-d.cc
  1ac6ae1e7d6d83d76667769f7166b9a7  gcc/config/rs6000/rs6000-d.h
! 19cf935ce7de136fe7ef1a4a6350f541  gcc/config/rs6000/rs6000-gen-builtins.cc
  c165dfc83b2c9e75d3906f429e76a3fa  gcc/config/rs6000/rs6000-internal.h
  68da03c0d0c1dfafebf4ba706e6d3ff9  gcc/config/rs6000/rs6000-linux.cc
  4768cacdca0b901f6cb649726cca5eeb  gcc/config/rs6000/rs6000-logue.cc
  108998dcf0201ccd3e147d71251ca9f6  gcc/config/rs6000/rs6000-modes.def
  e6f2820356a7ee18c353376ab3490fb6  gcc/config/rs6000/rs6000-opts.h
! fab9961e9c2dca827c0ac5e7b100d398  gcc/config/rs6000/rs6000-overload.def
  dc46fa102175551da2f4ce2ee5c6435c  gcc/config/rs6000/rs6000-p8swap.cc
  da37007432adac35e44d7592e307e64a  gcc/config/rs6000/rs6000-passes.def
  384645a6c72587ac7501915a0c737e64  gcc/config/rs6000/rs6000-pcrel-opt.cc
! d3a1c98fd13be04e1250b073cb8dcef2  gcc/config/rs6000/rs6000-protos.h
  9e39e759376eb97f2a56ebfc28c8d149  gcc/config/rs6000/rs6000-string.cc
  835f22c956cc4deb83970ee9a9b5b79b  gcc/config/rs6000/rs6000-tables.opt
  ce8de9a27f36b759a69194616c02eb38  gcc/config/rs6000/rs6000-tables.opt.urls
! 133c7cb4fcb84c2a55999c792301652f  gcc/config/rs6000/rs6000.cc
  022807cee92311bbde8050337f5e7efb  gcc/config/rs6000/rs6000.h
  a575dd5c5592c7d23a9b53b985c01120  gcc/config/rs6000/rs6000.md
  e407423336f12658b509205c3e8f7130  gcc/config/rs6000/rs6000.opt
--- 5244,5271 ----
  25ea383c1f398321c28d21896c9d79db  gcc/config/rs6000/predicates.md
  63ccc96ff2cef948c080eac4455d02b1  gcc/config/rs6000/rbtree.cc
  8ece9ca8167f5056fa411488a97c6131  gcc/config/rs6000/rbtree.h
! 9d6e3642f81b371d186717d3d443741c  gcc/config/rs6000/rs6000-builtin.cc
! 010031868edf76618f069fc191ba34a5  gcc/config/rs6000/rs6000-builtins.def
! bb710aa9f6e98d46357a2a10104dda23  gcc/config/rs6000/rs6000-c.cc
  c97babd518212b16f2837b9b1d5d8359  gcc/config/rs6000/rs6000-call.cc
  4579aba833c122ad0e6a91b573653e2c  gcc/config/rs6000/rs6000-cpus.def
  7b860836fdc33cdfdd29f6348a553096  gcc/config/rs6000/rs6000-d.cc
  1ac6ae1e7d6d83d76667769f7166b9a7  gcc/config/rs6000/rs6000-d.h
! 9e2905c5e0b10bcbf6e70f323c37bbdf  gcc/config/rs6000/rs6000-gen-builtins.cc
  c165dfc83b2c9e75d3906f429e76a3fa  gcc/config/rs6000/rs6000-internal.h
  68da03c0d0c1dfafebf4ba706e6d3ff9  gcc/config/rs6000/rs6000-linux.cc
  4768cacdca0b901f6cb649726cca5eeb  gcc/config/rs6000/rs6000-logue.cc
  108998dcf0201ccd3e147d71251ca9f6  gcc/config/rs6000/rs6000-modes.def
  e6f2820356a7ee18c353376ab3490fb6  gcc/config/rs6000/rs6000-opts.h
! d7427b95ab9b1b6a0f245c77b298f61f  gcc/config/rs6000/rs6000-overload.def
  dc46fa102175551da2f4ce2ee5c6435c  gcc/config/rs6000/rs6000-p8swap.cc
  da37007432adac35e44d7592e307e64a  gcc/config/rs6000/rs6000-passes.def
  384645a6c72587ac7501915a0c737e64  gcc/config/rs6000/rs6000-pcrel-opt.cc
! 27554d327449762be03c44084bead914  gcc/config/rs6000/rs6000-protos.h
  9e39e759376eb97f2a56ebfc28c8d149  gcc/config/rs6000/rs6000-string.cc
  835f22c956cc4deb83970ee9a9b5b79b  gcc/config/rs6000/rs6000-tables.opt
  ce8de9a27f36b759a69194616c02eb38  gcc/config/rs6000/rs6000-tables.opt.urls
! 43c48798ca1e7e10c5d7cef5a074429a  gcc/config/rs6000/rs6000.cc
  022807cee92311bbde8050337f5e7efb  gcc/config/rs6000/rs6000.h
  a575dd5c5592c7d23a9b53b985c01120  gcc/config/rs6000/rs6000.md
  e407423336f12658b509205c3e8f7130  gcc/config/rs6000/rs6000.opt
*************** d57d0eb0a8e2193f5cef2aaf1ad6d722  gcc/co
*** 5276,5282 ****
  0a803e7432938644d0614c5d9ee60670  gcc/config/rs6000/si2vmx.h
  b1a1f1ea8636fe96381989b926619397  gcc/config/rs6000/smmintrin.h
  016514c870054ecd799330bad9520a9d  gcc/config/rs6000/spu2vmx.h
! 1e29cb9165b1e69aa36190a9d528b27e  gcc/config/rs6000/sync.md
  e8c76038df323d77e90f69c78138b1fd  gcc/config/rs6000/sysv4.h
  e51499a69ac94adadb730c6c5491b97d  gcc/config/rs6000/sysv4.opt
  b1ed936b1a3e7303c34f1e54ec933230  gcc/config/rs6000/sysv4.opt.urls
--- 5276,5282 ----
  0a803e7432938644d0614c5d9ee60670  gcc/config/rs6000/si2vmx.h
  b1a1f1ea8636fe96381989b926619397  gcc/config/rs6000/smmintrin.h
  016514c870054ecd799330bad9520a9d  gcc/config/rs6000/spu2vmx.h
! 514b735b14f4d170ed5f976ec3483954  gcc/config/rs6000/sync.md
  e8c76038df323d77e90f69c78138b1fd  gcc/config/rs6000/sysv4.h
  e51499a69ac94adadb730c6c5491b97d  gcc/config/rs6000/sysv4.opt
  b1ed936b1a3e7303c34f1e54ec933230  gcc/config/rs6000/sysv4.opt.urls
*************** ea440bcad8a276afecfcff0ce6aae6fe  gcc/co
*** 5364,5370 ****
  14c40f85d99aad740c052f55703baf70  gcc/config/s390/s390-opts.h
  aa396b24681954cbcd0cd64bf19d469c  gcc/config/s390/s390-passes.def
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*** 6727,6733 ****
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*** 23370,23375 ****
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*************** ec931fac17f763f1bc84069e03ca53fa  gcc/te
*** 25065,25070 ****
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*** 133342,133348 ****
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--- 133370,133376 ----
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*************** a73d560a3ba317c5ad0a7919d87b4b6d  libssp
*** 145955,145961 ****
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--- 145983,145989 ----
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*************** abf1c74de0fb52f696034bd48432d075  libstd
*** 146649,146655 ****
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--- 146677,146683 ----
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*************** a5e720346d3b4c60bfbcb9cf9a79f417  libstd
*** 146742,146755 ****
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*************** ce66644b3691c04e697aa707358542a6  libstd
*** 147659,147665 ****
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--- 147687,147693 ----
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*************** efc2d383fef2d2a712b15fabea12d717  libstd
*** 147684,147690 ****
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--- 147712,147718 ----
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*************** cdf9c54ab7ea85aa42bbf32b2e749913  libstd
*** 147709,147715 ****
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--- 147737,147743 ----
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*************** e5a726de140540a59e2007eceae3acd1  libstd
*** 147737,147743 ****
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--- 147765,147771 ----
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*************** c4a0f1988ab64c05d8acb1647b35c6b6  libstd
*** 155025,155034 ****
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--- 155053,155062 ----
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*************** aecb3356c64edbcd333d271606efd55f  libstd
*** 155040,155046 ****
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  e11957df9e55154829ef2c88f05939da  libstdc++-v3/testsuite/27_io/filesystem/operations/last_write_time.cc
  21ce7cfab3a7d4fae787d92e0964bbf0  libstdc++-v3/testsuite/27_io/filesystem/operations/permissions.cc
! d3bfb9763a0417404cbf25c413706c20  libstdc++-v3/testsuite/27_io/filesystem/operations/pr118158.cc
  b647d57a9901c82d0129c5201acc9094  libstdc++-v3/testsuite/27_io/filesystem/operations/proximate.cc
  42bbabf2da09905ae37bbba098e11e54  libstdc++-v3/testsuite/27_io/filesystem/operations/read_symlink.cc
  7a4057ce0324bf3666a807bf226db6b0  libstdc++-v3/testsuite/27_io/filesystem/operations/relative.cc
--- 155068,155074 ----
  9aa4edaec681b4c91aa1fc15e09fd6bf  libstdc++-v3/testsuite/27_io/filesystem/operations/is_empty.cc
  e11957df9e55154829ef2c88f05939da  libstdc++-v3/testsuite/27_io/filesystem/operations/last_write_time.cc
  21ce7cfab3a7d4fae787d92e0964bbf0  libstdc++-v3/testsuite/27_io/filesystem/operations/permissions.cc
! 8c96b3b2206b4a258bec4e71bdf5c09d  libstdc++-v3/testsuite/27_io/filesystem/operations/pr118158.cc
  b647d57a9901c82d0129c5201acc9094  libstdc++-v3/testsuite/27_io/filesystem/operations/proximate.cc
  42bbabf2da09905ae37bbba098e11e54  libstdc++-v3/testsuite/27_io/filesystem/operations/read_symlink.cc
  7a4057ce0324bf3666a807bf226db6b0  libstdc++-v3/testsuite/27_io/filesystem/operations/relative.cc
*************** e2493aaebd9a1a286017264515b56ba5  libstd
*** 157411,157417 ****
  d020ffeed3a700de700dcd8ab75dcc70  libstdc++-v3/testsuite/std/simd/stores_expensive.cc
  9555f30a8004fbe5c183c3d458dbe0c7  libstdc++-v3/testsuite/std/simd/test_setup.h
  6fc3af6248205b9756a89ab36e7d57c7  libstdc++-v3/testsuite/std/simd/traits_common.cc
! 6e23d90aa722f32c50e0010fcf2a9dbf  libstdc++-v3/testsuite/std/simd/traits_impl.cc
  b9fbe2181e3faf5bba7943f5a46a4f00  libstdc++-v3/testsuite/std/simd/traits_math.cc
  a0efc42f3d3e1e881d69063fe7f2c586  libstdc++-v3/testsuite/std/text_encoding/cons.cc
  bfa6a93e5c5cd2d11c1eddd5572fd5de  libstdc++-v3/testsuite/std/text_encoding/members.cc
--- 157439,157445 ----
  d020ffeed3a700de700dcd8ab75dcc70  libstdc++-v3/testsuite/std/simd/stores_expensive.cc
  9555f30a8004fbe5c183c3d458dbe0c7  libstdc++-v3/testsuite/std/simd/test_setup.h
  6fc3af6248205b9756a89ab36e7d57c7  libstdc++-v3/testsuite/std/simd/traits_common.cc
! 32c48a7d3243b9a78a267a51cfa33c22  libstdc++-v3/testsuite/std/simd/traits_impl.cc
  b9fbe2181e3faf5bba7943f5a46a4f00  libstdc++-v3/testsuite/std/simd/traits_math.cc
  a0efc42f3d3e1e881d69063fe7f2c586  libstdc++-v3/testsuite/std/text_encoding/cons.cc
  bfa6a93e5c5cd2d11c1eddd5572fd5de  libstdc++-v3/testsuite/std/text_encoding/members.cc
diff -Nrcpad gcc-16-20260627/gcc/ChangeLog gcc-16-20260704/gcc/ChangeLog
*** gcc-16-20260627/gcc/ChangeLog	Sat Jun 27 22:32:04 2026
--- gcc-16-20260704/gcc/ChangeLog	Sat Jul  4 22:32:05 2026
***************
*** 1,3 ****
--- 1,568 ----
+ 2026-07-03  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 
+ 	Backported from master:
+ 	2026-05-07  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 
+ 	* config/rs6000/crypto.md (UNSPEC_XXAESENCP): New unspec entry.
+ 	(UNSPEC_XXAES128ENCP): Likewise.
+ 	(UNSPEC_XXAES192ENCP): Likewise.
+ 	(UNSPEC_XXAES256ENCP): Likewise.
+ 	(UNSPEC_XXAESDECP): Likewise.
+ 	(UNSPEC_XXAES128DECP): Likewise.
+ 	(UNSPEC_XXAES192DECP): Likewise.
+ 	(UNSPEC_XXAES256DECP): Likewise.
+ 	(UNSPEC_XXAESGENLKP): Likewise.
+ 	(UNSPEC_XXAES128GENLKP): Likewise.
+ 	(UNSPEC_XXAES192GENLKP): Likewise.
+ 	(UNSPEC_XXAES256GENLKP): Likewise.
+ 	(UNSPEC_XXGFMUL128): Likewise.
+ 	(UNSPEC_XXGFMUL128GCM): Likewise.
+ 	(UNSPEC_XXGFMUL128XTS): Likewise.
+ 	(AESACC_base_code): New iterator for xxaesencp and xxaesdecp base
+ 	mnemonics.
+ 	(AESACC_code): New iterator for xxaesencp and xxaesdecp extended
+ 	mnemonics.
+ 	(AESGENLKP_code): New iterator for xxaesgenlkp extended mnemonics.
+ 	(AESGF_code): New iterator for xxgfmul128 extended mnemonics.
+ 	(AESACC_base_insn): New attribute iterator for xxaesencp and xxaesdecp
+ 	base mnemonics.
+ 	(AESACC_insn): New attribute iterator for xxaesencp and xxaesdecp
+ 	extended mnemonics.
+ 	(AESGENLKP_insn): New attribute iterator for xxaesgenlkp extended
+ 	mnemonics.
+ 	(AESGF_insn): New attribute iterator for xxgfmul128 extended mnemonics.
+ 	(<AESACC_base_insn>): New define_insn for xxaesencp and xxaesdecp base
+ 	mnemonics.
+ 	(<AESACC_insn>): New define_insn for xxaesencp and xxaesdecp extended
+ 	mnemonics.
+ 	(<AESGENLKP_insn>): New define_insn for xxaesgenlkp extended mnemonics.
+ 	(xxaesgenlkp): New define_insn for genlkp base mnemonic.
+ 	(<AESGF_insn>): New define_insn for xxgfmul128 extended mnemonics.
+ 	(xxgfmul128): New define_insn for xxgfmul128 base mnemonic.
+ 	* config/rs6000/rs6000-builtins.def: Added new builtin definitions for
+ 	AES acceleration.
+ 	* doc/extend.texi: Add new section for AES acceleration builtins
+ 	for Future ISA.
+ 
+ 2026-07-03  Kishan Parmar  <kishan@linux.ibm.com>
+ 
+ 	Backported from master:
+ 	2026-06-23  Kishan Parmar  <kishan@linux.ibm.com>
+ 
+ 	* config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Handle
+ 	ENB_FUTURE_ALTIVEC and issue a diagnostic requiring -mcpu=future
+ 	and -maltivec.
+ 	(rs6000_builtin_is_supported): Check TARGET_FUTURE && TARGET_ALTIVEC
+ 	for ENB_FUTURE_ALTIVEC built-ins.
+ 	* config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add
+ 	BSTZ_FUTURE_ALTIVEC entry.
+ 	(stanza_map): Add future-altivec stanza mapping.
+ 	(enable_string): Add ENB_FUTURE_ALTIVEC.
+ 	(write_decls): Add ENB_FUTURE_ALTIVEC to the bif_enable enum in the
+ 	generated header file.
+ 
+ 2026-07-02  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	Backported from master:
+ 	2026-06-30  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	* config/loongarch/loongarch.md
+ 	(@stack_protect_combined_set_normal_<mode>): Replace `st.d'
+ 	with `st.<d>', reject stptr.d on LA32 with enabled attribute.
+ 	(@stack_protect_combined_test_internal_<mode>): Replace `ld.d'
+ 	with `ld.<d>', reject ldptr.d on LA32 with enabled attribute.
+ 	(@stack_protect_combined_set_extreme_<mode>): Rename to ...
+ 	(stack_protect_combined_set_extreme): ... here.  Force DImode.
+ 	Add TARGET_ABI_LP64 as the condition.
+ 	(stack_protect_combined_set): Adapt for the change of
+ 	stack_protect_combined_set_extreme.
+ 
+ 2026-07-01  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-06-26  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	PR target/125972
+ 	* config/s390/s390.cc (s390_rtx_costs): Deal with non-compare
+ 	conditions during costing.  Also fix some indentation.
+ 
+ 2026-07-01  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* tree-ssa-structalias.cc (set_uids_in_ptset): If ANYTHING is
+ 	present in the ESCAPED_RETURN solution, record that the global
+ 	solution has an escaped heap if FROM contains a heap variable.
+ 
+ 2026-07-01  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 
+ 	Backported from master:
+ 	2026-06-30  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 		    Surya Kumari Jangala  <jskumari@linux.ibm.com>
+ 
+ 	* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Add logic to
+ 	handle __builtin_ppc_atomic_cas_local.
+ 	* config/rs6000/rs6000-builtins.def: New builtins for
+ 	__builtin_ppc_atomic_cas_local with types.
+ 	* config/rs6000/rs6000-c.cc (altivec_build_resolved_builtin): Handle
+ 	builtins with up to 6 arguments.
+ 	* config/rs6000/rs6000-overload.def: Overload builtin for signed/unsiged
+ 	char, short, int, long, __int128.
+ 	* config/rs6000/rs6000-protos.h (rs6000_expand_atomic_compare_and_swap): Add
+ 	additional parameter 'local' to the prototype.
+ 	* config/rs6000/rs6000.cc (emit_load_locked): Add new parameter. Pass new
+ 	parameter to generate load-locked instruction.
+ 	(rs6000_expand_atomic_compare_and_swap): Add new parameter. Call
+ 	emit_load_locked() with additional parameter value of EH bit.
+ 	(rs6000_expand_atomic_exchange): Pass EH value 0 to emit_load_locked().
+ 	(rs6000_expand_atomic_op): Likewise.
+ 	* config/rs6000/sync.md (load_locked<mode>): Add new operand in RTL template.
+ 	Specify EH bit in the larx instruction.
+ 	(load_locked<QHI:mode>_si): Likewise.
+ 	(load_lockedpti): Likewise.
+ 	(load_lockedti): Add new operand in RTL template. Pass EH bit to
+ 	gen_load_lockedpti().
+ 	(atomic_compare_and_swap<mode>): Pass new parameter 'false' to
+ 	rs6000_expand_atomic_compare_and_swap.
+ 	(atomic_compare_and_swap_local<mode>): New define_expand.
+ 	* doc/extend.texi: Add documentation for new builtin.
+ 
+ 2026-07-01  Haochen Jiang  <haochen.jiang@intel.com>
+ 
+ 	* config/i386/i386.h (PTA_DIAMONDRAPIDS): Remove PTA_AMX_TF32.
+ 	* doc/invoke.texi: Correct documentation.
+ 
+ 2026-07-01  Xin Liu  <liulxx@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-06-23  Xin Liu  <liulxx@hygon.cn>
+ 
+ 	* common/config/i386/cpuinfo.h (get_hygon_cpu): Detect HYGON
+ 	Family 18h model 8 as c86-4g-m8.
+ 	* common/config/i386/i386-common.cc (processor_names): Add
+ 	c86-4g-m8.
+ 	(processor_alias_table): Likewise.
+ 	* common/config/i386/i386-cpuinfo.h (enum processor_subtypes): Add
+ 	HYGONFAM18H_C86_4G_M8.
+ 	* config.gcc: Add c86-4g-m8 to supported x86 CPUs and handle
+ 	c86_4g_m8 target triples.
+ 	* config/i386/c86-4g-m7.md: Rename to ...
+ 	* config/i386/c86-4g-m7m8.md: ... this and extend shared c86-4g-m7
+ 	scheduling reservations to c86-4g-m8.
+ 	(c86_4g_m8_imovx_cwde): New reservation.
+ 	(c86_4g_m7_imov_xchg): Add c86_4g_m8 to CPU attribute.
+ 	(c86_4g_m7_imov_xchg_load): Ditto.
+ 	(c86_4g_m7_imov): Ditto.
+ 	(c86_4g_m7_imov_load): Ditto.
+ 	(c86_4g_m7_imov_store): Ditto.
+ 	(c86_4g_m7_push): Ditto.
+ 	(c86_4g_m7_push_mem): Ditto.
+ 	(c86_4g_m7_pop): Ditto.
+ 	(c86_4g_m7_pop_mem): Ditto.
+ 	(c86_4g_m7_imul): Ditto.
+ 	(c86_4g_m7_imul_load): Ditto.
+ 	(c86_4g_m7_idiv): Ditto.
+ 	(c86_4g_m7_idiv_QI): Ditto.
+ 	(c86_4g_m7_idiv_load): Ditto.
+ 	(c86_4g_m7_idiv_QI_load): Ditto.
+ 	(c86_4g_m7_insn): Ditto.
+ 	(c86_4g_m7_insn_load): Ditto.
+ 	(c86_4g_m7_insn_store): Ditto.
+ 	(c86_4g_m7_insn2_store): Ditto.
+ 	(c86_4g_m7_insn_both): Ditto.
+ 	(c86_4g_m7_setcc): Ditto.
+ 	(c86_4g_m7_setcc_load): Ditto.
+ 	(c86_4g_m7_setcc_store): Ditto.
+ 	(c86_4g_m7_alu1_double): Ditto.
+ 	(c86_4g_m7_alu1_double_load): Ditto.
+ 	(c86_4g_m7_alu1_vector): Ditto.
+ 	(c86_4g_m7_alu1_vector_load): Ditto.
+ 	(c86_4g_m7_alu1_direct): Ditto.
+ 	(c86_4g_m7_alu1_direct_load): Ditto.
+ 	(c86_4g_m7_call): Ditto.
+ 	(c86_4g_m7_branch): Ditto.
+ 	(c86_4g_m7_branch_load): Ditto.
+ 	(c86_4g_m7_lea): Ditto.
+ 	(c86_4g_m7_leave): Ditto.
+ 	(c86_4g_m7_str): Ditto.
+ 	(c86_4g_m7_str_load): Ditto.
+ 	(c86_4g_m7_ieu_vector): Ditto.
+ 	(c86_4g_m7_ieu_vector_load): Ditto.
+ 	(c86_4g_m7_sse_insertimm): Ditto.
+ 	(c86_4g_m7_sse_insert): Ditto.
+ 	(c86_4g_m7_fp_cmov): Ditto.
+ 	(c86_4g_m7_fp_mov_direct_load): Ditto.
+ 	(c86_4g_m7_fp_mov_direct_store): Ditto.
+ 	(c86_4g_m7_fp_mov_double_load): Ditto.
+ 	(c86_4g_m7_fp_mov_double_store): Ditto.
+ 	(c86_4g_m7_fp_mov_direct): Ditto.
+ 	(c86_4g_m7_fp_sqrt): Ditto.
+ 	(c86_4g_m7_fp_spc_direct): Ditto.
+ 	(c86_4g_m7_fp_spc): Ditto.
+ 	(c86_4g_m7_fp_op_mul): Ditto.
+ 	(c86_4g_m7_fp_op_mul_load): Ditto.
+ 	(c86_4g_m7_fp_op_imul_load): Ditto.
+ 	(c86_4g_m7_fp_div): Ditto.
+ 	(c86_4g_m7_fp_div_load): Ditto.
+ 	(c86_4g_m7_fp_idiv_load): Ditto.
+ 	(c86_4g_m7_fp_fsgn): Ditto.
+ 	(c86_4g_m7_fp_fcmp): Ditto.
+ 	(c86_4g_m7_fp_fcmp_load): Ditto.
+ 	(c86_4g_m7_fp_mmx): Ditto.
+ 	(c86_4g_m7_mmx_add_cmp): Ditto.
+ 	(c86_4g_m7_mmx_add_cmp_load): Ditto.
+ 	(c86_4g_m7_mmx_cvt): Ditto.
+ 	(c86_4g_m7_mmx_cvt_load): Ditto.
+ 	(c86_4g_m7_mmx_shift): Ditto.
+ 	(c86_4g_m7_mmx_shift_load): Ditto.
+ 	(c86_4g_m7_mmx_shift_avg): Ditto.
+ 	(c86_4g_m7_mmx_shift_avg_load): Ditto.
+ 	(c86_4g_m7_mmx_shift_sadbw): Ditto.
+ 	(c86_4g_m7_mmx_shift_sadbw_load): Ditto.
+ 	(c86_4g_m7_mmx_mov): Ditto.
+ 	(c86_4g_m7_mmx_mov_store): Ditto.
+ 	(c86_4g_m7_mmx_mov_load): Ditto.
+ 	(c86_4g_m7_mmx_mul): Ditto.
+ 	(c86_4g_m7_mmx_mul_load): Ditto.
+ 	(c86_4g_m7_sse_pinsr_reg): Ditto.
+ 	(c86_4g_m7_sse_pinsr_reg_load): Ditto.
+ 	(c86_4g_m7_avx_vpinsr_reg): Ditto.
+ 	(c86_4g_m7_avx_vpinsr_reg_load): Ditto.
+ 	(c86_4g_m7_avx512_perm_xmm): Ditto.
+ 	(c86_4g_m7_avx512_perm_xmm_opload): Ditto.
+ 	(c86_4g_m7_avx512_permi2_ymm): Ditto.
+ 	(c86_4g_m7_avx512_permi2_zmm): Ditto.
+ 	(c86_4g_m7_avx512_permi2_ymm_load): Ditto.
+ 	(c86_4g_m7_avx512_permi2_zmm_load): Ditto.
+ 	(c86_4g_m7_avx512_perm_zmm_imm): Ditto.
+ 	(c86_4g_m7_avx512_perm_zmm_imm_load): Ditto.
+ 	(c86_4g_m7_avx512_perm_zmm_noimm): Ditto.
+ 	(c86_4g_m7_sse_perm_zmm_noimm_load): Ditto.
+ 	(c86_4g_m7_avx512_insertx_ymm): Ditto.
+ 	(c86_4g_m7_avx512_insertx_ymem): Ditto.
+ 	(c86_4g_m7_avx512_insertx_zxmm): Ditto.
+ 	(c86_4g_m7_avx512_insertx_zxmem): Ditto.
+ 	(c86_4g_m7_avx512_insertx_zymm): Ditto.
+ 	(c86_4g_m7_avx512_insertx_zymem): Ditto.
+ 	(c86_4g_m7_avx_insertx_ymm): Ditto.
+ 	(c86_4g_m7_avx_insertx_ymem): Ditto.
+ 	(c86_4g_m7_avx512_shuf_xymm): Ditto.
+ 	(c86_4g_m7_avx512_shuf_zmm): Ditto.
+ 	(c86_4g_m7_avx512_shuf_xymem): Ditto.
+ 	(c86_4g_m7_avx512_shuf_zmem): Ditto.
+ 	(c86_4g_m7_sselogic_xymm): Ditto.
+ 	(c86_4g_m7_sselogic_xymm_load): Ditto.
+ 	(c86_4g_m7_avx512_cmpestr): Ditto.
+ 	(c86_4g_m7_avx512_cmpestr_load): Ditto.
+ 	(c86_4g_m7_avx512_log): Ditto.
+ 	(c86_4g_m7_avx512_log_load): Ditto.
+ 	(c86_4g_m7_avx512_vdbpsadbw_xymm): Ditto.
+ 	(c86_4g_m7_avx512_vdbpsadbw_xymem): Ditto.
+ 	(c86_4g_m7_avx512_vdbpsadbw_zmm): Ditto.
+ 	(c86_4g_m7_avx512_vdbpsadbw_zmem): Ditto.
+ 	(c86_4g_m7_avx512_abs): Ditto.
+ 	(c86_4g_m7_avx512_abs_load): Ditto.
+ 	(c86_4g_m7_avx_sign): Ditto.
+ 	(c86_4g_m7_avx_sign_load): Ditto.
+ 	(c86_4g_m7_avx_blend): Ditto.
+ 	(c86_4g_m7_avx_blend_load): Ditto.
+ 	(c86_4g_m7_avx512_aes): Ditto.
+ 	(c86_4g_m7_avx512_aes_load): Ditto.
+ 	(c86_4g_m7_avx_aes): Ditto.
+ 	(c86_4g_m7_avx_aes_load): Ditto.
+ 	(c86_4g_m7_extr): Ditto.
+ 	(c86_4g_m7_extr_store): Ditto.
+ 	(c86_4g_m7_avx_ssecomi_comi): Ditto.
+ 	(c86_4g_m7_avx_ssecomi_comi_load): Ditto.
+ 	(c86_4g_m7_avx_ssecomi_test): Ditto.
+ 	(c86_4g_m7_avx_ssecomi_test_load): Ditto.
+ 	(c86_4g_m7_avx512_imul): Ditto.
+ 	(c86_4g_m7_avx512_imul_mem): Ditto.
+ 	(c86_4g_m7_avx_imul): Ditto.
+ 	(c86_4g_m7_avx_imul_mem): Ditto.
+ 	(c86_4g_m7_avx512_mov_vmov): Ditto.
+ 	(c86_4g_m7_avx512_mov_vmov_store): Ditto.
+ 	(c86_4g_m7_avx512_mov_vmov_load): Ditto.
+ 	(c86_4g_m7_avx512_vpmovx_y): Ditto.
+ 	(c86_4g_m7_avx512_vpmovx_y_load): Ditto.
+ 	(c86_4g_m7_avx512_vpmovx_z): Ditto.
+ 	(c86_4g_m7_avx512_vpmovx_z_load): Ditto.
+ 	(c86_4g_m7_avx512_vpmovx_x): Ditto.
+ 	(c86_4g_m7_avx512_vpmovx_x_load): Ditto.
+ 	(c86_4g_m7_avx_vpmovx_xx): Ditto.
+ 	(c86_4g_m7_avx_vpmovx_xx_load): Ditto.
+ 	(c86_4g_m7_avx512_expand): Ditto.
+ 	(c86_4g_m7_avx512_expand_load): Ditto.
+ 	(c86_4g_m7_avx512_expand_z): Ditto.
+ 	(c86_4g_m7_avx512_expand_z_load): Ditto.
+ 	(c86_4g_m7_avx512_movnt_load): Ditto.
+ 	(c86_4g_m7_avx512_movnt_store): Ditto.
+ 	(c86_4g_m7_sse_movnt_store): Ditto.
+ 	(c86_4g_m7_sse_movnt): Ditto.
+ 	(c86_4g_m7_avx512_blendv): Ditto.
+ 	(c86_4g_m7_avx512_blendv_load): Ditto.
+ 	(c86_4g_m7_sse_mov2): Ditto.
+ 	(c86_4g_m7_sse_mov2_load): Ditto.
+ 	(c86_4g_m7_avx512_sseishft_aligr): Ditto.
+ 	(c86_4g_m7_avx512_sseishft_aligr_load): Ditto.
+ 	(c86_4g_m7_avx512_sseishft_vshift): Ditto.
+ 	(c86_4g_m7_avx512_sseishft_vshift_load): Ditto.
+ 	(c86_4g_m7_avx512_sseadd_maxmin): Ditto.
+ 	(c86_4g_m7_avx512_sseadd_maxmin_load): Ditto.
+ 	(c86_4g_m7_avx_sseadd_maxmin): Ditto.
+ 	(c86_4g_m7_avx_sseadd_maxmin_load): Ditto.
+ 	(c86_4g_m7_sse_sseadd_maxmin): Ditto.
+ 	(c86_4g_m7_sse_sseadd_maxmin_load): Ditto.
+ 	(c86_4g_m7_avx512_sseadd): Ditto.
+ 	(c86_4g_m7_avx512_sseadd_load): Ditto.
+ 	(c86_4g_m7_avx_sseadd_hplus): Ditto.
+ 	(c86_4g_m7_avx_sseadd_hplus_load): Ditto.
+ 	(c86_4g_m7_avx512_sseiadd_madd): Ditto.
+ 	(c86_4g_m7_avx512_sseiadd_madd_mem): Ditto.
+ 	(c86_4g_m7_avx_sseiadd_sadbw): Ditto.
+ 	(c86_4g_m7_avx_sseiadd_sadbw_mem): Ditto.
+ 	(c86_4g_m7_sse_sseiadd_sadbw): Ditto.
+ 	(c86_4g_m7_sse_sseiadd_sadbw_mem): Ditto.
+ 	(c86_4g_m7_sse_sseiadd_madd): Ditto.
+ 	(c86_4g_m7_sse_sseiadd_madd_mem): Ditto.
+ 	(c86_4g_m7_avx512_sseiadd_avg): Ditto.
+ 	(c86_4g_m7_avx512_sseiadd_avg_load): Ditto.
+ 	(c86_4g_m7_avx_sseiadd_hplus): Ditto.
+ 	(c86_4g_m7_avx_sseiadd_hplus_load): Ditto.
+ 	(c86_4g_m7_sse_sseiadd_hplus): Ditto.
+ 	(c86_4g_m7_sse_sseiadd_hplus_load): Ditto.
+ 	(c86_4g_m8_avx512_ssemul): New reservation.
+ 	(c86_4g_m8_avx512_ssemul_load): Ditto.
+ 	(c86_4g_m7_avx512_ssediv_x): Add c86_4g_m8 to CPU attribute.
+ 	(c86_4g_m7_avx512_ssediv_xmem): Ditto.
+ 	(c86_4g_m7_avx512_ssediv_y): Ditto.
+ 	(c86_4g_m7_avx512_ssediv_ymem): Ditto.
+ 	(c86_4g_m7_avx512_ssediv_z): Ditto.
+ 	(c86_4g_m7_avx512_ssediv_zmem): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_load): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_z): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_z_load): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_vp): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_vp_load): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_vp_z): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_vp_z_load): Ditto.
+ 	(c86_4g_m7_avx_ssecmp_vp): Ditto.
+ 	(c86_4g_m7_avx_ssecmp_vp_load): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_test): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_test_load): Ditto.
+ 	(c86_4g_m7_avx512_ssecvt_xy): Ditto.
+ 	(c86_4g_m7_avx512_ssecvt_xy_load): Ditto.
+ 	(c86_4g_m7_avx512_ssecvt_y_z): Ditto.
+ 	(c86_4g_m7_avx512_ssecvt_y_z_load): Ditto.
+ 	(c86_4g_m7_avx512_ssecvt_z): Ditto.
+ 	(c86_4g_m7_avx512_ssecvt_z_load): Ditto.
+ 	(c86_4g_m7_avx_ssecvt): Ditto.
+ 	(c86_4g_m7_avx_ssecvt_load): Ditto.
+ 	(c86_4g_m7_sse_ssecvt_pspi): Ditto.
+ 	(c86_4g_m7_sse_ssecvt_pspi_load): Ditto.
+ 	(c86_4g_m7_sse_ssecvt_pi): Ditto.
+ 	(c86_4g_m7_sse_ssecvt_pi_load): Ditto.
+ 	(c86_4g_m8_avx512_muladd): New reservation.
+ 	(c86_4g_m8_avx512_muladd_load): Ditto.
+ 	(c86_4g_m7_avx512_muladd_madd): Add c86_4g_m8 to CPU attribute.
+ 	(c86_4g_m7_avx512_muladd_madd_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_range): Ditto.
+ 	(c86_4g_m7_avx512_sse_range_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_x): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_x_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_y): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_y_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_z): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_z_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_class): Ditto.
+ 	(c86_4g_m7_avx512_sse_class_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_class_z): Ditto.
+ 	(c86_4g_m7_avx512_sse_class_z_load): Ditto.
+ 	(c86_4g_m7_avx_sse): Ditto.
+ 	(c86_4g_m7_avx_sse_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_x): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_xload): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_y): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_yload): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_z): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_zload): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_x): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_xload): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_y): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_yload): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_z): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_zload): Ditto.
+ 	(c86_4g_m7_avx512_msklog): Ditto.
+ 	(c86_4g_m7_avx512_msklog_vector): Ditto.
+ 	(c86_4g_m7_avx512_mskmov_reg_k): Ditto.
+ 	(c86_4g_m7_avx512_mskmov_xy_k): Ditto.
+ 	(c86_4g_m7_avx512_mskmov_z_k): Ditto.
+ 	(c86_4g_m7_avx512_mskmov_k_k): Ditto.
+ 	(c86_4g_m7_avx512_mskmov_k_reg): Ditto.
+ 	(c86_4g_m7_avx512_mskmov_k_m): Ditto.
+ 	* config/i386/driver-i386.cc (host_detect_local_cpu): Detect
+ 	c86-4g-m8.
+ 	* config/i386/i386-c.cc (ix86_target_macros_internal): Define
+ 	c86-4g-m8 arch and tune macros.
+ 	* config/i386/i386-options.cc (m_C86_4G_M8): New macro.
+ 	(m_C86_4G): Include m_C86_4G_M8.
+ 	(processor_cost_table): Add c86_4g_m8_cost.
+ 	* config/i386/i386.cc (ix86_reassociation_width): Handle
+ 	PROCESSOR_C86_4G_M8.
+ 	* config/i386/i386.h (enum processor_type): Add
+ 	PROCESSOR_C86_4G_M8.
+ 	(PTA_C86_4G_M8): New.
+ 	* config/i386/i386.md: Add c86_4g_m8 to cpu attribute.
+ 	* config/i386/x86-tune-costs.h (c86_4g_m8_cost): New.
+ 	* config/i386/x86-tune-sched.cc (ix86_issue_rate): Handle
+ 	PROCESSOR_C86_4G_M8.
+ 	(ix86_adjust_cost): Likewise.
+ 	* config/i386/x86-tune.def (X86_TUNE_USE_SCATTER_2PARTS): Include
+ 	m_C86_4G_M8.
+ 	(X86_TUNE_USE_SCATTER_4PARTS): Likewise.
+ 	(X86_TUNE_USE_SCATTER_8PARTS): Likewise.
+ 	(X86_TUNE_SSE_REDUCTION_PREFER_PSHUF): Likewise.
+ 	(X86_TUNE_AVX512_SPLIT_REGS): Likewise.
+ 	(X86_TUNE_AVX512_MOVE_BY_PIECES): Likewise.
+ 	(X86_TUNE_AVX512_MASKED_EPILOGUES): Likewise.
+ 	* doc/extend.texi: Document c86-4g-m8 for __builtin_cpu_is.
+ 	* doc/invoke.texi: Document c86-4g-m8.
+ 
+ 2026-07-01  Zhongjie Guo  <guozhongjie@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-06-17  Zhongjie Guo  <guozhongjie@hygon.cn>
+ 
+ 	* config/i386/x86-tune-costs.h (c86_4g_m7_cost): Increase
+ 	512-bit load/store and unaligned load/store costs.
+ 
+ 2026-07-01  Xin Liu  <liulxx@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-06-17  Xin Liu  <liulxx@hygon.cn>
+ 
+ 	* config/i386/c86-4g-m7.md (c86_4g_m7_imov_xchg): Adjust
+ 	reservation units.
+ 	(c86_4g_m7_imov_xchg_load): Ditto.
+ 	(c86_4g_m7_call): Ditto.
+ 	(c86_4g_m7_branch): Ditto.
+ 	(c86_4g_m7_branch_load): Ditto.
+ 	(c86_4g_m7_fp_spc_direct): Add missing store unit.
+ 	(c86_4g_m7_sse_pinsr_reg): Adjust reservation units.
+ 	(c86_4g_m7_avx512_insertx_ymm): Ditto.
+ 	(c86_4g_m7_avx512_insertx_ymem): Ditto.
+ 	(c86_4g_m7_avx512_insertx_zxmm): Ditto.
+ 	(c86_4g_m7_avx512_insertx_zxmem): Ditto.
+ 	(c86_4g_m7_avx512_abs_load): Add missing store unit.
+ 	(c86_4g_m7_avx_sign): Use combined FPU reservation.
+ 	(c86_4g_m7_avx_sign_load): Ditto.
+ 	(c86_4g_m7_avx_aes): Ditto.
+ 	(c86_4g_m7_avx_aes_load): Ditto.
+ 	(c86_4g_m7_extr_load): Rename to ...
+ 	(c86_4g_m7_extr_store): ... this and restrict to store memory.
+ 	(c86_4g_m7_avx_imul): Use combined FPU reservation.
+ 	(c86_4g_m7_avx_imul_mem): Ditto.
+ 	(c86_4g_m7_avx512_vpmovx_y_load): Add missing store unit.
+ 	(c86_4g_m7_avx_vpmovx_xx_load): Ditto.
+ 	(c86_4g_m7_avx512_sseadd_maxmin_xy): Rename to ...
+ 	(c86_4g_m7_avx512_sseadd_maxmin): ... this and simplify
+ 	memory attribute check.
+ 	(c86_4g_m7_avx512_sseadd_maxmin_xy_load): Rename to ...
+ 	(c86_4g_m7_avx512_sseadd_maxmin_load): ... this and simplify
+ 	memory attribute check.
+ 	(c86_4g_m7_avx512_sseadd_xy): Rename to ...
+ 	(c86_4g_m7_avx512_sseadd): ... this.
+ 	(c86_4g_m7_avx512_sseadd_xy_load): Rename to ...
+ 	(c86_4g_m7_avx512_sseadd_load): ... this.
+ 	(c86_4g_m7_sse_sseiadd_sadbw): Use combined FPU reservation.
+ 	(c86_4g_m7_sse_sseiadd_sadbw_mem): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_vp_z): Adjust reservation units.
+ 	(c86_4g_m7_avx512_ssecmp_vp_z_load): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_test_load): Ditto.
+ 	(c86_4g_m7_avx512_mskmov_k_m): Adjust latency.
+ 
+ 2026-06-30  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-06-12  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	PR rtl-optimization/125173
+ 	* ira.cc (combine_and_move_insns): Allow multiple uses within
+ 	an insn.
+ 
+ 2026-06-30  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	Backported from master:
+ 	2026-04-22  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	PR target/124908
+ 	* config/aarch64/aarch64-sve-builtins-base.cc
+ 	(svld1rq_impl::fold): When the SVE vector length equals the
+ 	quadword width, emit VIEW_CONVERT_EXPR instead of VEC_PERM_EXPR.
+ 
+ 2026-06-30  Alfie Richards  <alfie.richards@arm.com>
+ 
+ 	PR target/125838
+ 	* config/aarch64/aarch64.cc (aarch64_fntype_abi): Fall back to
+ 	AAPCS for preserve_none variadic calls.
+ 
+ 2026-06-30  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2026-06-21  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR target/125883
+ 	* config/i386/i386-features.cc (ix86_broadcast_inner): Skip JUMP
+ 	from asm goto.
+ 
+ 2026-06-29  Alex Coplan  <alex.coplan@arm.com>
+ 
+ 	Backported from master:
+ 	2026-06-23  Alex Coplan  <alex.coplan@arm.com>
+ 
+ 	PR target/125818
+ 	* config/aarch64/aarch64-sve-builtins-base.cc (svset_impl::fold): Fix
+ 	unsharing to ensure the returned stmt has the exact same lhs as the
+ 	original.
+ 
+ 2026-06-29  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-29  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR target/125469
+ 	* config/i386/i386.md (*add<mode>_1<nf_name>): Revert 2026-05-28
+ 	changes.
+ 	(define_split from *add<mode>_1_nf to *lea<mode>): Set INSN_CODE
+ 	to -1 if <LEAMODE> and <MODE> are the same.
+ 
+ 2026-06-29  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-05-28  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR target/125469
+ 	* config/i386/i386.md (*add<mode>_1<nf_name>): Don't return "#" for
+ 	the lea non-TARGET_APX_NDD case, instead emit a lea directly.
+ 
+ 2026-06-29  vekumar  <Venkataramanan.Kumar@amd.com>
+ 
+ 	Backported from master:
+ 	2026-06-26  vekumar  <Venkataramanan.Kumar@amd.com>
+ 
+ 	PR target/125949
+ 	* config/i386/i386.md ("isa"): Add avxvnniint8.
+ 	("enabled"): Adjust for avxvnniint8.
+ 	* config/i386/sse.md (vpdp<vpdotprodtype>_<mode>): Adjust for
+ 	AVXVNNIINT8.
+ 
+ 2026-06-27  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-27  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR target/125992
+ 	* config/s390/s390.md (*brx_stage1_<GPR:mode>): Add CC_REGNUM clobber.
+ 
  2026-06-25  Peter Bergner  <bergner@tenstorrent.com>
  
  	* config/riscv/riscv-cores.def (RISCV_TUNE): Add tt-ascalon-x.
diff -Nrcpad gcc-16-20260627/gcc/DATESTAMP gcc-16-20260704/gcc/DATESTAMP
*** gcc-16-20260627/gcc/DATESTAMP	Sat Jun 27 22:32:05 2026
--- gcc-16-20260704/gcc/DATESTAMP	Sat Jul  4 22:32:06 2026
***************
*** 1 ****
! 20260627
--- 1 ----
! 20260704
diff -Nrcpad gcc-16-20260627/gcc/ada/ChangeLog gcc-16-20260704/gcc/ada/ChangeLog
*** gcc-16-20260627/gcc/ada/ChangeLog	Sat Jun 27 22:32:05 2026
--- gcc-16-20260704/gcc/ada/ChangeLog	Sat Jul  4 22:32:06 2026
***************
*** 1,3 ****
--- 1,36 ----
+ 2026-06-29  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* exp_util.ads (Find_Optional_Prim_Op): Add Controlled_Op parameter
+ 	defaulting to False.
+ 	* exp_util.adb (Find_Optional_Prim_Op): Likewise.  When it is set to
+ 	True, test whether the primitive has the signature of the controlled
+ 	primitives.
+ 	* sem_ch13.adb (Resolve_Finalization_Procedure): Reset Is_Overloaded
+ 	once an interpretation has been selected among the set.
+ 
+ 2026-06-29  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* sem_ch3.adb (Find_Type_Of_Object): In the subtype indication case
+ 	for a stand-alone object, invoke Process_Subtype during preanalysis
+ 	instead of partially reimplementing it.
+ 	* sem_ch5.ads (Has_Sec_Stack_Call): Move back declaration to...
+ 	* sem_ch5.adb (Has_Sec_Stack_Call): ...here.
+ 	* sem_ch4.adb (Analyze_Expression_With_Actions): Deal with transient
+ 	scopes created during analysis.
+ 	* sem_res.adb: Add clauses for Sem_Ch9 package.
+ 	(Resolve_Declare_Expression): Streamline and deal with transient
+ 	scopes created during resolution.
+ 
+ 2026-06-29  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* exp_ch4.adb (Expand_N_Expression_With_Actions): Create a temporary
+ 	only for types that can be copied, and replace the EWA node by its
+ 	expression for other types.
+ 	* exp_ch6.adb (Expand_Ctrl_Function_Call): Bail out when the parent
+ 	is an EWA node.
+ 	* sem_ch3.adb (OK_For_Limited_Init_In_05): Recurse on the expression
+ 	of an EWA node.
+ 
  2026-06-19  Eric Botcazou  <ebotcazou@adacore.com>
  
  	* sem_ch12.adb (Analyze_Generic_Package_Declaration): Do not set the
diff -Nrcpad gcc-16-20260627/gcc/ada/exp_ch4.adb gcc-16-20260704/gcc/ada/exp_ch4.adb
*** gcc-16-20260627/gcc/ada/exp_ch4.adb	Sat Jun 27 22:32:05 2026
--- gcc-16-20260704/gcc/ada/exp_ch4.adb	Sat Jul  4 22:32:06 2026
*************** package body Exp_Ch4 is
*** 5606,5662 ****
     --------------------------------------
  
     procedure Expand_N_Expression_With_Actions (N : Node_Id) is
!       Acts : constant List_Id := Actions (N);
  
!       procedure Force_Boolean_Evaluation (Expr : Node_Id);
!       --  Force the evaluation of Boolean expression Expr
  
!       ------------------------------
!       -- Force_Boolean_Evaluation --
!       ------------------------------
  
!       procedure Force_Boolean_Evaluation (Expr : Node_Id) is
!          Loc       : constant Source_Ptr := Sloc (N);
!          Flag_Decl : Node_Id;
!          Flag_Id   : Entity_Id;
  
        begin
!          --  Relocate the expression to the actions list by capturing its value
!          --  in a Boolean flag. Generate:
!          --    Flag : constant Boolean := Expr;
  
!          Flag_Id := Make_Temporary (Loc, 'F');
  
!          Flag_Decl :=
!            Make_Object_Declaration (Loc,
!              Defining_Identifier => Flag_Id,
!              Constant_Present    => True,
!              Object_Definition   => New_Occurrence_Of (Standard_Boolean, Loc),
!              Expression          => Relocate_Node (Expr));
  
!          Append (Flag_Decl, Acts);
!          Analyze (Flag_Decl);
  
!          --  Replace the expression with a reference to the flag
  
!          Rewrite (Expression (N), New_Occurrence_Of (Flag_Id, Loc));
!          Analyze (Expression (N));
!       end Force_Boolean_Evaluation;
  
!    --  Start of processing for Expand_N_Expression_With_Actions
  
!    begin
!       --  Do not evaluate the expression when it denotes an entity because the
!       --  expression_with_actions node will be replaced by the reference.
  
!       if Is_Entity_Name (Expression (N)) then
!          null;
  
!       --  Do not evaluate the expression when there are no actions because the
!       --  expression_with_actions node will be replaced by the expression.
  
!       elsif Is_Empty_List (Acts) then
!          null;
  
        --  Force the evaluation of the expression by capturing its value in a
        --  temporary. This ensures that aliases of transient objects do not leak
--- 5606,5681 ----
     --------------------------------------
  
     procedure Expand_N_Expression_With_Actions (N : Node_Id) is
!       Acts : constant List_Id    := Actions (N);
!       Loc  : constant Source_Ptr := Sloc (N);
!       Typ  : constant Entity_Id  := Etype (N);
  
!       function Is_Copy_Type (Typ : Entity_Id) return Boolean;
!       --  Return True if we can copy objects of this type when expanding the
!       --  node. The function must return False for limited types for semantic
!       --  reasons, and more generally should do so for all by-reference types.
!       --  Of course the run-time performance of the copy operation should also
!       --  be taken into account, but the expansion of conditional expressions
!       --  may choose to create EWA nodes instead of conditional statements to
!       --  deal with the actions, in which case these EWA nodes also need to be
!       --  preserved for semantic reasons. In practice, this means that the
!       --  subset of types accepted by this Is_Copy_Type predicate must contain
!       --  the union of the subsets of types accepted by its homonyms in the
!       --  Expand_N_Case_Expression and Expand_N_If_Expression procedures, in
!       --  other words must return True when at least one of them returns true.
!       --  This implementation is that of Expand_N_If_Expression.Is_Copy_Type,
!       --  which already accepts a superset of the types accepted by its twin
!       --  Expand_N_Case_Expression.Is_Copy_Type predicate.
  
!       ------------------
!       -- Is_Copy_Type --
!       ------------------
  
!       function Is_Copy_Type (Typ : Entity_Id) return Boolean is
!          Utyp : constant Entity_Id := Underlying_Type (Typ);
  
        begin
!          return Is_Definite_Subtype (Utyp)
!            and then not Is_By_Reference_Type (Utyp);
!       end Is_Copy_Type;
  
!       --  Local variables
  
!       Temp_Decl : Node_Id;
!       Temp_Id   : Entity_Id;
!       Temp_Ref  : Node_Id;
  
!    --  Start of processing for Expand_N_Expression_With_Actions
  
!    begin
!       --  A check is first needed since the subtype of the EWA node and the
!       --  subtype of the expression may differ (for example, the EWA node
!       --  may have a null-excluding access subtype).
  
!       Apply_Constraint_Check (Expression (N), Typ);
  
!       --  Deal with case where there are no actions. In this case we simply
!       --  rewrite the node with its expression since we don't need the actions
!       --  and the specification of this node does not allow a null action list.
  
!       --  Note: we use Rewrite instead of Replace, because Codepeer is using
!       --  the expanded tree and relying on being able to retrieve the original
!       --  tree in cases like this. This raises a whole lot of issues of whether
!       --  we have problems elsewhere, which will be addressed in the future???
  
!       if Is_Empty_List (Acts) then
!          Rewrite (N, Relocate_Node (Expression (N)));
!          Analyze_And_Resolve (N, Typ);
  
!       --  Do not evaluate the expression when it denotes an entity because the
!       --  EWA node will simply be replaced by the reference. Likewise if it was
!       --  rewritten as a raise node. But nevertheless process transient objects
!       --  found within the actions of the EWA node.
  
!       elsif Is_Entity_Name (Expression (N))
!         or else Nkind (Expression (N)) in N_Raise_xxx_Error
!       then
!          Process_Transients_In_Expression (N, Acts);
  
        --  Force the evaluation of the expression by capturing its value in a
        --  temporary. This ensures that aliases of transient objects do not leak
*************** package body Exp_Ch4 is
*** 5682,5723 ****
        --  Once this transformation is performed, it is safe to finalize the
        --  transient object at the end of the actions list.
  
!       --  Note that Force_Evaluation does not remove side effects in operators
!       --  because it assumes that all operands are evaluated and side effect
!       --  free. This is not the case when an operand depends implicitly on the
!       --  transient object through the use of access types.
  
!       elsif Is_Boolean_Type (Etype (Expression (N))) then
!          Force_Boolean_Evaluation (Expression (N));
  
!       --  The expression of an expression_with_actions node may not necessarily
!       --  be Boolean when the node appears in an if expression. In this case do
!       --  the usual forced evaluation to encapsulate potential aliasing.
  
!       else
!          --  A check is also needed since the subtype of the EWA node and the
!          --  subtype of the expression may differ (for example, the EWA node
!          --  may have a null-excluding access subtype).
  
!          Apply_Constraint_Check (Expression (N), Etype (N));
!          Force_Evaluation (Expression (N));
!       end if;
  
!       --  Process transient objects found within the actions of the EWA node
  
!       Process_Transients_In_Expression (N, Acts);
  
!       --  Deal with case where there are no actions. In this case we simply
!       --  rewrite the node with its expression since we don't need the actions
!       --  and the specification of this node does not allow a null action list.
  
!       --  Note: we use Rewrite instead of Replace, because Codepeer is using
!       --  the expanded tree and relying on being able to retrieve the original
!       --  tree in cases like this. This raises a whole lot of issues of whether
!       --  we have problems elsewhere, which will be addressed in the future???
  
!       if Is_Empty_List (Acts) then
           Rewrite (N, Relocate_Node (Expression (N)));
        end if;
     end Expand_N_Expression_With_Actions;
  
--- 5701,5753 ----
        --  Once this transformation is performed, it is safe to finalize the
        --  transient object at the end of the actions list.
  
!       elsif Is_Copy_Type (Typ) then
!          --  Relocate the expression to the actions list by capturing its value
!          --  in a temporary. Generate:
!          --
!          --    Temp : constant Exp_Typ := Exp;
  
!          Temp_Id := Make_Temporary (Loc, 'F');
  
!          Temp_Decl :=
!            Make_Object_Declaration (Loc,
!              Defining_Identifier => Temp_Id,
!              Constant_Present    => True,
!              Object_Definition   =>
!                New_Occurrence_Of (Etype (Expression (N)), Loc),
!              Expression          => Relocate_Node (Expression (N)));
  
!          Append (Temp_Decl, Acts);
!          Analyze (Temp_Decl);
  
!          Temp_Ref := New_Occurrence_Of (Temp_Id, Loc);
  
!          --  Copy the Do_Range_Check flag that may have been set above
  
!          Set_Do_Range_Check (Temp_Ref, Do_Range_Check (Expression (N)));
  
!          --  Replace the expression with a reference to the temporary
  
!          Rewrite (Expression (N), Temp_Ref);
  
!          --  Process transient objects found within the actions of the EWA node
! 
!          Process_Transients_In_Expression (N, Acts);
! 
!       --  Otherwise insert the actions and replace the EWA by its expression.
!       --  This is necessary for limited types, and desirable for by-reference
!       --  types, because we cannot or should not create a temporary for them.
!       --  This means that the management of transient objects is deferred to
!       --  the enclosing context where the actions are inserted.
! 
!       else
!          Insert_Actions (N, Acts);
           Rewrite (N, Relocate_Node (Expression (N)));
+          Analyze_And_Resolve (N, Typ);
+ 
+          --  Note that the result is never static
+ 
+          Set_Is_Static_Expression (N, False);
        end if;
     end Expand_N_Expression_With_Actions;
  
diff -Nrcpad gcc-16-20260627/gcc/ada/exp_ch6.adb gcc-16-20260704/gcc/ada/exp_ch6.adb
*** gcc-16-20260627/gcc/ada/exp_ch6.adb	Sat Jun 27 22:32:05 2026
--- gcc-16-20260704/gcc/ada/exp_ch6.adb	Sat Jul  4 22:32:06 2026
*************** package body Exp_Ch6 is
*** 5755,5760 ****
--- 5755,5766 ----
       --  cause a temporary to be created.
  
     begin
+       --  The decision will be made after the EWA node is expanded
+ 
+       if Nkind (Par) = N_Expression_With_Actions then
+          return;
+       end if;
+ 
        --  Optimization: if the returned value is returned again, then no need
        --  to copy/readjust/finalize, we can just pass the value through (see
        --  Expand_Simple_Function_Return), and thus no attachment is needed.
diff -Nrcpad gcc-16-20260627/gcc/ada/exp_util.adb gcc-16-20260704/gcc/ada/exp_util.adb
*** gcc-16-20260627/gcc/ada/exp_util.adb	Sat Jun 27 22:32:05 2026
--- gcc-16-20260704/gcc/ada/exp_util.adb	Sat Jul  4 22:32:06 2026
*************** package body Exp_Util is
*** 6266,6272 ****
           return Empty;
        end if;
  
!       return Find_Optional_Prim_Op (T, Op_Name);
     end Find_Controlled_Prim_Op;
  
     ------------------------
--- 6266,6272 ----
           return Empty;
        end if;
  
!       return Find_Optional_Prim_Op (T, Op_Name, Controlled_Op => True);
     end Find_Controlled_Prim_Op;
  
     ------------------------
*************** package body Exp_Util is
*** 6920,6930 ****
     ---------------------------
  
     function Find_Optional_Prim_Op
!      (T : Entity_Id; Name : Name_Id) return Entity_Id
     is
        Prim : Elmt_Id;
        Typ  : Entity_Id := T;
-       Op   : Entity_Id;
  
     begin
        if Is_Class_Wide_Type (Typ) then
--- 6920,6932 ----
     ---------------------------
  
     function Find_Optional_Prim_Op
!      (T             : Entity_Id;
!       Name          : Name_Id;
!       Controlled_Op : Boolean := False) return Entity_Id
     is
+       Op   : Entity_Id;
        Prim : Elmt_Id;
        Typ  : Entity_Id := T;
  
     begin
        if Is_Class_Wide_Type (Typ) then
*************** package body Exp_Util is
*** 6946,6959 ****
           Op := Node (Prim);
  
           --  We can retrieve primitive operations by name if it is an internal
!          --  name. For equality we must check that both of its operands have
!          --  the same type, to avoid confusion with user-defined equalities
!          --  than may have a asymmetric signature.
  
           exit when Chars (Op) = Name
             and then
               (Name /= Name_Op_Eq
!                or else Etype (First_Formal (Op)) = Etype (Last_Formal (Op)));
  
           Next_Elmt (Prim);
        end loop;
--- 6948,6970 ----
           Op := Node (Prim);
  
           --  We can retrieve primitive operations by name if it is an internal
!          --  name. For equality, we must check that both of its operands have
!          --  the same type, to avoid confusion with user-defined equalities,
!          --  which may have an asymmetric signature. For controlled operations,
!          --  we check that the primitive is a procedure with a single In Out
!          --  parameter of a non-access type.
  
           exit when Chars (Op) = Name
             and then
               (Name /= Name_Op_Eq
!                or else Etype (First_Formal (Op)) = Etype (Last_Formal (Op)))
!            and then
!              (not Controlled_Op
!                or else
!                  (Ekind (Op) = E_Procedure
!                    and then Ekind (First_Formal (Op)) = E_In_Out_Parameter
!                    and then not Is_Access_Type (Etype (First_Formal (Op)))
!                    and then No (Next_Formal (First_Formal (Op)))));
  
           Next_Elmt (Prim);
        end loop;
diff -Nrcpad gcc-16-20260627/gcc/ada/exp_util.ads gcc-16-20260704/gcc/ada/exp_util.ads
*** gcc-16-20260627/gcc/ada/exp_util.ads	Sat Jun 27 22:32:05 2026
--- gcc-16-20260704/gcc/ada/exp_util.ads	Sat Jul  4 22:32:06 2026
*************** package Exp_Util is
*** 651,657 ****
     --  although they are not master constructs in the language.
  
     function Find_Optional_Prim_Op
!      (T : Entity_Id; Name : Name_Id) return Entity_Id;
     function Find_Optional_Prim_Op
       (T    : Entity_Id;
        Name : TSS_Name_Type) return Entity_Id;
--- 651,663 ----
     --  although they are not master constructs in the language.
  
     function Find_Optional_Prim_Op
!      (T             : Entity_Id;
!       Name          : Name_Id;
!       Controlled_Op : Boolean := False) return Entity_Id;
!    --  Same as Find_Prim_Op but, if Controlled_Op is True, returns a primitive
!    --  only if it has the signature of the three primitives of controlled types
!    --  Initialize/Adjust/Finalize, and returns Empty if not found.
! 
     function Find_Optional_Prim_Op
       (T    : Entity_Id;
        Name : TSS_Name_Type) return Entity_Id;
diff -Nrcpad gcc-16-20260627/gcc/ada/sem_ch13.adb gcc-16-20260704/gcc/ada/sem_ch13.adb
*** gcc-16-20260627/gcc/ada/sem_ch13.adb	Sat Jun 27 22:32:05 2026
--- gcc-16-20260704/gcc/ada/sem_ch13.adb	Sat Jul  4 22:32:06 2026
*************** package body Sem_Ch13 is
*** 17926,17931 ****
--- 17926,17932 ----
              while Present (It.Typ) loop
                 if Is_Finalizable_Primitive (It.Nam) then
                    Set_Entity (N, It.Nam);
+                   Set_Is_Overloaded (N, False);
                    return True;
                 end if;
  
diff -Nrcpad gcc-16-20260627/gcc/ada/sem_ch3.adb gcc-16-20260704/gcc/ada/sem_ch3.adb
*** gcc-16-20260627/gcc/ada/sem_ch3.adb	Sat Jun 27 22:32:05 2026
--- gcc-16-20260704/gcc/ada/sem_ch3.adb	Sat Jul  4 22:32:06 2026
*************** package body Sem_Ch3 is
*** 19138,19146 ****
        elsif Nkind (P) /= N_Component_Declaration
          and then Def_Kind = N_Subtype_Indication
        then
-          --  Base name of subtype on object name, which will be unique in
-          --  the current scope.
- 
           --  If this is a duplicate declaration, return base type, to avoid
           --  generating duplicate anonymous types.
  
--- 19138,19143 ----
*************** package body Sem_Ch3 is
*** 19149,19201 ****
              return Entity (Subtype_Mark (Obj_Def));
           end if;
  
           Nam :=
              New_External_Name
               (Chars (Defining_Identifier (Related_Nod)), 'S', 0, 'T');
  
           T := Make_Defining_Identifier (Sloc (P), Nam);
  
-          --  If In_Spec_Expression, for example within a pre/postcondition,
-          --  provide enough information for use of the subtype without
-          --  depending on full analysis and freezing, which will happen when
-          --  building the corresponding subprogram.
- 
-          if In_Spec_Expression then
-             Analyze (Subtype_Mark (Obj_Def));
- 
-             declare
-                Base_T  : constant Entity_Id := Entity (Subtype_Mark (Obj_Def));
-                New_Def : constant Node_Id   := New_Copy_Tree (Obj_Def);
-                Decl    : constant Node_Id   :=
-                  Make_Subtype_Declaration (Sloc (P),
-                    Defining_Identifier => T,
-                    Subtype_Indication  => New_Def);
- 
-             begin
-                Set_Etype  (T, Base_T);
-                Mutate_Ekind  (T, Subtype_Kind (Ekind (Base_T)));
-                Set_Parent (T, Decl);
-                Set_Scope (T, Current_Scope);
- 
-                if Ekind (T) = E_Array_Subtype then
-                   Constrain_Array (T, New_Def, Related_Nod, T, 'P');
- 
-                elsif Ekind (T) = E_Record_Subtype then
-                   Set_First_Entity (T, First_Entity (Base_T));
-                   Set_Has_Discriminants (T, Has_Discriminants (Base_T));
-                   Set_Is_Constrained (T);
-                end if;
- 
-                Insert_Before (Related_Nod, Decl);
-             end;
- 
-             return T;
-          end if;
- 
           --  When generating code, insert subtype declaration ahead of
!          --  declaration that generated it. Similar behavior required under
!          --  preanalysis (including strict preanalysis) to perform the
!          --  minimum decoration, and avoid reporting spurious errors.
  
           Insert_Action (Obj_Def,
             Make_Subtype_Declaration (Sloc (P),
--- 19146,19173 ----
              return Entity (Subtype_Mark (Obj_Def));
           end if;
  
+          --  During preanalysis, for example within a pre/postcondition,
+          --  provide just enough information to use the subtype.
+ 
+          if Preanalysis_Active then
+             return
+               Process_Subtype
+                 (Obj_Def,
+                  Related_Nod,
+                  Excludes_Null => Null_Exclusion_Present (P));
+          end if;
+ 
+          --  Base name of subtype on object name, which will be unique in
+          --  the current scope.
+ 
           Nam :=
              New_External_Name
               (Chars (Defining_Identifier (Related_Nod)), 'S', 0, 'T');
  
           T := Make_Defining_Identifier (Sloc (P), Nam);
  
           --  When generating code, insert subtype declaration ahead of
!          --  declaration that generated it.
  
           Insert_Action (Obj_Def,
             Make_Subtype_Declaration (Sloc (P),
*************** package body Sem_Ch3 is
*** 21038,21047 ****
        --  Ada 2005 (AI-287, AI-318): Relax the strictness of the front end in
        --  case of limited aggregates (including extension aggregates), and
        --  function calls. The function call may have been given in prefixed
!       --  notation, in which case the original node is an indexed component.
!       --  If the function is parameterless, the original node was an explicit
!       --  dereference. The function may also be parameterless, in which case
!       --  the source node is just an identifier.
  
        --  A branch of a conditional expression may have been removed if the
        --  condition is statically known. This happens during expansion, and
--- 21010,21019 ----
        --  Ada 2005 (AI-287, AI-318): Relax the strictness of the front end in
        --  case of limited aggregates (including extension aggregates), and
        --  function calls. The function call may have been given in prefixed
!       --  notation, in which case the original node is an indexed component,
!       --  or a selected component if the function is parameterless, or even
!       --  an explicit dereference. Finally, for a direct unprefixed call to
!       --  a parameterless function, the original node is just an identifier.
  
        --  A branch of a conditional expression may have been removed if the
        --  condition is statically known. This happens during expansion, and
*************** package body Sem_Ch3 is
*** 21066,21072 ****
              return Present (Entity (Original_Node (Exp)))
                and then Ekind (Entity (Original_Node (Exp))) = E_Function;
  
!          when N_Qualified_Expression =>
              return
                OK_For_Limited_Init_In_05
                  (Typ, Expression (Original_Node (Exp)));
--- 21038,21044 ----
              return Present (Entity (Original_Node (Exp)))
                and then Ekind (Entity (Original_Node (Exp))) = E_Function;
  
!          when N_Expression_With_Actions | N_Qualified_Expression =>
              return
                OK_For_Limited_Init_In_05
                  (Typ, Expression (Original_Node (Exp)));
diff -Nrcpad gcc-16-20260627/gcc/ada/sem_ch4.adb gcc-16-20260704/gcc/ada/sem_ch4.adb
*** gcc-16-20260627/gcc/ada/sem_ch4.adb	Sat Jun 27 22:32:05 2026
--- gcc-16-20260704/gcc/ada/sem_ch4.adb	Sat Jul  4 22:32:06 2026
*************** package body Sem_Ch4 is
*** 2486,2491 ****
--- 2486,2492 ----
  
        A        : Node_Id;
        EWA_Scop : Entity_Id;
+       SE       : Scope_Stack_Entry;
  
     --  Start of processing for Analyze_Expression_With_Actions
  
*************** package body Sem_Ch4 is
*** 2523,2530 ****
--- 2524,2551 ----
           In_Declare_Expr := In_Declare_Expr - 1;
        end if;
  
+       --  If the analysis of the expression has created a transient
+       --  scope, we first need to save the transient scope and pop it.
+ 
+       if Scope_Is_Transient then
+          SE := Scope_Stack.Table (Scope_Stack.Last);
+          Scope_Stack.Decrement_Last;
+       else
+          SE.Is_Transient := False;
+       end if;
+ 
+       --  Remove the scope and its declarations from visibility. Note that
+       --  the scope is purely static and the EWA is not a master construct
+       --  (see AI22-0017) so the lifetime of the objects does not end here.
+ 
        pragma Assert (Current_Scope = Scope_Link (N));
        End_Scope;
+ 
+       --  Push again the transient scope, if any
+ 
+       if SE.Is_Transient then
+          Scope_Stack.Append (SE);
+       end if;
     end Analyze_Expression_With_Actions;
  
     ---------------------------
diff -Nrcpad gcc-16-20260627/gcc/ada/sem_ch5.adb gcc-16-20260704/gcc/ada/sem_ch5.adb
*** gcc-16-20260627/gcc/ada/sem_ch5.adb	Sat Jun 27 22:32:05 2026
--- gcc-16-20260704/gcc/ada/sem_ch5.adb	Sat Jul  4 22:32:06 2026
*************** package body Sem_Ch5 is
*** 94,99 ****
--- 94,110 ----
     --  statements. On success, the return value is the entity of the loop
     --  referenced by the statement.
  
+    function Has_Sec_Stack_Call (N : Node_Id) return Boolean;
+    --  N is the node for an arbitrary construct. This function searches the
+    --  construct N to see if it contains a function call that returns on the
+    --  secondary stack, returning True if any such call is found, and False
+    --  otherwise.
+ 
+    --  ??? The implementation invokes Sem_Util.Requires_Transient_Scope so it
+    --  will return True if N contains a function call that needs finalization,
+    --  in addition to the above specification. See Analyze_Loop_Statement for
+    --  a similar comment about this entanglement.
+ 
     procedure Preanalyze_Range (R_Copy : Node_Id);
     --  Determine expected type of range or domain of iteration of Ada 2012
     --  loop by analyzing separate copy. Do the analysis and resolution of the
diff -Nrcpad gcc-16-20260627/gcc/ada/sem_ch5.ads gcc-16-20260704/gcc/ada/sem_ch5.ads
*** gcc-16-20260627/gcc/ada/sem_ch5.ads	Sat Jun 27 22:32:05 2026
--- gcc-16-20260704/gcc/ada/sem_ch5.ads	Sat Jul  4 22:32:06 2026
*************** package Sem_Ch5 is
*** 51,66 ****
     --  an unconditional transfer of control or an apparent infinite loop. It
     --  checks to see if the statement is followed by some other statement, and
     --  if so generates an appropriate warning for unreachable code.
- 
-    function Has_Sec_Stack_Call (N : Node_Id) return Boolean;
-    --  N is the node for an arbitrary construct. This function searches the
-    --  construct N to see if it contains a function call that returns on the
-    --  secondary stack, returning True if any such call is found, and False
-    --  otherwise.
- 
-    --  ??? The implementation invokes Sem_Util.Requires_Transient_Scope so it
-    --  will return True if N contains a function call that needs finalization,
-    --  in addition to the above specification. See Analyze_Loop_Statement for
-    --  a similar comment about this entanglement.
- 
  end Sem_Ch5;
--- 51,54 ----
diff -Nrcpad gcc-16-20260627/gcc/ada/sem_res.adb gcc-16-20260704/gcc/ada/sem_res.adb
*** gcc-16-20260627/gcc/ada/sem_res.adb	Sat Jun 27 22:32:05 2026
--- gcc-16-20260704/gcc/ada/sem_res.adb	Sat Jul  4 22:32:06 2026
*************** with Sem_Ch4;        use Sem_Ch4;
*** 67,72 ****
--- 67,73 ----
  with Sem_Ch5;        use Sem_Ch5;
  with Sem_Ch6;        use Sem_Ch6;
  with Sem_Ch8;        use Sem_Ch8;
+ with Sem_Ch9;        use Sem_Ch9;
  with Sem_Ch13;       use Sem_Ch13;
  with Sem_Dim;        use Sem_Dim;
  with Sem_Disp;       use Sem_Disp;
*************** package body Sem_Res is
*** 7741,7885 ****
     -- Resolve_Declare_Expression --
     --------------------------------
  
!    procedure Resolve_Declare_Expression
!      (N   : Node_Id;
!       Typ : Entity_Id)
!    is
!       Expr : constant Node_Id := Expression (N);
! 
!       Decl  : Node_Id;
!       Local : Entity_Id := Empty;
! 
!       Save_Hidden_Map : constant Elist_Id := New_Elmt_List;
!       --  Stores the map of identifiers, and corresponding entities, that
!       --  temporarily loose visibility due to homonym declarations in the
!       --  current declare expression.
! 
!       function Replace_Local (N  : Node_Id) return Traverse_Result;
!       --  Use a tree traversal to replace each occurrence of the name of
!       --  a local object declared in the construct, with the corresponding
!       --  entity. This replaces the usual way to perform name capture by
!       --  visibility, because it is not possible to place on the scope
!       --  stack the fake scope created for the analysis of the local
!       --  declarations; such a scope conflicts with the transient scopes
!       --  that may be generated if the expression includes function calls
!       --  requiring finalization.
! 
!       -------------------
!       -- Replace_Local --
!       -------------------
! 
!       function Replace_Local (N  : Node_Id) return Traverse_Result is
!       begin
!          --  The identifier may be the prefix of a selected component,
!          --  but not a selector name, because the local entities do not
!          --  have a scope that can be named: a selected component whose
!          --  selector is a homonym of a local entity must denote some
!          --  global entity.
! 
!          if Nkind (N) = N_Identifier
!            and then Chars (N) = Chars (Local)
!            and then No (Entity (N))
!            and then
!              (Nkind (Parent (N)) /= N_Selected_Component
!                or else N = Prefix (Parent (N)))
!          then
!             Set_Entity (N, Local);
!             Set_Etype (N, Etype (Local));
!             Generate_Reference (Local, N);
!          end if;
! 
!          return OK;
!       end Replace_Local;
! 
!       procedure Replace_Local_Ref is new Traverse_Proc (Replace_Local);
! 
!    --  Start of processing for Resolve_Declare_Expression
  
     begin
-       --  Create a transient scope if the type of this declare-expression
-       --  or its expression requires it; this must be done before we push
-       --  in the scope stack the scope of this declare expression (in order
-       --  to properly remove it from the stack on exit from this routine).
-       --  Given that we don't know yet if secondary stack management will
-       --  be needed, we assume the worst case.
- 
-       if not Preanalysis_Active
-         and then (Requires_Transient_Scope (Typ)
-                     or else Has_Sec_Stack_Call (Expr))
-       then
-          Establish_Transient_Scope (N, Manage_Sec_Stack => True);
-       end if;
- 
        Push_Scope (Scope_Link (N));
  
!       Decl := First (Actions (N));
! 
!       while Present (Decl) loop
!          if Nkind (Decl) in
!             N_Object_Declaration | N_Object_Renaming_Declaration
!               and then Comes_From_Source (Defining_Identifier (Decl))
!          then
!             Local := Defining_Identifier (Decl);
!             Replace_Local_Ref (Expr);
! 
!             --  Traverse the expression to replace references to local
!             --  variables that occur within declarations of the
!             --  declare_expression.
! 
!             declare
!                D : Node_Id := Next (Decl);
!             begin
!                while Present (D) loop
!                   Replace_Local_Ref (D);
!                   Next (D);
!                end loop;
!             end;
! 
!             --  Homonyms of the new local declaration are saved to be restored
!             --  after the resolution of the declare block's expression.
! 
!             Append_Elmt (Local, Save_Hidden_Map);
!             Append_Elmt (Get_Name_Entity_Id (Chars (Local)), Save_Hidden_Map);
  
!             --  Update the references to local in the name table and make them
!             --  immediately visible to be available within the expression.
  
!             Set_Current_Entity (Local);
!             Set_Is_Immediately_Visible (Local);
!             Set_Is_Not_Self_Hidden (Local);
!          end if;
  
!          Next (Decl);
!       end loop;
  
!       --  The end of the declarative list is a freeze point for the
!       --  local declarations.
  
!       if Present (Local) then
!          Decl := Parent (Local);
!          Freeze_All (First_Entity (Scope (Local)), Decl);
        end if;
  
!       Resolve (Expr, Typ);
!       Check_Unset_Reference (Expr);
! 
!       --  Restore any hidden entity homonyms to a local one
! 
!       declare
!          Cursor : Elmt_Id := First_Elmt (Save_Hidden_Map);
!          Name : Name_Id;
!       begin
!          while Present (Cursor) loop
!             Name := Chars (Node (Cursor));
!             Next_Elmt (Cursor);
!             Set_Name_Entity_Id (Name, Node (Cursor));
!             Next_Elmt (Cursor);
!          end loop;
!       end;
  
        pragma Assert (Current_Scope = Scope_Link (N));
        End_Scope;
     end Resolve_Declare_Expression;
  
     -----------------------------------
--- 7742,7788 ----
     -- Resolve_Declare_Expression --
     --------------------------------
  
!    procedure Resolve_Declare_Expression (N : Node_Id; Typ : Entity_Id) is
!       After : Node_Id;
!       SE    : Scope_Stack_Entry;
  
     begin
        Push_Scope (Scope_Link (N));
+       Install_Declarations (Scope_Link (N));
  
!       --  The end of the declarative list is a freezing point for the
!       --  local declarations.
  
!       After := Last (Actions (N));
!       Freeze_All (First_Entity (Scope_Link (N)), After);
  
!       --  Now resolve the expression
  
!       Resolve (Expression (N), Typ);
!       Check_Unset_Reference (Expression (N));
  
!       --  If the resolution of the expression has created a transient
!       --  scope, we first need to save the transient scope and pop it.
  
!       if Scope_Is_Transient then
!          SE := Scope_Stack.Table (Scope_Stack.Last);
!          Scope_Stack.Decrement_Last;
!       else
!          SE.Is_Transient := False;
        end if;
  
!       --  Remove the scope and its declarations from visibility. Note that
!       --  the scope is purely static and the EWA is not a master construct
!       --  (see AI22-0017) so the lifetime of the objects does not end here.
  
        pragma Assert (Current_Scope = Scope_Link (N));
        End_Scope;
+ 
+       --  Push again the transient scope, if any
+ 
+       if SE.Is_Transient then
+          Scope_Stack.Append (SE);
+       end if;
     end Resolve_Declare_Expression;
  
     -----------------------------------
diff -Nrcpad gcc-16-20260627/gcc/common/config/i386/cpuinfo.h gcc-16-20260704/gcc/common/config/i386/cpuinfo.h
*** gcc-16-20260627/gcc/common/config/i386/cpuinfo.h	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/common/config/i386/cpuinfo.h	Sat Jul  4 22:32:07 2026
*************** get_hygon_cpu (struct __processor_model
*** 383,388 ****
--- 383,394 ----
  	  CHECK___builtin_cpu_is ("c86-4g-m7");
  	  cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M7;
  	}
+       else if (model == 0x8)
+ 	{
+ 	  cpu = "c86-4g-m8";
+ 	  CHECK___builtin_cpu_is ("c86-4g-m8");
+ 	  cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M8;
+ 	}
        break;
      default:
        break;
diff -Nrcpad gcc-16-20260627/gcc/common/config/i386/i386-common.cc gcc-16-20260704/gcc/common/config/i386/i386-common.cc
*** gcc-16-20260627/gcc/common/config/i386/i386-common.cc	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/common/config/i386/i386-common.cc	Sat Jul  4 22:32:07 2026
*************** const char *const processor_names[] =
*** 2208,2214 ****
    "znver6",
    "c86-4g-m4",
    "c86-4g-m6",
!   "c86-4g-m7"
  };
  
  /* Guarantee that the array is aligned with enum processor_type.  */
--- 2208,2215 ----
    "znver6",
    "c86-4g-m4",
    "c86-4g-m6",
!   "c86-4g-m7",
!   "c86-4g-m8"
  };
  
  /* Guarantee that the array is aligned with enum processor_type.  */
*************** const pta processor_alias_table[] =
*** 2485,2490 ****
--- 2486,2494 ----
    {"c86-4g-m7", PROCESSOR_C86_4G_M7, CPU_C86_4G_M7,
      PTA_C86_4G_M7,
      M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M7), P_PROC_AVX512F},
+   {"c86-4g-m8", PROCESSOR_C86_4G_M8, CPU_C86_4G_M8,
+     PTA_C86_4G_M8,
+     M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M8), P_PROC_AVX512F},
  
    {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
      PTA_64BIT
diff -Nrcpad gcc-16-20260627/gcc/common/config/i386/i386-cpuinfo.h gcc-16-20260704/gcc/common/config/i386/i386-cpuinfo.h
*** gcc-16-20260627/gcc/common/config/i386/i386-cpuinfo.h	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/common/config/i386/i386-cpuinfo.h	Sat Jul  4 22:32:07 2026
*************** enum processor_subtypes
*** 113,118 ****
--- 113,119 ----
    HYGONFAM18H_C86_4G_M4,
    HYGONFAM18H_C86_4G_M6,
    HYGONFAM18H_C86_4G_M7,
+   HYGONFAM18H_C86_4G_M8,
    CPU_SUBTYPE_MAX
  };
  
diff -Nrcpad gcc-16-20260627/gcc/config/aarch64/aarch64-sve-builtins-base.cc gcc-16-20260704/gcc/config/aarch64/aarch64-sve-builtins-base.cc
*** gcc-16-20260627/gcc/config/aarch64/aarch64-sve-builtins-base.cc	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/aarch64/aarch64-sve-builtins-base.cc	Sat Jul  4 22:32:07 2026
*************** public:
*** 1854,1859 ****
--- 1854,1873 ----
  	gimple_seq_add_stmt_without_update (&stmts, mem_ref_stmt);
  
  	int source_nelts = TYPE_VECTOR_SUBPARTS (access_type).to_constant ();
+ 
+ 	/* When the SVE vector has the same number of elements as the
+ 	   128-bit quadword (i.e. VL == 128), the load fills the entire
+ 	   register and no replication is needed.  Just convert the
+ 	   loaded value from the Advanced SIMD type to the SVE type.  */
+ 	if (known_eq (lhs_len, (unsigned int) source_nelts))
+ 	  {
+ 	    gimple *g
+ 	      = gimple_build_assign (lhs, build1 (VIEW_CONVERT_EXPR,
+ 						  lhs_type, mem_ref_lhs));
+ 	    gimple_seq_add_stmt_without_update (&stmts, g);
+ 	    gsi_replace_with_seq_vops (f.gsi, stmts);
+ 	    return g;
+ 	  }
  	vec_perm_builder sel (lhs_len, source_nelts, 1);
  	for (int i = 0; i < source_nelts; i++)
  	  sel.quick_push (i);
*************** public:
*** 2977,2988 ****
         The fold routines expect the replacement statement to have the
         same lhs as the original call, so return the copy statement
         rather than the field update.  */
!     gassign *copy = gimple_build_assign (unshare_expr (f.lhs), rhs_tuple);
  
      /* Get a reference to the individual vector.  */
      tree field = tuple_type_field (TREE_TYPE (f.lhs));
      tree lhs_array = build3 (COMPONENT_REF, TREE_TYPE (field),
! 			     f.lhs, field, NULL_TREE);
      tree lhs_vector = build4 (ARRAY_REF, TREE_TYPE (rhs_vector),
  			      lhs_array, index, NULL_TREE, NULL_TREE);
      gassign *update = gimple_build_assign (lhs_vector, rhs_vector);
--- 2991,3002 ----
         The fold routines expect the replacement statement to have the
         same lhs as the original call, so return the copy statement
         rather than the field update.  */
!     gassign *copy = gimple_build_assign (f.lhs, rhs_tuple);
  
      /* Get a reference to the individual vector.  */
      tree field = tuple_type_field (TREE_TYPE (f.lhs));
      tree lhs_array = build3 (COMPONENT_REF, TREE_TYPE (field),
! 			     unshare_expr (f.lhs), field, NULL_TREE);
      tree lhs_vector = build4 (ARRAY_REF, TREE_TYPE (rhs_vector),
  			      lhs_array, index, NULL_TREE, NULL_TREE);
      gassign *update = gimple_build_assign (lhs_vector, rhs_vector);
diff -Nrcpad gcc-16-20260627/gcc/config/aarch64/aarch64.cc gcc-16-20260704/gcc/config/aarch64/aarch64.cc
*** gcc-16-20260627/gcc/config/aarch64/aarch64.cc	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/aarch64/aarch64.cc	Sat Jul  4 22:32:07 2026
*************** aarch64_fntype_abi (const_tree fntype)
*** 2571,2577 ****
    if (lookup_attribute ("aarch64_vector_pcs", TYPE_ATTRIBUTES (fntype)))
      return aarch64_simd_abi ();
  
!   if (lookup_attribute ("preserve_none", TYPE_ATTRIBUTES (fntype)))
      return aarch64_preserve_none_abi ();
  
    if (aarch64_returns_value_in_sve_regs_p (fntype)
--- 2571,2579 ----
    if (lookup_attribute ("aarch64_vector_pcs", TYPE_ATTRIBUTES (fntype)))
      return aarch64_simd_abi ();
  
!   /* Fall back to AAPCS for variadic functions.  */
!   if (lookup_attribute ("preserve_none", TYPE_ATTRIBUTES (fntype))
!       && !stdarg_p (fntype))
      return aarch64_preserve_none_abi ();
  
    if (aarch64_returns_value_in_sve_regs_p (fntype)
diff -Nrcpad gcc-16-20260627/gcc/config/i386/c86-4g-m7.md gcc-16-20260704/gcc/config/i386/c86-4g-m7.md
*** gcc-16-20260627/gcc/config/i386/c86-4g-m7.md	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/i386/c86-4g-m7.md	Thu Jan  1 00:00:00 1970
***************
*** 1,2063 ****
- ;; Copyright (C) 2026 Free Software Foundation, Inc.
- ;;
- ;; This file is part of GCC.
- ;;
- ;; GCC is free software; you can redistribute it and/or modify
- ;; it under the terms of the GNU General Public License as published by
- ;; the Free Software Foundation; either version 3, or (at your option)
- ;; any later version.
- ;;
- ;; GCC is distributed in the hope that it will be useful,
- ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
- ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- ;; GNU General Public License for more details.
- ;;
- ;; You should have received a copy of the GNU General Public License
- ;; along with GCC; see the file COPYING3.  If not see
- ;; <http://www.gnu.org/licenses/>.
- ;;
- 
- ;; HYGON c86-4g-m7 Scheduling
- ;; Modeling automatons for decoders, integer execution pipes,
- ;; AGU pipes, branch, floating point execution, fp store units,
- ;; integer and floating point dividers.  Split fpu1 and fpu3
- ;; into their own automata to keep these units independent
- ;; without increasing the main c86_4g_m7_fpu state space.
- (define_automaton "c86_4g_m7, c86_4g_m7_ieu, c86_4g_m7_agu, c86_4g_m7_fpu02, c86_4g_m7_fpu13, c86_4g_m7_idiv, c86_4g_m7_fdiv")
- 
- ;; Decoders unit has 4 decoders and all of them can decode fast path
- ;; and vector type instructions.
- (define_cpu_unit "c86-4g-m7-decode0" "c86_4g_m7")
- (define_cpu_unit "c86-4g-m7-decode1" "c86_4g_m7")
- (define_cpu_unit "c86-4g-m7-decode2" "c86_4g_m7")
- (define_cpu_unit "c86-4g-m7-decode3" "c86_4g_m7")
- 
- ;; Currently blocking all decoders for vector path instructions as
- ;; they are dispatched separetely as microcode sequence.
- (define_reservation "c86-4g-m7-vector" "c86-4g-m7-decode0+c86-4g-m7-decode1+c86-4g-m7-decode2+c86-4g-m7-decode3")
- 
- ;; Direct instructions can be issued to any of the four decoders.
- (define_reservation "c86-4g-m7-direct" "c86-4g-m7-decode0|c86-4g-m7-decode1|c86-4g-m7-decode2|c86-4g-m7-decode3")
- 
- ;; Fix me: Need to revisit this later to simulate fast path double behavior.
- (define_reservation "c86-4g-m7-double" "c86-4g-m7-direct")
- 
- ;; Integer unit 4 ALU pipes.
- (define_cpu_unit "c86-4g-m7-ieu0" "c86_4g_m7_ieu")
- (define_cpu_unit "c86-4g-m7-ieu1" "c86_4g_m7_ieu")
- (define_cpu_unit "c86-4g-m7-ieu2" "c86_4g_m7_ieu")
- (define_cpu_unit "c86-4g-m7-ieu3" "c86_4g_m7_ieu")
- 
- ;; One separated integer divider.
- (define_cpu_unit "c86-4g-m7-idiv" "c86_4g_m7_idiv")
- 
- ;; c86-4g-m7 has an additional branch unit.
- (define_cpu_unit "c86-4g-m7-bru0" "c86_4g_m7_ieu")
- (define_reservation "c86-4g-m7-ieu" "c86-4g-m7-ieu0|c86-4g-m7-ieu1|c86-4g-m7-ieu2|c86-4g-m7-ieu3")
- 
- ;; 3 AGU pipes in c86-4g-m7
- (define_cpu_unit "c86-4g-m7-agu0" "c86_4g_m7_agu")
- (define_cpu_unit "c86-4g-m7-agu1" "c86_4g_m7_agu")
- (define_cpu_unit "c86-4g-m7-agu2" "c86_4g_m7_agu")
- (define_reservation "c86-4g-m7-agu-reserve" "c86-4g-m7-agu0|c86-4g-m7-agu1|c86-4g-m7-agu2")
- 
- ;; Load is 4 cycles.  We do not model reservation of load unit.
- (define_reservation "c86-4g-m7-load" "c86-4g-m7-agu-reserve")
- (define_reservation "c86-4g-m7-store" "c86-4g-m7-agu-reserve")
- 
- ;; vectorpath (microcoded) instructions are single issue instructions.
- ;; So, they occupy all the integer units.
- (define_reservation "c86-4g-m7-ivector" "c86-4g-m7-ieu0+c86-4g-m7-ieu1
- 					 +c86-4g-m7-ieu2+c86-4g-m7-ieu3+c86-4g-m7-bru0
- 					 +c86-4g-m7-agu0+c86-4g-m7-agu1+c86-4g-m7-agu2")
- 
- ;; Floating point unit 4 FP pipes.
- (define_cpu_unit "c86-4g-m7-fpu0" "c86_4g_m7_fpu02")
- (define_cpu_unit "c86-4g-m7-fpu1" "c86_4g_m7_fpu13")
- (define_cpu_unit "c86-4g-m7-fpu2" "c86_4g_m7_fpu02")
- (define_cpu_unit "c86-4g-m7-fpu3" "c86_4g_m7_fpu13")
- 
- (define_reservation "c86-4g-m7-fpu" "c86-4g-m7-fpu0|c86-4g-m7-fpu1|c86-4g-m7-fpu2|c86-4g-m7-fpu3")
- (define_reservation "c86-4g-m7-fpu_0_1" "c86-4g-m7-fpu0|c86-4g-m7-fpu1")
- (define_reservation "c86-4g-m7-fpu_0_2" "c86-4g-m7-fpu0|c86-4g-m7-fpu2")
- (define_reservation "c86-4g-m7-fpu_0_2x2" "c86-4g-m7-fpu0*2|c86-4g-m7-fpu2*2")
- (define_reservation "c86-4g-m7-fpu_0_2x4" "c86-4g-m7-fpu0*4|c86-4g-m7-fpu2*4")
- (define_reservation "c86-4g-m7-fpu_0_3" "c86-4g-m7-fpu0|c86-4g-m7-fpu3")
- (define_reservation "c86-4g-m7-fpu_1_3" "c86-4g-m7-fpu1|c86-4g-m7-fpu3")
- (define_reservation "c86-4g-m7-fpu_1_3x2" "c86-4g-m7-fpu1*2|c86-4g-m7-fpu3*2")
- (define_reservation "c86-4g-m7-fpu_1_3x3" "c86-4g-m7-fpu1*3|c86-4g-m7-fpu3*3")
- (define_reservation "c86-4g-m7-fpu_1_3x6" "c86-4g-m7-fpu1*6|c86-4g-m7-fpu3*6")
- (define_reservation "c86-4g-m7-fpux2" "c86-4g-m7-fpu0*2|c86-4g-m7-fpu1*2|c86-4g-m7-fpu2*2|c86-4g-m7-fpu3*2")
- (define_reservation "c86-4g-m7-fpux4" "c86-4g-m7-fpu0*4|c86-4g-m7-fpu1*4|c86-4g-m7-fpu2*4|c86-4g-m7-fpu3*4")
- (define_reservation "c86-4g-m7-fpux8" "c86-4g-m7-fpu0*8|c86-4g-m7-fpu1*8|c86-4g-m7-fpu2*8|c86-4g-m7-fpu3*8")
- (define_reservation "c86-4g-m7-fpux6" "c86-4g-m7-fpu0*6|c86-4g-m7-fpu1*6|c86-4g-m7-fpu2*6|c86-4g-m7-fpu3*6")
- (define_reservation "c86-4g-m7-fpux16" "c86-4g-m7-fpu0*16|c86-4g-m7-fpu1*16|c86-4g-m7-fpu2*16|c86-4g-m7-fpu3*16")
- (define_reservation "c86-4g-m7-fvector" "c86-4g-m7-fpu0+c86-4g-m7-fpu1
- 					 +c86-4g-m7-fpu2+c86-4g-m7-fpu3
- 					 +c86-4g-m7-agu0+c86-4g-m7-agu1+c86-4g-m7-agu2")
- 
- ;; Two FP dividers.
- (define_cpu_unit "c86-4g-m7-fdiv1" "c86_4g_m7_fdiv")
- (define_cpu_unit "c86-4g-m7-fdiv3" "c86_4g_m7_fdiv")
- 
- (define_reservation "c86-4g-m7-fp1fdiv1x4" "(c86-4g-m7-fpu1+c86-4g-m7-fdiv1)*4")
- (define_reservation "c86-4g-m7-fp3fdiv3x4" "(c86-4g-m7-fpu3+c86-4g-m7-fdiv3)*4")
- (define_reservation "c86-4g-m7-fdiv13" "(c86-4g-m7-fdiv1+c86-4g-m7-fdiv3)")
- (define_reservation "c86-4g-m7-fp13div13" "(c86-4g-m7-fpu1+c86-4g-m7-fpu3+c86-4g-m7-fdiv1+c86-4g-m7-fdiv3)")
- (define_reservation "c86-4g-m7-fp13div13x4" "c86-4g-m7-fp13div13*4")
- (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x8" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*8)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*8)")
- (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x9" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*9)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*9)")
- (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x11" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*11)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*11)")
- (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x15" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*15)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*15)")
- (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x18" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*18)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*18)")
- 
- ;; IMOV/IMOVX
- (define_insn_reservation "c86_4g_m7_imov_xchg" 1
- 			(and (eq_attr "cpu" "c86_4g_m7")
- 			     (and (eq_attr "type" "imov")
- 				  (and (eq_attr "c86_decode" "vector")
- 				       (eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct")
- 
- (define_insn_reservation "c86_4g_m7_imov_xchg_load" 5
- 			(and (eq_attr "cpu" "c86_4g_m7")
- 			     (and (eq_attr "type" "imov")
- 				  (and (eq_attr "c86_decode" "vector")
- 				       (eq_attr "memory" "!none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load")
- 
- (define_insn_reservation "c86_4g_m7_imovx_cwde" 2
- 			(and (eq_attr "cpu" "c86_4g_m7")
- 			     (and (eq_attr "type" "imovx")
- 				  (and (eq_attr "c86_decode" "double")
- 				       (eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
- 
- (define_insn_reservation "c86_4g_m7_imov" 1
- 			(and (eq_attr "cpu" "c86_4g_m7")
- 			     (and (eq_attr "type" "imov,imovx")
- 				  (and (eq_attr "c86_decode" "direct")
- 				       (eq_attr "memory" "none"))))
- 	     "c86-4g-m7-direct,c86-4g-m7-ieu")
- 
- (define_insn_reservation "c86_4g_m7_imov_load" 5
- 			(and (eq_attr "cpu" "c86_4g_m7")
- 			     (and (eq_attr "type" "imov,imovx")
- 				  (and (eq_attr "c86_decode" "!vector")
- 				       (eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu")
- 
- (define_insn_reservation "c86_4g_m7_imov_store" 1
- 			(and (eq_attr "cpu" "c86_4g_m7")
- 			     (and (eq_attr "type" "imov,imovx")
- 				  (and (eq_attr "c86_decode" "!vector")
- 				       (eq_attr "memory" "store"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu")
- 
- ;; PUSH
- (define_insn_reservation "c86_4g_m7_push" 1
- 			(and (eq_attr "cpu" "c86_4g_m7")
- 			     (and (eq_attr "type" "push,sse")
- 				  (eq_attr "memory" "store")))
- 			 "c86-4g-m7-direct,c86-4g-m7-store")
- 
- (define_insn_reservation "c86_4g_m7_push_mem" 5
- 			(and (eq_attr "cpu" "c86_4g_m7")
- 				 (and (eq_attr "type" "push")
- 				  (eq_attr "memory" "both")))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store")
- 
- ;; POP
- (define_insn_reservation "c86_4g_m7_pop" 4
- 			(and (eq_attr "cpu" "c86_4g_m7")
- 			     (and (eq_attr "type" "pop")
- 				  (eq_attr "memory" "load")))
- 			 "c86-4g-m7-direct,c86-4g-m7-load")
- 
- (define_insn_reservation "c86_4g_m7_pop_mem" 5
- 	    (and (eq_attr "cpu" "c86_4g_m7")
- 		 (and (eq_attr "type" "pop")
- 		  (eq_attr "memory" "both")))
- 	     "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store")
- 
- ;; IMUL/IMULX
- (define_insn_reservation "c86_4g_m7_imul" 3
- 			(and (eq_attr "cpu" "c86_4g_m7")
- 			     (and (eq_attr "type" "imul,imulx")
- 				  (eq_attr "memory" "none")))
- 			 "c86-4g-m7-direct,c86-4g-m7-ieu1")
- 
- (define_insn_reservation "c86_4g_m7_imul_load" 7
- 			(and (eq_attr "cpu" "c86_4g_m7")
- 			     (and (eq_attr "type" "imul")
- 				  (eq_attr "memory" "!none")))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu1")
- 
- ;; IDIV
- (define_insn_reservation "c86_4g_m7_idiv" 7
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "idiv")
- 				   (and (eq_attr "mode" "!QI")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*7")
- 
- (define_insn_reservation "c86_4g_m7_idiv_QI" 6
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "idiv")
- 				   (and (eq_attr "mode" "QI")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*6")
- 
- (define_insn_reservation "c86_4g_m7_idiv_load" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "idiv")
- 				   (and (eq_attr "mode" "!QI")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*7")
- 
- (define_insn_reservation "c86_4g_m7_idiv_QI_load" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "idiv")
- 				   (and (eq_attr "mode" "QI")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*6")
- 
- ;; Integer/genaral Instructions
- (define_insn_reservation "c86_4g_m7_insn" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "alu,negnot,rotate1,ishift1,test,incdec,icmp,
- 						    rotate,rotatex,ishift,ishiftx,icmov")
- 				   (eq_attr "memory" "none,unknown")))
- 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
- 
- (define_insn_reservation "c86_4g_m7_insn_load" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "alu,incdec,icmp,test,ishift,
- 						    ishiftx,icmov,rotate,rotatex")
- 				   (eq_attr "memory" "load")))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu")
- 
- (define_insn_reservation "c86_4g_m7_insn_store" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ishift1,rotate1,rotate,incdec,
- 						    alu,icmov,ishift,negnot,alu1")
- 				   (eq_attr "memory" "store")))
- 			 "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store")
- 
- (define_insn_reservation "c86_4g_m7_insn2_store" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "icmp")
- 				   (eq_attr "memory" "store")))
- 			 "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store")
- 
- (define_insn_reservation "c86_4g_m7_insn_both" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "alu,negnot,rotate1,ishift1,incdec,rotate,
- 						    rotatex,ishift,ishiftx,icmov")
- 				   (eq_attr "memory" "both")))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu,c86-4g-m7-store")
- 
- (define_insn_reservation "c86_4g_m7_setcc" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "setcc")
- 				   (eq_attr "memory" "none,unknown")))
- 			 "c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
- 
- (define_insn_reservation "c86_4g_m7_setcc_load" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "setcc")
- 				   (eq_attr "memory" "load")))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
- 
- (define_insn_reservation "c86_4g_m7_setcc_store" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "setcc")
- 				   (eq_attr "memory" "store")))
- 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
- 
- ;; ALU1
- (define_insn_reservation "c86_4g_m7_alu1_double" 2
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "alu1")
- 				   (and (eq_attr "c86_decode" "double")
- 					(eq_attr "memory" "none,unknown"))))
- 			 "c86-4g-m7-double,c86-4g-m7-ieu")
- 
- (define_insn_reservation "c86_4g_m7_alu1_double_load" 6
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "alu1")
- 				   (and (eq_attr "c86_decode" "double")
- 					(eq_attr "memory" "both"))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu")
- 
- (define_insn_reservation "c86_4g_m7_alu1_vector" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "alu1")
- 				   (and (eq_attr "c86_decode" "vector")
- 					(eq_attr "memory" "none,unknown"))))
- 			 "c86-4g-m7-vector,c86-4g-m7-ivector*3")
- 
- (define_insn_reservation "c86_4g_m7_alu1_vector_load" 7
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "alu1")
- 				   (and (eq_attr "c86_decode" "vector")
- 					(eq_attr "memory" "both"))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ivector*3")
- 
- (define_insn_reservation "c86_4g_m7_alu1_direct" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "alu1")
- 				   (and (eq_attr "c86_decode" "direct")
- 					(eq_attr "memory" "none,unknown"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
- 
- (define_insn_reservation "c86_4g_m7_alu1_direct_load" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "alu1")
- 				   (and (eq_attr "c86_decode" "direct")
- 					(eq_attr "memory" "both"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu")
- 
- ;; CALL/CALLV
- (define_insn_reservation "c86_4g_m7_call" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (eq_attr "type" "call,callv"))
- 			 "c86-4g-m7-double,c86-4g-m7-ieu0|c86-4g-m7-bru0,c86-4g-m7-store")
- 
- ;; IBR
- (define_insn_reservation "c86_4g_m7_branch" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ibr")
- 				   (eq_attr "memory" "none")))
- 			  "c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-bru0")
- 
- (define_insn_reservation "c86_4g_m7_branch_load" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ibr")
- 				   (eq_attr "memory" "load")))
- 			  "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-bru0")
- 
- ;; LEA
- (define_insn_reservation "c86_4g_m7_lea" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (eq_attr "type" "lea"))
- 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
- 
- ;; LEAVE
- (define_insn_reservation "c86_4g_m7_leave" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (eq_attr "type" "leave"))
- 			 "c86-4g-m7-double,c86-4g-m7-ieu,c86-4g-m7-store")
- 
- ;; STR
- (define_insn_reservation "c86_4g_m7_str" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "str")
- 				   (eq_attr "memory" "none")))
- 			 "c86-4g-m7-vector,c86-4g-m7-ivector*3")
- 
- (define_insn_reservation "c86_4g_m7_str_load" 7
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "str")
- 				   (eq_attr "memory" "load")))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*3")
- 
- 
- (define_insn_reservation "c86_4g_m7_ieu_vector" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "other,multi")
- 				   (and (eq_attr "unit" "!i387")
- 				       (eq_attr "memory" "none,unknown"))))
- 			 "c86-4g-m7-vector,c86-4g-m7-ivector*5")
- 
- (define_insn_reservation "c86_4g_m7_ieu_vector_load" 9
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "other,multi")
- 				   (and (eq_attr "unit" "!i387")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*5")
- 
- ;; SSEINS
- (define_insn_reservation "c86_4g_m7_sse_insertimm" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseins")
- 				   (and (eq_attr "memory" "none")
- 					(eq_attr "length_immediate" "2"))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_3,c86-4g-m7-fpu1")
- 
- (define_insn_reservation "c86_4g_m7_sse_insert" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseins")
- 				   (and (eq_attr "memory" "none")
- 					(eq_attr "length_immediate" "!2"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu1*2")
- 
- ;; FCMOV
- (define_insn_reservation "c86_4g_m7_fp_cmov" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (eq_attr "type" "fcmov"))
- 			 "c86-4g-m7-vector,c86-4g-m7-fvector*3")
- 
- ;; FLD
- (define_insn_reservation "c86_4g_m7_fp_mov_direct_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "c86_decode" "direct")
- 				   (and (eq_attr "type" "fmov")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
- 
- ;; FST
- (define_insn_reservation "c86_4g_m7_fp_mov_direct_store" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "c86_decode" "direct")
- 				   (and (eq_attr "type" "fmov")
- 					(eq_attr "memory" "store"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu1,c86-4g-m7-store")
- 
- ;; FILD
- (define_insn_reservation "c86_4g_m7_fp_mov_double_load" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "c86_decode" "double")
- 				   (and (eq_attr "type" "fmov")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
- 
- ;; FIST
- (define_insn_reservation "c86_4g_m7_fp_mov_double_store" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "c86_decode" "double")
- 				   (and (eq_attr "type" "fmov")
- 					(eq_attr "memory" "store"))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-store")
- 
- (define_insn_reservation "c86_4g_m7_fp_mov_direct" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "c86_decode" "direct")
- 				   (and (eq_attr "type" "fmov")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
- 
- ;; FSQRT
- (define_insn_reservation "c86_4g_m7_fp_sqrt" 22
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "fpspc")
- 				   (eq_attr "c86_attr" "sqrt")))
- 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x18")
- 
- ;; FPSPC
- (define_insn_reservation "c86_4g_m7_fp_spc_direct" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "fpspc")
- 				   (and (eq_attr "c86_decode" "direct")
- 				    (and (eq_attr "c86_attr" "other")
- 					 (eq_attr "memory" "store")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu3")
- 
- (define_insn_reservation "c86_4g_m7_fp_spc" 6
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "fpspc")
- 				   (and (eq_attr "c86_attr" "other")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-vector,c86-4g-m7-fvector*6")
- 
- (define_insn_reservation "c86_4g_m7_fp_op_mul" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "fop,fmul")
- 				   (eq_attr "memory" "none")))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_fp_op_mul_load" 12
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "fop,fmul")
- 				   (and (eq_attr "fp_int_src" "false")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_fp_op_imul_load" 16
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "fmul")
- 				   (and (eq_attr "fp_int_src" "true")
- 					(eq_attr "memory" "!none"))))
- 			"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu_0_2")
- 
- ;; FDIV
- (define_insn_reservation "c86_4g_m7_fp_div" 15
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "fdiv")
- 				   (eq_attr "memory" "none")))
- 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x11")
- 
- (define_insn_reservation "c86_4g_m7_fp_div_load" 22
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "fdiv")
- 				   (and (eq_attr "fp_int_src" "false")
- 					(eq_attr "memory" "!none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x11")
- 
- (define_insn_reservation "c86_4g_m7_fp_idiv_load" 26
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "fdiv")
- 				   (and (eq_attr "fp_int_src" "true")
- 					(eq_attr "memory" "!none"))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1*4,c86-4g-m7-fp1div1_fp3div3_x4x11")
- 
- (define_insn_reservation "c86_4g_m7_fp_fsgn" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (eq_attr "type" "fsgn"))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
- 
- ;; FCMP
- (define_insn_reservation "c86_4g_m7_fp_fcmp" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "fcmp")
- 				   (eq_attr "memory" "none")))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu0,c86-4g-m7-fpu1")
- 
- (define_insn_reservation "c86_4g_m7_fp_fcmp_load" 12
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "fcmp")
- 				   (eq_attr "memory" "load")))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu1")
- 
- ;; MMX
- (define_insn_reservation "c86_4g_m7_fp_mmx" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (eq_attr "type" "mmx"))
- 			 "c86-4g-m7-direct")
- 
- (define_insn_reservation "c86_4g_m7_mmx_add_cmp" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxadd,mmxcmp")
- 				   (eq_attr "memory" "none")))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_mmx_add_cmp_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxadd,mmxcmp")
- 				   (eq_attr "memory" "load")))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_mmx_cvt" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxcvt")
- 				   (and (eq_attr "c86_attr" "other")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
- 
- (define_insn_reservation "c86_4g_m7_mmx_cvt_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxcvt")
- 				   (and (eq_attr "c86_attr" "other")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
- 
- (define_insn_reservation "c86_4g_m7_mmx_shift" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxshft")
- 				   (and (eq_attr "c86_attr" "other")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
- 
- (define_insn_reservation "c86_4g_m7_mmx_shift_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxshft")
- 				   (and (eq_attr "c86_attr" "other")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
- 
- (define_insn_reservation "c86_4g_m7_mmx_shift_avg" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxshft")
- 				   (and (eq_attr "c86_attr" "avg")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_mmx_shift_avg_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxshft")
- 				   (and (eq_attr "c86_attr" "avg")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
- 
- ;; SADBW
- (define_insn_reservation "c86_4g_m7_mmx_shift_sadbw" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxshft")
- 				   (and (eq_attr "c86_attr" "sadbw")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu0")
- 
- (define_insn_reservation "c86_4g_m7_mmx_shift_sadbw_load" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxshft")
- 				   (and (eq_attr "c86_attr" "sadbw")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
- 
- (define_insn_reservation "c86_4g_m7_mmx_mov" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxmov")
- 				   (eq_attr "memory" "none")))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
- 
- (define_insn_reservation "c86_4g_m7_mmx_mov_store" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxmov")
- 				   (and (eq_attr "c86_attr" "other")
- 					(eq_attr "memory" "store"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
- 
- (define_insn_reservation "c86_4g_m7_mmx_mov_load" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxmov")
- 				   (eq_attr "memory" "load")))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
- 
- (define_insn_reservation "c86_4g_m7_mmx_mul" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxmul")
- 				   (eq_attr "memory" "none")))
- 			  "c86-4g-m7-direct,c86-4g-m7-fpu0")
- 
- (define_insn_reservation "c86_4g_m7_mmx_mul_load" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mmxmul")
- 				   (eq_attr "memory" "load")))
- 			  "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
- 
- ;; PINSR
- (define_insn_reservation "c86_4g_m7_sse_pinsr_reg" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog,mmxcvt")
- 				   (and (eq_attr "c86_attr" "insr")
- 				    (and (eq_attr "prefix" "orig")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-double,c86-4g-m7-ieu2,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_sse_pinsr_reg_load" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog,mmxcvt")
- 				   (and (eq_attr "c86_attr" "insr")
- 				    (and (eq_attr "prefix" "orig")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_avx_vpinsr_reg" 2
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "insr")
- 				     (and (eq_attr "prefix" "!orig")
- 					  (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3x2")
- 
- (define_insn_reservation "c86_4g_m7_avx_vpinsr_reg_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "insr")
- 				     (and (eq_attr "prefix" "!orig")
- 					  (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
- 
- ;; PERM
- (define_insn_reservation "c86_4g_m7_avx512_perm_xmm" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (ior (and (eq_attr "c86_attr" "perm2")
- 						  (eq_attr "mode" "V4SF,V2DF,TI"))
- 					     (and (eq_attr "c86_attr" "perm")
- 						  (eq_attr "mode" "V8SF,V4DF,TI,OI")))
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_perm_xmm_opload" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (ior (and (eq_attr "c86_attr" "perm2")
- 						  (eq_attr "mode" "V4SF,V2DF,TI"))
- 					     (and (eq_attr "c86_attr" "perm")
- 						  (eq_attr "mode" "V8SF,V4DF,TI,OI")))
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_permi2_ymm" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "perm2")
- 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
- 					  (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpux4")
- 
- (define_insn_reservation "c86_4g_m7_avx512_permi2_zmm" 16
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "perm2")
- 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpux16")
- 
- (define_insn_reservation "c86_4g_m7_avx512_permi2_ymm_load" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "perm2")
- 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux4")
- 
- (define_insn_reservation "c86_4g_m7_avx512_permi2_zmm_load" 23
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "perm2")
- 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux16")
- 
- (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "perm")
- 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
- 				     (and (match_operand 2 "immediate_operand")
- 					  (eq_attr "memory" "none"))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpux4")
- 
- (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm_load" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "perm")
- 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
- 				     (and (match_operand 2 "immediate_operand")
- 					  (eq_attr "memory" "load"))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpux4")
- 
- (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_noimm" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "perm")
- 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
- 				     (and (match_operand 2 "nonimmediate_operand")
- 					  (eq_attr "memory" "none"))))))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpux8")
- 
- (define_insn_reservation "c86_4g_m7_sse_perm_zmm_noimm_load" 15
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "perm")
- 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
- 				     (and (match_operand 2 "nonimmediate_operand")
- 					 (eq_attr "memory" "load"))))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux8")
- 
- ;; VINSERT
- (define_insn_reservation "c86_4g_m7_avx512_insertx_ymm" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog,sselog1")
- 				   (and (eq_attr "c86_attr" "insertx")
- 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
- 				     (and (eq_attr "prefix" "evex")
- 					  (eq_attr "memory" "none"))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_insertx_ymem" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog,sselog1")
- 				   (and (eq_attr "c86_attr" "insertx")
- 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
- 				     (and (eq_attr "prefix" "evex")
- 					  (eq_attr "memory" "load,both"))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmm" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "insertx")
- 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
- 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==16")
- 					 (match_operand 2 "register_operand"))))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2x4,c86-4g-m7-fpu_0_2x4")
- 
- (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmem" 12
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "insertx")
- 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
- 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==16")
- 					  (match_operand 2 "memory_operand"))))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4,c86-4g-m7-fpu_0_2x4")
- 
- (define_insn_reservation "c86_4g_m7_avx512_insertx_zymm" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "insertx")
- 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
- 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==32")
- 					  (match_operand 2 "register_operand"))))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_insertx_zymem" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "insertx")
- 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
- 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==32")
- 					  (match_operand 2 "memory_operand"))))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx_insertx_ymm" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog,sselog1")
- 				   (and (eq_attr "c86_attr" "insertx")
- 				     (and (eq_attr "prefix" "!evex")
- 					  (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu0*2")
- 
- (define_insn_reservation "c86_4g_m7_avx_insertx_ymem" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog,sselog1")
- 				   (and (eq_attr "c86_attr" "insertx")
- 				     (and (eq_attr "prefix" "!evex")
- 					  (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0*2")
- 
- ;; SHUF/MULTISHIFTQB
- (define_insn_reservation "c86_4g_m7_avx512_shuf_xymm" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "shufx")
- 				     (and (not (eq_attr "mode" "V8DF,V16SF,XI"))
- 					  (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_shuf_zmm" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "shufx")
- 				     (and (eq_attr "mode" "V8DF,V16SF,XI")
- 					  (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2x4")
- 
- (define_insn_reservation "c86_4g_m7_avx512_shuf_xymem" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "shufx")
- 				     (and (not (eq_attr "mode" "V8DF,V16SF,XI"))
- 					  (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_shuf_zmem" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "shufx")
- 				     (and (eq_attr "mode" "V8DF,V16SF,XI")
- 					  (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4")
- 
- ;; SSELOGIC
- (define_insn_reservation "c86_4g_m7_sselogic_xymm" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog,sselog1")
- 				   (and (eq_attr "c86_attr" "sselogic")
- 					 (eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_sselogic_xymm_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog,sselog1")
- 				   (and (eq_attr "c86_attr" "sselogic")
- 					 (eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
- 
- ;; CMPESTR
- (define_insn_reservation "c86_4g_m7_avx512_cmpestr" 6
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "cmpestr")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpux6")
- 
- (define_insn_reservation "c86_4g_m7_avx512_cmpestr_load" 13
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog")
- 				   (and (eq_attr "c86_attr" "cmpestr")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux6")
- 
- ;; SSELOG
- (define_insn_reservation "c86_4g_m7_avx512_log" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
- 				   (and (eq_attr "c86_attr" "other")
- 					  (eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_log_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
- 				   (and (eq_attr "c86_attr" "other")
- 					 (eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
- 
- ;; SSELOG1
- ;; VDBPSADBW
- (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymm" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1")
- 				   (and (eq_attr "c86_attr" "sadbw")
- 				    (and (eq_attr "mode" "OI,TI")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymem" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1")
- 				   (and (eq_attr "c86_attr" "sadbw")
- 				    (and (eq_attr "mode" "OI,TI")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmm" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1")
- 				   (and (eq_attr "c86_attr" "sadbw")
- 				    (and (eq_attr "mode" "XI")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmem" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1")
- 				   (and (eq_attr "c86_attr" "sadbw")
- 				    (and (eq_attr "mode" "XI")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")
- 
- ;; ABS
- (define_insn_reservation "c86_4g_m7_avx512_abs" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1,sse")
- 				   (and (eq_attr "c86_attr" "abs")
- 				    (and (eq_attr "prefix" "evex")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_avx512_abs_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1,sse")
- 				   (and (eq_attr "c86_attr" "abs")
- 				    (and (eq_attr "prefix" "evex")
- 					 (eq_attr "memory" "load,both")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
- 
- ;; SIGN
- (define_insn_reservation "c86_4g_m7_avx_sign" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1")
- 				   (and (eq_attr "c86_attr" "sign")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
- 
- (define_insn_reservation "c86_4g_m7_avx_sign_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1")
- 				   (and (eq_attr "c86_attr" "sign")
- 					(eq_attr "memory" "!none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
- 
- ;; BLEND/ABS/AES
- (define_insn_reservation "c86_4g_m7_avx_blend" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1")
- 				   (and (eq_attr "c86_attr" "abs,blend,aes")
- 				    (and (eq_attr "prefix" "!evex")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
- 
- (define_insn_reservation "c86_4g_m7_avx_blend_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1")
- 				   (and (eq_attr "c86_attr" "abs,blend,aes")
- 				    (and (eq_attr "prefix" "!evex")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
- 
- (define_insn_reservation "c86_4g_m7_avx512_aes" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1,ssecvt,sse")
- 				   (and (eq_attr "c86_attr" "aes")
- 				    (and (eq_attr "prefix" "evex")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_aes_load" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1,ssecvt,sse")
- 				   (and (eq_attr "c86_attr" "aes")
- 				    (and (eq_attr "prefix" "evex")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx_aes" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1")
- 				   (and (eq_attr "c86_attr" "aes")
- 				    (and (eq_attr "prefix" "!evex")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu1")
- 
- (define_insn_reservation "c86_4g_m7_avx_aes_load" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1")
- 				   (and (eq_attr "c86_attr" "aes")
- 				    (and (eq_attr "prefix" "!evex")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu1")
- 
- ;; EXTR
- (define_insn_reservation "c86_4g_m7_extr" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1,sselog,mmxcvt")
- 				   (and (eq_attr "c86_attr" "extr")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
- 
- (define_insn_reservation "c86_4g_m7_extr_load" 12
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sselog1,sselog,mmxcvt")
- 				   (and (eq_attr "c86_attr" "extr")
- 					(eq_attr "memory" "!none"))))
- 			 "c86-4g-m7-double,c86-4g-m7-store,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
- 
- ;; SSECOMI
- (define_insn_reservation "c86_4g_m7_avx_ssecomi_comi" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecomi")
- 				   (and (eq_attr "prefix_extra" "0")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_avx_ssecomi_comi_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecomi")
- 				   (and (eq_attr "prefix_extra" "0")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_avx_ssecomi_test" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecomi")
- 				   (and (eq_attr "prefix_extra" "1")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
- 
- (define_insn_reservation "c86_4g_m7_avx_ssecomi_test_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecomi")
- 				   (and (eq_attr "prefix_extra" "1")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
- 
- ;; SSEIMUL
- (define_insn_reservation "c86_4g_m7_avx512_imul" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseimul")
- 				   (and (eq_attr "prefix" "evex")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_imul_mem" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseimul")
- 				   (and (eq_attr "prefix" "evex")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_avx_imul" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseimul")
- 				   (and (eq_attr "prefix" "!evex")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
- 
- (define_insn_reservation "c86_4g_m7_avx_imul_mem" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseimul")
- 				   (and (eq_attr "prefix" "!evex")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
- 
- ;; SSEMOV
- (define_insn_reservation "c86_4g_m7_avx512_mov_vmov" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov,sseiadd")
- 				    (and (eq_attr "c86_attr" "other,blend,maxmin")
- 					 (eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_avx512_mov_vmov_store" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "other")
- 					 (eq_attr "memory" "store"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
- 
- (define_insn_reservation "c86_4g_m7_avx512_mov_vmov_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov,sseiadd")
- 				   (and (eq_attr "c86_attr" "other,blend,maxmin")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "vpmovx")
- 				    (and (eq_attr "prefix" "evex")
- 				     (and (eq_attr "mode" "OI,V8SF,V4DF")
- 					  (eq_attr "memory" "none"))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y_load" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov,sselog1")
- 				   (and (eq_attr "c86_attr" "vpmovx")
- 				    (and (eq_attr "prefix" "evex")
- 				     (and (eq_attr "mode" "OI,V8SF,V4DF")
- 					  (eq_attr "memory" "load,both"))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "vpmovx")
- 				     (and (eq_attr "mode" "XI")
- 					  (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x4")
- 
- (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z_load" 12
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "vpmovx")
- 				     (and (eq_attr "mode" "XI")
- 					  (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4")
- 
- (define_insn_reservation "c86_4g_m7_avx512_vpmovx_x" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "vpmovx")
- 				    (and (eq_attr "prefix" "evex")
- 				     (and (eq_attr "mode" "TI,SI")
- 					  (eq_attr "memory" "none"))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_vpmovx_x_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "vpmovx")
- 				    (and (eq_attr "prefix" "evex")
- 				     (and (eq_attr "mode" "TI,SI")
- 					  (eq_attr "memory" "load"))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "vpmovx")
- 				    (and (eq_attr "prefix" "!evex")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
- 
- (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "vpmovx")
- 				    (and (eq_attr "prefix" "!evex")
- 					 (eq_attr "memory" "load,both")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
- 
- ;; EXPAND
- (define_insn_reservation "c86_4g_m7_avx512_expand" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "expand,compress")
- 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_expand_load" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "expand,compress")
- 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_expand_z" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "expand,compress")
- 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_expand_z_load" 17
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "expand,compress")
- 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
- 
- ;; MOVNT
- (define_insn_reservation "c86_4g_m7_avx512_movnt_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "movnt")
- 				   (and (eq_attr "mode" "XI,V16SF,V8DF")
- 					(eq_attr "memory" "load")))))
- 			 "c86-4g-m7-double,c86-4g-m7-load")
- 
- (define_insn_reservation "c86_4g_m7_avx512_movnt_store" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "movnt")
- 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
- 					 (eq_attr "memory" "store")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1*2")
- 
- (define_insn_reservation "c86_4g_m7_sse_movnt_store" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov,mmxmov")
- 				   (and (eq_attr "c86_attr" "movnt")
- 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
- 					 (eq_attr "memory" "!none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
- 
- (define_insn_reservation "c86_4g_m7_sse_movnt" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "movnt")
- 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
- 
- ;; BLENDV
- (define_insn_reservation "c86_4g_m7_avx512_blendv" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "blendv")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
- 
- (define_insn_reservation "c86_4g_m7_avx512_blendv_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov")
- 				   (and (eq_attr "c86_attr" "blendv")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
- 
- ;; SSEMOV2
- (define_insn_reservation "c86_4g_m7_sse_mov2" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov2")
- 				   (eq_attr "memory" "none")))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_sse_mov2_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemov2")
- 				   (eq_attr "memory" "!none")))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
- 
- ;; SSEISHFT
- (define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseishft")
- 				   (and (eq_attr "prefix_extra" "1")
- 				    (and (eq_attr "prefix" "evex")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseishft")
- 				   (and (eq_attr "prefix_extra" "1")
- 				    (and (eq_attr "prefix" "evex")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseishft")
- 				   (and (eq_attr "prefix_extra" "!1")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseishft")
- 				   (and (eq_attr "prefix_extra" "!1")
- 					(eq_attr "memory" "!none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
- 
- 
- ;; SSEADD
- (define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_xy" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseadd,sse")
- 				   (and (eq_attr "c86_attr" "maxmin")
- 				    (and (eq_attr "prefix" "evex")
- 				      (and (eq_attr "memory" "none")
- 					   (eq_attr "memory" "none"))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_xy_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseadd,sse")
- 				   (and (eq_attr "c86_attr" "maxmin")
- 				    (and (eq_attr "prefix" "evex")
- 				      (ior (eq_attr "memory" "load")
- 					   (eq_attr "memory" "load"))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseadd,sse")
- 				   (and (eq_attr "c86_attr" "maxmin")
- 				    (and (eq_attr "prefix" "vex")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
- 
- (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseadd,sse")
- 				   (and (eq_attr "c86_attr" "maxmin")
- 				    (and (eq_attr "prefix" "vex")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
- 
- (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseadd,sse")
- 				   (and (eq_attr "c86_attr" "maxmin")
- 				    (and (eq_attr "prefix" "orig")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
- 
- (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseadd,sse")
- 				   (and (eq_attr "c86_attr" "maxmin")
- 				    (and (eq_attr "prefix" "orig")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
- 
- ;; SUB/ADD
- (define_insn_reservation "c86_4g_m7_avx512_sseadd_xy" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseadd")
- 				   (and (eq_attr "c86_attr" "other")
- 					  (eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sseadd_xy_load" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseadd")
- 				   (and (eq_attr "c86_attr" "other")
- 					 (eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
- 
- ;; HADD/HSUB
- (define_insn_reservation "c86_4g_m7_avx_sseadd_hplus" 7
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseadd,sseadd1")
- 				   (and (eq_attr "c86_attr" "hplus")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-vector")
- 
- (define_insn_reservation "c86_4g_m7_avx_sseadd_hplus_load" 14
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseadd,sseadd1")
- 				   (and (eq_attr "c86_attr" "hplus")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load")
- 
- ;; SSEIADD
- (define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseiadd")
- 				   (and (eq_attr "c86_attr" "sadbw,madd")
- 					(and (ior (eq_attr "prefix" "evex")
- 						  (eq_attr "mode" "XI"))
- 					     (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd_mem" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseiadd")
- 				   (and (eq_attr "c86_attr" "sadbw,madd")
- 					(and (ior (eq_attr "prefix" "evex")
- 						  (eq_attr "mode" "XI"))
- 					     (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseiadd")
- 				   (and (eq_attr "c86_attr" "sadbw")
- 				    (and (eq_attr "prefix" "vex,maybe_evex")
- 				     (and (eq_attr "mode" "TI,OI")
- 					  (eq_attr "memory" "none"))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
- 
- (define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw_mem" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseiadd")
- 				   (and (eq_attr "c86_attr" "sadbw")
- 				    (and (eq_attr "prefix" "vex,maybe_evex")
- 				     (and (eq_attr "mode" "TI,OI")
- 					  (eq_attr "memory" "load"))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
- 
- (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseiadd")
- 				   (and (eq_attr "c86_attr" "sadbw")
- 				    (and (eq_attr "prefix" "orig")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
- 
- (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw_mem" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseiadd")
- 				   (and (eq_attr "c86_attr" "sadbw")
- 				    (and (eq_attr "prefix" "orig")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
- 
- (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseiadd")
- 				   (and (eq_attr "c86_attr" "madd")
- 				    (and (eq_attr "prefix" "!evex")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu0")
- 
- (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd_mem" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseiadd")
- 				   (and (eq_attr "c86_attr" "madd")
- 				    (and (eq_attr "prefix" "!evex")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
- 
- ;; AVG
- (define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseiadd")
- 				   (and (eq_attr "c86_attr" "avg")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseiadd")
- 				   (and (eq_attr "c86_attr" "avg")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseiadd,sseiadd1")
- 				   (and (eq_attr "c86_attr" "hplus")
- 				    (and (eq_attr "prefix" "vex")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-vector")
- 
- (define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus_load" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseiadd,sseiadd1")
- 				   (and (eq_attr "c86_attr" "hplus")
- 				    (and (eq_attr "prefix" "vex")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load")
- 
- (define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseiadd,sseiadd1")
- 				   (and (eq_attr "c86_attr" "hplus")
- 				    (and (eq_attr "prefix" "orig")
- 				     (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpux2")
- 
- (define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus_load" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sseiadd,sseiadd1")
- 				   (and (eq_attr "c86_attr" "hplus")
- 				    (and (eq_attr "prefix" "orig")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux2")
- 
- ;; SSEMUL
- (define_insn_reservation "c86_4g_m7_avx512_ssemul" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemul")
- 				   (eq_attr "memory" "none")))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssemul_load" 10
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemul")
- 				   (eq_attr "memory" "load")))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
- 
- ;; SSEDIV
- (define_insn_reservation "c86_4g_m7_avx512_ssediv_x" 13
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssediv")
- 				   (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x8")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssediv_xmem" 20
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssediv")
- 				   (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x8")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssediv_y" 13
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssediv")
- 				   (and (eq_attr "mode" "V8SF,V4DF")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*8")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssediv_ymem" 20
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssediv")
- 				   (and (eq_attr "mode" "V8SF,V4DF")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*8")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssediv_z" 24
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssediv")
- 				   (and (eq_attr "mode" "V16SF,V8DF")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-double,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*20")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssediv_zmem" 31
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssediv")
- 				   (and (eq_attr "mode" "V16SF,V8DF")
- 					 (eq_attr "memory" "load"))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*20")
- 
- ;; SSECMP
- (define_insn_reservation "c86_4g_m7_avx512_ssecmp" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecmp")
- 				   (and (eq_attr "prefix" "evex")
- 				    (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssecmp_load" 12
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecmp")
- 				   (and (eq_attr "prefix" "evex")
- 				    (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssecmp_z" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecmp")
- 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
- 				     (and (eq_attr "c86_attr" "other")
- 					  (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssecmp_z_load" 12
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecmp")
- 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
- 				     (and (eq_attr "c86_attr" "other")
- 					  (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecmp")
- 				   (and (eq_attr "prefix" "evex")
- 				    (and (eq_attr "mode" "TI,OI")
- 				     (and (eq_attr "c86_attr" "other")
- 					  (eq_attr "memory" "none"))))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_load" 12
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecmp")
- 				   (and (eq_attr "prefix" "evex")
- 				    (and (eq_attr "mode" "TI,OI")
- 				     (and (eq_attr "c86_attr" "other")
- 					  (eq_attr "memory" "load"))))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecmp")
- 				   (and (eq_attr "prefix" "evex")
- 				    (and (eq_attr "mode" "XI")
- 				     (and (eq_attr "c86_attr" "other,ptest")
- 					  (eq_attr "memory" "none"))))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z_load" 12
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecmp")
- 				   (and (eq_attr "prefix" "evex")
- 				    (and (eq_attr "mode" "XI")
- 				     (and (eq_attr "c86_attr" "other,ptest")
- 					  (eq_attr "memory" "load"))))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3x2")
- 
- (define_insn_reservation "c86_4g_m7_avx_ssecmp_vp" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecmp")
- 				   (and (eq_attr "prefix" "!evex")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
- 
- (define_insn_reservation "c86_4g_m7_avx_ssecmp_vp_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecmp")
- 				   (and (eq_attr "prefix" "!evex")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
- 
- ;; VPTEST
- (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test" 6
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecmp")
- 				    (and (eq_attr "mode" "TI,OI")
- 				     (and (eq_attr "c86_attr" "ptest")
- 					  (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test_load" 13
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecmp")
- 				    (and (eq_attr "mode" "TI,OI")
- 				     (and (eq_attr "c86_attr" "ptest")
- 					  (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fpu_1_3")
- 
- ;; SSECVT
- (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecvt")
- 				   (and (eq_attr "c86_attr" "other")
- 				    (and (eq_attr "prefix" "evex")
- 				     (and (eq_attr "mode" "TI,V4SF,V2DF,OI,V8SF,V4DF")
- 				      (and (not (ior (match_operand:V8DI 1 "register_operand")
- 						     (match_operand:V8DF 1 "register_operand")))
- 					   (eq_attr "memory" "none")))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy_load" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecvt")
- 				   (and (eq_attr "prefix" "evex")
- 				    (and (eq_attr "c86_attr" "other")
- 				     (and (eq_attr "mode" "TI,V4SF,V2DF,OI,V8SF,V4DF")
- 				      (and (not (ior (match_operand:V8DI 1 "register_operand")
- 						     (match_operand:V8DF 1 "register_operand")))
- 					   (eq_attr "memory" "!none")))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecvt")
- 				   (and (eq_attr "mode" "OI,V8SF,V4DF")
- 				    (and (eq_attr "c86_attr" "other")
- 				     (and (ior (match_operand:V8DI 1 "register_operand")
- 					       (match_operand:V8DF 1 "register_operand"))
- 					  (eq_attr "memory" "none"))))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z_load" 15
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecvt")
- 				   (and (eq_attr "mode" "OI,V8SF,V4DF")
- 				    (and (eq_attr "c86_attr" "other")
- 				     (and (ior (match_operand:V8DI 1 "memory_operand")
- 					       (match_operand:V8DF 1 "memory_operand"))
- 					  (eq_attr "memory" "!none"))))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssecvt_z" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecvt")
- 				   (and (eq_attr "c86_attr" "other")
- 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_ssecvt_z_load" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecvt")
- 				   (and (eq_attr "c86_attr" "other")
- 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
- 					 (eq_attr "memory" "!none")))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx_ssecvt" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecvt")
- 				   (and (eq_attr "prefix" "!evex")
- 				     (and (eq_attr "mmx_isa" "base")
- 					  (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
- 
- (define_insn_reservation "c86_4g_m7_avx_ssecvt_load" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecvt")
- 				   (and (eq_attr "prefix" "!evex")
- 				    (and (eq_attr "mmx_isa" "base")
- 					 (eq_attr "memory" "!none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
- 
- ;; CVTPI
- (define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecvt")
- 				   (and (eq_attr "mode" "SF,DI")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
- 
- (define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi_load" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecvt")
- 				   (and (eq_attr "mode" "SF,DI")
- 					 (eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
- 
- (define_insn_reservation "c86_4g_m7_sse_ssecvt_pi" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecvt")
- 				    (and (not (eq_attr "mode" "SF,DI"))
- 				     (and (eq_attr "mmx_isa" "native")
- 					  (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
- 
- (define_insn_reservation "c86_4g_m7_sse_ssecvt_pi_load" 12
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssecvt")
- 				   (and (not (eq_attr "mode" "SF,DI"))
- 				    (and (eq_attr "mmx_isa" "native")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
- 
- ;; SSEMULADD
- (define_insn_reservation "c86_4g_m7_avx512_muladd" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemuladd")
- 				   (and (eq_attr "c86_attr" "other")
- 					(eq_attr "memory" "none"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_muladd_load" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemuladd")
- 				   (and (eq_attr "c86_attr" "other")
- 					(eq_attr "memory" "load"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_muladd_madd" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemuladd,sse")
- 				   (and (eq_attr "c86_attr" "madd,rcp")
- 				    (and (eq_attr "prefix" "evex")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_muladd_madd_load" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "ssemuladd,sse")
- 				   (and (eq_attr "c86_attr" "madd,rcp")
- 				    (and (eq_attr "prefix" "evex")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
- 
- ;; SSE
- (define_insn_reservation "c86_4g_m7_avx512_sse_range" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				    (and (eq_attr "c86_attr" "other")
- 				     (and (eq_attr "length_immediate" "!1")
- 				      (and (eq_attr "prefix" "evex")
- 				       (and (eq_attr "c86_decode" "direct")
- 					   (eq_attr "memory" "none")))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_range_load" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				    (and (eq_attr "c86_attr" "other")
- 				     (and (eq_attr "length_immediate" "!1")
- 				      (and (eq_attr "c86_decode" "direct")
- 				       (and (eq_attr "prefix" "evex")
- 					    (eq_attr "memory" "load")))))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x" 2
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "c86_decode" "vector")
- 				    (and (eq_attr "mode" "TI")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x_load" 9
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "c86_decode" "vector")
- 				    (and (eq_attr "mode" "TI")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x2")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "c86_decode" "vector")
- 				    (and (eq_attr "mode" "OI")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y_load" 12
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "c86_decode" "vector")
- 				    (and (eq_attr "mode" "OI")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "c86_decode" "vector")
- 				    (and (eq_attr "mode" "XI")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x6")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z_load" 15
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "c86_decode" "vector")
- 				    (and (eq_attr "mode" "XI")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x6")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_class" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "c86_attr" "other")
- 				    (and (eq_attr "length_immediate" "1")
- 				     (and (not (eq_attr "mode" "V32HF,V16SF,V8DF"))
- 					  (eq_attr "memory" "none"))))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_class_load" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				    (and (eq_attr "c86_attr" "other")
- 				     (and (eq_attr "length_immediate" "1")
- 				      (and (not (eq_attr "mode" "V32HF,V16SF,V8DF"))
- 					   (eq_attr "memory" "load"))))))
- 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_class_z" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				    (and (eq_attr "c86_attr" "other")
- 				     (and (eq_attr "length_immediate" "1")
- 				      (and (eq_attr "mode" "V32HF,V16SF,V8DF")
- 					   (eq_attr "memory" "none"))))))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_class_z_load" 11
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				    (and (eq_attr "c86_attr" "other")
- 				     (and (eq_attr "length_immediate" "1")
- 				      (and (eq_attr "mode" "V32HF,V16SF,V8DF")
- 					   (eq_attr "memory" "load"))))))
- 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx_sse" 5
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "c86_attr" "rcp,other")
- 				    (and (eq_attr "prefix" "!evex")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
- 
- (define_insn_reservation "c86_4g_m7_avx_sse_load" 12
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "c86_attr" "rcp,other")
- 				    (and (eq_attr "prefix" "!evex")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
- 
- ;; SSE SQRT
- (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_x" 14
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "mode" "SF,V4SF")
- 				    (and (eq_attr "c86_attr" "sqrt")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x9")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_xload" 21
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "mode" "SF,V4SF")
- 				    (and (eq_attr "c86_attr" "sqrt")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x9")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_y" 14
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "mode" "V8SF")
- 				    (and (eq_attr "c86_attr" "sqrt")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*9")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_yload" 21
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "mode" "V8SF")
- 				    (and (eq_attr "c86_attr" "sqrt")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*9")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_z" 26
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "mode" "V16SF")
- 				    (and (eq_attr "c86_attr" "sqrt")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*22")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_zload" 33
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "mode" "V16SF")
- 				    (and (eq_attr "c86_attr" "sqrt")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*22")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_x" 20
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "mode" "DF,V2DF")
- 				    (and (eq_attr "c86_attr" "sqrt")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x15")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_xload" 27
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "mode" "DF,V2DF")
- 				    (and (eq_attr "c86_attr" "sqrt")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x15")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_y" 20
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "mode" "V4DF")
- 				    (and (eq_attr "c86_attr" "sqrt")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*15")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_yload" 27
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "mode" "V4DF")
- 				    (and (eq_attr "c86_attr" "sqrt")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*15")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_z" 38
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "mode" "V8DF")
- 				    (and (eq_attr "c86_attr" "sqrt")
- 					 (eq_attr "memory" "none")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*34")
- 
- (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_zload" 45
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "sse")
- 				   (and (eq_attr "mode" "V8DF")
- 				    (and (eq_attr "c86_attr" "sqrt")
- 					 (eq_attr "memory" "load")))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*34")
- 
- ;; MSKLOG/MSKMOV
- (define_insn_reservation "c86_4g_m7_avx512_msklog" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "msklog")
- 				   (eq_attr "c86_decode" "direct")))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_msklog_vector" 4
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "msklog")
- 				   (eq_attr "c86_decode" "vector")))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_mskmov_reg_k" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mskmov")
- 				  (and (match_operand 0 "register_operand" "r")
- 				       (eq_attr "memory" "none"))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_mskmov_xy_k" 2
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mskmov")
- 				   (ior (match_operand:V2DI 0 "register_operand" "v")
- 					(match_operand:V4DI 0 "register_operand" "v"))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_mskmov_z_k" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mskmov")
- 				   (match_operand:V8DI 0 "register_operand" "v")))
- 			 "c86-4g-m7-vector,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_k" 1
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mskmov")
- 				  (and (match_operand 0 "register_operand" "k")
- 				       (match_operand 1 "register_operand" "k"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_reg" 3
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mskmov")
- 				  (and (match_operand 0 "register_operand" "k")
- 				       (match_operand 1 "register_operand" "r"))))
- 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_1_3")
- 
- (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_m" 8
- 			 (and (eq_attr "cpu" "c86_4g_m7")
- 			      (and (eq_attr "type" "mskmov")
- 				  (and (match_operand 0 "register_operand" "k")
- 				       (match_operand 1 "memory_operand"))))
- 			 "c86-4g-m7-direct,c86-4g-m7-load")
--- 0 ----
diff -Nrcpad gcc-16-20260627/gcc/config/i386/c86-4g-m7m8.md gcc-16-20260704/gcc/config/i386/c86-4g-m7m8.md
*** gcc-16-20260627/gcc/config/i386/c86-4g-m7m8.md	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/config/i386/c86-4g-m7m8.md	Sat Jul  4 22:32:07 2026
***************
*** 0 ****
--- 1,2097 ----
+ ;; Copyright (C) 2026 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+ ;;
+ ;; GCC is free software; you can redistribute it and/or modify
+ ;; it under the terms of the GNU General Public License as published by
+ ;; the Free Software Foundation; either version 3, or (at your option)
+ ;; any later version.
+ ;;
+ ;; GCC is distributed in the hope that it will be useful,
+ ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+ ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ ;; GNU General Public License for more details.
+ ;;
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING3.  If not see
+ ;; <http://www.gnu.org/licenses/>.
+ ;;
+ 
+ ;; HYGON c86-4g-m7/m8 Scheduling
+ ;; Modeling automatons for decoders, integer execution pipes,
+ ;; AGU pipes, branch, floating point execution, fp store units,
+ ;; integer and floating point dividers.  Split fpu1 and fpu3
+ ;; into their own automata to keep these units independent
+ ;; without increasing the main c86_4g_m7_fpu state space.
+ (define_automaton "c86_4g_m7, c86_4g_m7_ieu, c86_4g_m7_agu, c86_4g_m7_fpu02, c86_4g_m7_fpu13, c86_4g_m7_idiv, c86_4g_m7_fdiv")
+ 
+ ;; Decoders unit has 4 decoders and all of them can decode fast path
+ ;; and vector type instructions.
+ (define_cpu_unit "c86-4g-m7-decode0" "c86_4g_m7")
+ (define_cpu_unit "c86-4g-m7-decode1" "c86_4g_m7")
+ (define_cpu_unit "c86-4g-m7-decode2" "c86_4g_m7")
+ (define_cpu_unit "c86-4g-m7-decode3" "c86_4g_m7")
+ 
+ ;; Currently blocking all decoders for vector path instructions as
+ ;; they are dispatched separetely as microcode sequence.
+ (define_reservation "c86-4g-m7-vector" "c86-4g-m7-decode0+c86-4g-m7-decode1+c86-4g-m7-decode2+c86-4g-m7-decode3")
+ 
+ ;; Direct instructions can be issued to any of the four decoders.
+ (define_reservation "c86-4g-m7-direct" "c86-4g-m7-decode0|c86-4g-m7-decode1|c86-4g-m7-decode2|c86-4g-m7-decode3")
+ 
+ ;; Fix me: Need to revisit this later to simulate fast path double behavior.
+ (define_reservation "c86-4g-m7-double" "c86-4g-m7-direct")
+ 
+ ;; Integer unit 4 ALU pipes.
+ (define_cpu_unit "c86-4g-m7-ieu0" "c86_4g_m7_ieu")
+ (define_cpu_unit "c86-4g-m7-ieu1" "c86_4g_m7_ieu")
+ (define_cpu_unit "c86-4g-m7-ieu2" "c86_4g_m7_ieu")
+ (define_cpu_unit "c86-4g-m7-ieu3" "c86_4g_m7_ieu")
+ 
+ ;; One separated integer divider.
+ (define_cpu_unit "c86-4g-m7-idiv" "c86_4g_m7_idiv")
+ 
+ ;; c86-4g-m7 has an additional branch unit.
+ (define_cpu_unit "c86-4g-m7-bru0" "c86_4g_m7_ieu")
+ (define_reservation "c86-4g-m7-ieu" "c86-4g-m7-ieu0|c86-4g-m7-ieu1|c86-4g-m7-ieu2|c86-4g-m7-ieu3")
+ 
+ ;; 3 AGU pipes in c86-4g-m7
+ (define_cpu_unit "c86-4g-m7-agu0" "c86_4g_m7_agu")
+ (define_cpu_unit "c86-4g-m7-agu1" "c86_4g_m7_agu")
+ (define_cpu_unit "c86-4g-m7-agu2" "c86_4g_m7_agu")
+ (define_reservation "c86-4g-m7-agu-reserve" "c86-4g-m7-agu0|c86-4g-m7-agu1|c86-4g-m7-agu2")
+ 
+ ;; Load is 4 cycles.  We do not model reservation of load unit.
+ (define_reservation "c86-4g-m7-load" "c86-4g-m7-agu-reserve")
+ (define_reservation "c86-4g-m7-store" "c86-4g-m7-agu-reserve")
+ 
+ ;; vectorpath (microcoded) instructions are single issue instructions.
+ ;; So, they occupy all the integer units.
+ (define_reservation "c86-4g-m7-ivector" "c86-4g-m7-ieu0+c86-4g-m7-ieu1
+ 					 +c86-4g-m7-ieu2+c86-4g-m7-ieu3+c86-4g-m7-bru0
+ 					 +c86-4g-m7-agu0+c86-4g-m7-agu1+c86-4g-m7-agu2")
+ 
+ ;; Floating point unit 4 FP pipes.
+ (define_cpu_unit "c86-4g-m7-fpu0" "c86_4g_m7_fpu02")
+ (define_cpu_unit "c86-4g-m7-fpu1" "c86_4g_m7_fpu13")
+ (define_cpu_unit "c86-4g-m7-fpu2" "c86_4g_m7_fpu02")
+ (define_cpu_unit "c86-4g-m7-fpu3" "c86_4g_m7_fpu13")
+ 
+ (define_reservation "c86-4g-m7-fpu" "c86-4g-m7-fpu0|c86-4g-m7-fpu1|c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ (define_reservation "c86-4g-m7-fpu_0_1" "c86-4g-m7-fpu0|c86-4g-m7-fpu1")
+ (define_reservation "c86-4g-m7-fpu_0_2" "c86-4g-m7-fpu0|c86-4g-m7-fpu2")
+ (define_reservation "c86-4g-m7-fpu_0_2x2" "c86-4g-m7-fpu0*2|c86-4g-m7-fpu2*2")
+ (define_reservation "c86-4g-m7-fpu_0_2x4" "c86-4g-m7-fpu0*4|c86-4g-m7-fpu2*4")
+ (define_reservation "c86-4g-m7-fpu_0_3" "c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ (define_reservation "c86-4g-m7-fpu_1_3" "c86-4g-m7-fpu1|c86-4g-m7-fpu3")
+ (define_reservation "c86-4g-m7-fpu_1_3x2" "c86-4g-m7-fpu1*2|c86-4g-m7-fpu3*2")
+ (define_reservation "c86-4g-m7-fpu_1_3x3" "c86-4g-m7-fpu1*3|c86-4g-m7-fpu3*3")
+ (define_reservation "c86-4g-m7-fpu_1_3x6" "c86-4g-m7-fpu1*6|c86-4g-m7-fpu3*6")
+ (define_reservation "c86-4g-m7-fpux2" "c86-4g-m7-fpu0*2|c86-4g-m7-fpu1*2|c86-4g-m7-fpu2*2|c86-4g-m7-fpu3*2")
+ (define_reservation "c86-4g-m7-fpux4" "c86-4g-m7-fpu0*4|c86-4g-m7-fpu1*4|c86-4g-m7-fpu2*4|c86-4g-m7-fpu3*4")
+ (define_reservation "c86-4g-m7-fpux8" "c86-4g-m7-fpu0*8|c86-4g-m7-fpu1*8|c86-4g-m7-fpu2*8|c86-4g-m7-fpu3*8")
+ (define_reservation "c86-4g-m7-fpux6" "c86-4g-m7-fpu0*6|c86-4g-m7-fpu1*6|c86-4g-m7-fpu2*6|c86-4g-m7-fpu3*6")
+ (define_reservation "c86-4g-m7-fpux16" "c86-4g-m7-fpu0*16|c86-4g-m7-fpu1*16|c86-4g-m7-fpu2*16|c86-4g-m7-fpu3*16")
+ (define_reservation "c86-4g-m7-fvector" "c86-4g-m7-fpu0+c86-4g-m7-fpu1
+ 					 +c86-4g-m7-fpu2+c86-4g-m7-fpu3
+ 					 +c86-4g-m7-agu0+c86-4g-m7-agu1+c86-4g-m7-agu2")
+ 
+ ;; Two FP dividers.
+ (define_cpu_unit "c86-4g-m7-fdiv1" "c86_4g_m7_fdiv")
+ (define_cpu_unit "c86-4g-m7-fdiv3" "c86_4g_m7_fdiv")
+ 
+ (define_reservation "c86-4g-m7-fp1fdiv1x4" "(c86-4g-m7-fpu1+c86-4g-m7-fdiv1)*4")
+ (define_reservation "c86-4g-m7-fp3fdiv3x4" "(c86-4g-m7-fpu3+c86-4g-m7-fdiv3)*4")
+ (define_reservation "c86-4g-m7-fdiv13" "(c86-4g-m7-fdiv1+c86-4g-m7-fdiv3)")
+ (define_reservation "c86-4g-m7-fp13div13" "(c86-4g-m7-fpu1+c86-4g-m7-fpu3+c86-4g-m7-fdiv1+c86-4g-m7-fdiv3)")
+ (define_reservation "c86-4g-m7-fp13div13x4" "c86-4g-m7-fp13div13*4")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x8" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*8)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*8)")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x9" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*9)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*9)")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x11" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*11)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*11)")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x15" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*15)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*15)")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x18" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*18)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*18)")
+ 
+ ;; IMOV/IMOVX
+ 
+ ;; Some reservations keep the historical "m7" naming, while their CPU
+ ;; attributes include both m7 and m8.
+ (define_insn_reservation "c86_4g_m7_imov_xchg" 1
+ 			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			     (and (eq_attr "type" "imov")
+ 				  (and (eq_attr "c86_decode" "vector")
+ 				       (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-vector")
+ 
+ (define_insn_reservation "c86_4g_m7_imov_xchg_load" 5
+ 			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			     (and (eq_attr "type" "imov")
+ 				  (and (eq_attr "c86_decode" "vector")
+ 				       (eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load")
+ 
+ (define_insn_reservation "c86_4g_m7_imovx_cwde" 2
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imovx")
+ 				  (and (eq_attr "c86_decode" "double")
+ 				       (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m8_imovx_cwde" 1
+ 			(and (eq_attr "cpu" "c86_4g_m8")
+ 			     (and (eq_attr "type" "imovx")
+ 				  (and (eq_attr "c86_decode" "double")
+ 				       (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_imov" 1
+ 			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			     (and (eq_attr "type" "imov,imovx")
+ 				  (and (eq_attr "c86_decode" "direct")
+ 				       (eq_attr "memory" "none"))))
+ 	     "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_imov_load" 5
+ 			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			     (and (eq_attr "type" "imov,imovx")
+ 				  (and (eq_attr "c86_decode" "!vector")
+ 				       (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_imov_store" 1
+ 			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			     (and (eq_attr "type" "imov,imovx")
+ 				  (and (eq_attr "c86_decode" "!vector")
+ 				       (eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu")
+ 
+ ;; PUSH
+ (define_insn_reservation "c86_4g_m7_push" 1
+ 			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			     (and (eq_attr "type" "push,sse")
+ 				  (eq_attr "memory" "store")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_push_mem" 5
+ 			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 				 (and (eq_attr "type" "push")
+ 				  (eq_attr "memory" "both")))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store")
+ 
+ ;; POP
+ (define_insn_reservation "c86_4g_m7_pop" 4
+ 			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			     (and (eq_attr "type" "pop")
+ 				  (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load")
+ 
+ (define_insn_reservation "c86_4g_m7_pop_mem" 5
+ 	    (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 		 (and (eq_attr "type" "pop")
+ 		  (eq_attr "memory" "both")))
+ 	     "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store")
+ 
+ ;; IMUL/IMULX
+ (define_insn_reservation "c86_4g_m7_imul" 3
+ 			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			     (and (eq_attr "type" "imul,imulx")
+ 				  (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu1")
+ 
+ (define_insn_reservation "c86_4g_m7_imul_load" 7
+ 			(and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			     (and (eq_attr "type" "imul")
+ 				  (eq_attr "memory" "!none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu1")
+ 
+ ;; IDIV
+ (define_insn_reservation "c86_4g_m7_idiv" 7
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "!QI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*7")
+ 
+ (define_insn_reservation "c86_4g_m7_idiv_QI" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "QI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*6")
+ 
+ (define_insn_reservation "c86_4g_m7_idiv_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "!QI")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*7")
+ 
+ (define_insn_reservation "c86_4g_m7_idiv_QI_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "QI")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*6")
+ 
+ ;; Integer/genaral Instructions
+ (define_insn_reservation "c86_4g_m7_insn" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "alu,negnot,rotate1,ishift1,test,incdec,icmp,
+ 						    rotate,rotatex,ishift,ishiftx,icmov")
+ 				   (eq_attr "memory" "none,unknown")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_insn_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "alu,incdec,icmp,test,ishift,
+ 						    ishiftx,icmov,rotate,rotatex")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_insn_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ishift1,rotate1,rotate,incdec,
+ 						    alu,icmov,ishift,negnot,alu1")
+ 				   (eq_attr "memory" "store")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_insn2_store" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "icmp")
+ 				   (eq_attr "memory" "store")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_insn_both" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "alu,negnot,rotate1,ishift1,incdec,rotate,
+ 						    rotatex,ishift,ishiftx,icmov")
+ 				   (eq_attr "memory" "both")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_setcc" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "setcc")
+ 				   (eq_attr "memory" "none,unknown")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
+ 
+ (define_insn_reservation "c86_4g_m7_setcc_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "setcc")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
+ 
+ (define_insn_reservation "c86_4g_m7_setcc_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "setcc")
+ 				   (eq_attr "memory" "store")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
+ 
+ ;; ALU1
+ (define_insn_reservation "c86_4g_m7_alu1_double" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "double")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_double_load" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "double")
+ 					(eq_attr "memory" "both"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_vector" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-ivector*3")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_vector_load" 7
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 					(eq_attr "memory" "both"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ivector*3")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_direct" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "direct")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_direct_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "direct")
+ 					(eq_attr "memory" "both"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu")
+ 
+ ;; CALL/CALLV
+ (define_insn_reservation "c86_4g_m7_call" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (eq_attr "type" "call,callv"))
+ 			 "c86-4g-m7-double,c86-4g-m7-store,c86-4g-m7-bru0")
+ 
+ ;; IBR
+ (define_insn_reservation "c86_4g_m7_branch" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ibr")
+ 				   (eq_attr "memory" "none")))
+ 			  "c86-4g-m7-direct,c86-4g-m7-bru0")
+ 
+ (define_insn_reservation "c86_4g_m7_branch_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ibr")
+ 				   (eq_attr "memory" "load")))
+ 			  "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-bru0")
+ 
+ ;; LEA
+ (define_insn_reservation "c86_4g_m7_lea" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (eq_attr "type" "lea"))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ ;; LEAVE
+ (define_insn_reservation "c86_4g_m7_leave" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (eq_attr "type" "leave"))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu,c86-4g-m7-store")
+ 
+ ;; STR
+ (define_insn_reservation "c86_4g_m7_str" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "str")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-vector,c86-4g-m7-ivector*3")
+ 
+ (define_insn_reservation "c86_4g_m7_str_load" 7
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "str")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*3")
+ 
+ 
+ (define_insn_reservation "c86_4g_m7_ieu_vector" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "other,multi")
+ 				   (and (eq_attr "unit" "!i387")
+ 				       (eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-ivector*5")
+ 
+ (define_insn_reservation "c86_4g_m7_ieu_vector_load" 9
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "other,multi")
+ 				   (and (eq_attr "unit" "!i387")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*5")
+ 
+ ;; SSEINS
+ (define_insn_reservation "c86_4g_m7_sse_insertimm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseins")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "length_immediate" "2"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_3,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_insert" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseins")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "length_immediate" "!2"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1*2")
+ 
+ ;; FCMOV
+ (define_insn_reservation "c86_4g_m7_fp_cmov" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (eq_attr "type" "fcmov"))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fvector*3")
+ 
+ ;; FLD
+ (define_insn_reservation "c86_4g_m7_fp_mov_direct_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ ;; FST
+ (define_insn_reservation "c86_4g_m7_fp_mov_direct_store" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1,c86-4g-m7-store")
+ 
+ ;; FILD
+ (define_insn_reservation "c86_4g_m7_fp_mov_double_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ ;; FIST
+ (define_insn_reservation "c86_4g_m7_fp_mov_double_store" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_mov_direct" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
+ 
+ ;; FSQRT
+ (define_insn_reservation "c86_4g_m7_fp_sqrt" 22
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "fpspc")
+ 				   (eq_attr "c86_attr" "sqrt")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x18")
+ 
+ ;; FPSPC
+ (define_insn_reservation "c86_4g_m7_fp_spc_direct" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "fpspc")
+ 				   (and (eq_attr "c86_decode" "direct")
+ 				    (and (eq_attr "c86_attr" "other")
+ 					 (eq_attr "memory" "store")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_spc" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "fpspc")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fvector*6")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_op_mul" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "fop,fmul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_op_mul_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "fop,fmul")
+ 				   (and (eq_attr "fp_int_src" "false")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_op_imul_load" 16
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "fmul")
+ 				   (and (eq_attr "fp_int_src" "true")
+ 					(eq_attr "memory" "!none"))))
+ 			"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu_0_2")
+ 
+ ;; FDIV
+ (define_insn_reservation "c86_4g_m7_fp_div" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x11")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_div_load" 22
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (and (eq_attr "fp_int_src" "false")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x11")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_idiv_load" 26
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (and (eq_attr "fp_int_src" "true")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1*4,c86-4g-m7-fp1div1_fp3div3_x4x11")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_fsgn" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (eq_attr "type" "fsgn"))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ ;; FCMP
+ (define_insn_reservation "c86_4g_m7_fp_fcmp" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "fcmp")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu0,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_fcmp_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "fcmp")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu1")
+ 
+ ;; MMX
+ (define_insn_reservation "c86_4g_m7_fp_mmx" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (eq_attr "type" "mmx"))
+ 			 "c86-4g-m7-direct")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_add_cmp" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxadd,mmxcmp")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_add_cmp_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxadd,mmxcmp")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_cvt" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxcvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_cvt_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxcvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift_avg" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "avg")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift_avg_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "avg")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ ;; SADBW
+ (define_insn_reservation "c86_4g_m7_mmx_shift_sadbw" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift_sadbw_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mov" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxmov")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mov_store" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxmov")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mov_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxmov")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxmul")
+ 				   (eq_attr "memory" "none")))
+ 			  "c86-4g-m7-direct,c86-4g-m7-fpu0")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mul_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mmxmul")
+ 				   (eq_attr "memory" "load")))
+ 			  "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
+ 
+ ;; PINSR
+ (define_insn_reservation "c86_4g_m7_sse_pinsr_reg" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog,mmxcvt")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_pinsr_reg_load" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog,mmxcvt")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_vpinsr_reg" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 				     (and (eq_attr "prefix" "!orig")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_vpinsr_reg_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 				     (and (eq_attr "prefix" "!orig")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ ;; PERM
+ (define_insn_reservation "c86_4g_m7_avx512_perm_xmm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (ior (and (eq_attr "c86_attr" "perm2")
+ 						  (eq_attr "mode" "V4SF,V2DF,TI"))
+ 					     (and (eq_attr "c86_attr" "perm")
+ 						  (eq_attr "mode" "V8SF,V4DF,TI,OI")))
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_perm_xmm_opload" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (ior (and (eq_attr "c86_attr" "perm2")
+ 						  (eq_attr "mode" "V4SF,V2DF,TI"))
+ 					     (and (eq_attr "c86_attr" "perm")
+ 						  (eq_attr "mode" "V8SF,V4DF,TI,OI")))
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_permi2_ymm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm2")
+ 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_permi2_zmm" 16
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm2")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux16")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_permi2_ymm_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm2")
+ 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_permi2_zmm_load" 23
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm2")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux16")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (match_operand 2 "immediate_operand")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpux4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (match_operand 2 "immediate_operand")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpux4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_noimm" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (match_operand 2 "nonimmediate_operand")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux8")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_perm_zmm_noimm_load" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (match_operand 2 "nonimmediate_operand")
+ 					 (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux8")
+ 
+ ;; VINSERT
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_ymm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 				     (and (eq_attr "prefix" "evex")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_ymem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 				     (and (eq_attr "prefix" "evex")
+ 					  (eq_attr "memory" "load,both"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmm" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==16")
+ 					 (match_operand 2 "register_operand"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmem" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==16")
+ 					  (match_operand 2 "memory_operand"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_zymm" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==32")
+ 					  (match_operand 2 "register_operand"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_zymem" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==32")
+ 					  (match_operand 2 "memory_operand"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_insertx_ymm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				     (and (eq_attr "prefix" "!evex")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0*2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_insertx_ymem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				     (and (eq_attr "prefix" "!evex")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0*2")
+ 
+ ;; SHUF/MULTISHIFTQB
+ (define_insn_reservation "c86_4g_m7_avx512_shuf_xymm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "shufx")
+ 				     (and (not (eq_attr "mode" "V8DF,V16SF,XI"))
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_shuf_zmm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "shufx")
+ 				     (and (eq_attr "mode" "V8DF,V16SF,XI")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2x4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_shuf_xymem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "shufx")
+ 				     (and (not (eq_attr "mode" "V8DF,V16SF,XI"))
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_shuf_zmem" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "shufx")
+ 				     (and (eq_attr "mode" "V8DF,V16SF,XI")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4")
+ 
+ ;; SSELOGIC
+ (define_insn_reservation "c86_4g_m7_sselogic_xymm" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "sselogic")
+ 					 (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_sselogic_xymm_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "sselogic")
+ 					 (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ ;; CMPESTR
+ (define_insn_reservation "c86_4g_m7_avx512_cmpestr" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "cmpestr")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux6")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_cmpestr_load" 13
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "cmpestr")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux6")
+ 
+ ;; SSELOG
+ (define_insn_reservation "c86_4g_m7_avx512_log" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_log_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					 (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ ;; SSELOG1
+ ;; VDBPSADBW
+ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "mode" "OI,TI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymem" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "mode" "OI,TI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "mode" "XI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmem" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "mode" "XI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")
+ 
+ ;; ABS
+ (define_insn_reservation "c86_4g_m7_avx512_abs" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1,sse")
+ 				   (and (eq_attr "c86_attr" "abs")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_abs_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1,sse")
+ 				   (and (eq_attr "c86_attr" "abs")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "load,both")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu")
+ 
+ ;; SIGN
+ (define_insn_reservation "c86_4g_m7_avx_sign" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sign")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sign_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sign")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_3")
+ 
+ ;; BLEND/ABS/AES
+ (define_insn_reservation "c86_4g_m7_avx_blend" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "abs,blend,aes")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_blend_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "abs,blend,aes")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_aes" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1,ssecvt,sse")
+ 				   (and (eq_attr "c86_attr" "aes")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_aes_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1,ssecvt,sse")
+ 				   (and (eq_attr "c86_attr" "aes")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_aes" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "aes")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_aes_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "aes")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ ;; EXTR
+ (define_insn_reservation "c86_4g_m7_extr" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1,sselog,mmxcvt")
+ 				   (and (eq_attr "c86_attr" "extr")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_extr_store" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sselog1,sselog,mmxcvt")
+ 				   (and (eq_attr "c86_attr" "extr")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-store,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+ 
+ ;; SSECOMI
+ (define_insn_reservation "c86_4g_m7_avx_ssecomi_comi" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecomi")
+ 				   (and (eq_attr "prefix_extra" "0")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecomi_comi_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecomi")
+ 				   (and (eq_attr "prefix_extra" "0")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecomi_test" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecomi")
+ 				   (and (eq_attr "prefix_extra" "1")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecomi_test_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecomi")
+ 				   (and (eq_attr "prefix_extra" "1")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+ 
+ ;; SSEIMUL
+ (define_insn_reservation "c86_4g_m7_avx512_imul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (and (eq_attr "prefix" "evex")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_imul_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (and (eq_attr "prefix" "evex")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_imul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (and (eq_attr "prefix" "!evex")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_imul_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (and (eq_attr "prefix" "!evex")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_3")
+ 
+ ;; SSEMOV
+ (define_insn_reservation "c86_4g_m7_avx512_mov_vmov" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov,sseiadd")
+ 				    (and (eq_attr "c86_attr" "other,blend,maxmin")
+ 					 (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mov_vmov_store" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mov_vmov_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov,sseiadd")
+ 				   (and (eq_attr "c86_attr" "other,blend,maxmin")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "OI,V8SF,V4DF")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov,sselog1")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "OI,V8SF,V4DF")
+ 					  (eq_attr "memory" "load,both"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				     (and (eq_attr "mode" "XI")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				     (and (eq_attr "mode" "XI")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_x" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "TI,SI")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_x_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "TI,SI")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load,both")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+ 
+ ;; EXPAND
+ (define_insn_reservation "c86_4g_m7_avx512_expand" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "expand,compress")
+ 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_expand_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "expand,compress")
+ 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_expand_z" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "expand,compress")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_expand_z_load" 17
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "expand,compress")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
+ 
+ ;; MOVNT
+ (define_insn_reservation "c86_4g_m7_avx512_movnt_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "movnt")
+ 				   (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					(eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_movnt_store" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "movnt")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "store")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1*2")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_movnt_store" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov,mmxmov")
+ 				   (and (eq_attr "c86_attr" "movnt")
+ 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ 					 (eq_attr "memory" "!none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_movnt" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "movnt")
+ 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ ;; BLENDV
+ (define_insn_reservation "c86_4g_m7_avx512_blendv" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "blendv")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_blendv_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "blendv")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ ;; SSEMOV2
+ (define_insn_reservation "c86_4g_m7_sse_mov2" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov2")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_mov2_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemov2")
+ 				   (eq_attr "memory" "!none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ ;; SSEISHFT
+ (define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (and (eq_attr "prefix_extra" "1")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (and (eq_attr "prefix_extra" "1")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (and (eq_attr "prefix_extra" "!1")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (and (eq_attr "prefix_extra" "!1")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ 
+ ;; SSEADD
+ (define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "evex")
+ 				         (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "vex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "vex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ 
+ ;; SUB/ADD
+ (define_insn_reservation "c86_4g_m7_avx512_sseadd" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseadd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseadd_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseadd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ ;; HADD/HSUB
+ (define_insn_reservation "c86_4g_m7_avx_sseadd_hplus" 7
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseadd,sseadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-vector")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseadd_hplus_load" 14
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseadd,sseadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load")
+ 
+ ;; SSEIADD
+ (define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw,madd")
+ 					(and (ior (eq_attr "prefix" "evex")
+ 						  (eq_attr "mode" "XI"))
+ 					     (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw,madd")
+ 					(and (ior (eq_attr "prefix" "evex")
+ 						  (eq_attr "mode" "XI"))
+ 					     (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "prefix" "vex,maybe_evex")
+ 				     (and (eq_attr "mode" "TI,OI")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "prefix" "vex,maybe_evex")
+ 				     (and (eq_attr "mode" "TI,OI")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_3")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_3")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "madd")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "madd")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
+ 
+ ;; AVG
+ (define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "avg")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "avg")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseiadd,sseiadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 				    (and (eq_attr "prefix" "vex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseiadd,sseiadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 				    (and (eq_attr "prefix" "vex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseiadd,sseiadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux2")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sseiadd,sseiadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux2")
+ 
+ ;; SSEMUL
+ (define_insn_reservation "c86_4g_m7_avx512_ssemul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssemul_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m8_avx512_ssemul" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m8_avx512_ssemul_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ ;; SSEDIV
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_x" 13
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x8")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_xmem" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x8")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_y" 13
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "V8SF,V4DF")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*8")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_ymem" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "V8SF,V4DF")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*8")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_z" 24
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "V16SF,V8DF")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*20")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_zmem" 31
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "V16SF,V8DF")
+ 					 (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*20")
+ 
+ ;; SSECMP
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_z" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_z_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "TI,OI")
+ 				     (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "TI,OI")
+ 				     (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "XI")
+ 				     (and (eq_attr "c86_attr" "other,ptest")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "XI")
+ 				     (and (eq_attr "c86_attr" "other,ptest")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecmp_vp" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "!evex")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecmp_vp_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "!evex")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ ;; VPTEST
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				    (and (eq_attr "mode" "TI,OI")
+ 				     (and (eq_attr "c86_attr" "ptest")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test_load" 13
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				    (and (eq_attr "mode" "TI,OI")
+ 				     (and (eq_attr "c86_attr" "ptest")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+ 
+ ;; SSECVT
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "TI,V4SF,V2DF,OI,V8SF,V4DF")
+ 				      (and (not (ior (match_operand:V8DI 1 "register_operand")
+ 						     (match_operand:V8DF 1 "register_operand")))
+ 					   (eq_attr "memory" "none")))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "mode" "TI,V4SF,V2DF,OI,V8SF,V4DF")
+ 				      (and (not (ior (match_operand:V8DI 1 "register_operand")
+ 						     (match_operand:V8DF 1 "register_operand")))
+ 					   (eq_attr "memory" "!none")))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "mode" "OI,V8SF,V4DF")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (ior (match_operand:V8DI 1 "register_operand")
+ 					       (match_operand:V8DF 1 "register_operand"))
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z_load" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "mode" "OI,V8SF,V4DF")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (ior (match_operand:V8DI 1 "memory_operand")
+ 					       (match_operand:V8DF 1 "memory_operand"))
+ 					  (eq_attr "memory" "!none"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_z" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_z_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "!none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecvt" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "prefix" "!evex")
+ 				     (and (eq_attr "mmx_isa" "base")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecvt_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "prefix" "!evex")
+ 				    (and (eq_attr "mmx_isa" "base")
+ 					 (eq_attr "memory" "!none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ 
+ ;; CVTPI
+ (define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "mode" "SF,DI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "mode" "SF,DI")
+ 					 (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_ssecvt_pi" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				    (and (not (eq_attr "mode" "SF,DI"))
+ 				     (and (eq_attr "mmx_isa" "native")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_ssecvt_pi_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (not (eq_attr "mode" "SF,DI"))
+ 				    (and (eq_attr "mmx_isa" "native")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+ 
+ ;; SSEMULADD
+ (define_insn_reservation "c86_4g_m7_avx512_muladd" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemuladd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_muladd_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemuladd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m8_avx512_muladd" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemuladd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m8_avx512_muladd_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemuladd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_muladd_madd" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemuladd,sse")
+ 				   (and (eq_attr "c86_attr" "madd,rcp")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_muladd_madd_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "ssemuladd,sse")
+ 				   (and (eq_attr "c86_attr" "madd,rcp")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ ;; SSE
+ (define_insn_reservation "c86_4g_m7_avx512_sse_range" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "!1")
+ 				      (and (eq_attr "prefix" "evex")
+ 				       (and (eq_attr "c86_decode" "direct")
+ 					   (eq_attr "memory" "none")))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_range_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "!1")
+ 				      (and (eq_attr "c86_decode" "direct")
+ 				       (and (eq_attr "prefix" "evex")
+ 					    (eq_attr "memory" "load")))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "TI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x_load" 9
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "TI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "OI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "OI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "XI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x6")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z_load" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "XI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x6")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_class" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_attr" "other")
+ 				    (and (eq_attr "length_immediate" "1")
+ 				     (and (not (eq_attr "mode" "V32HF,V16SF,V8DF"))
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_class_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "1")
+ 				      (and (not (eq_attr "mode" "V32HF,V16SF,V8DF"))
+ 					   (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_class_z" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "1")
+ 				      (and (eq_attr "mode" "V32HF,V16SF,V8DF")
+ 					   (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_class_z_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "1")
+ 				      (and (eq_attr "mode" "V32HF,V16SF,V8DF")
+ 					   (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sse" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_attr" "rcp,other")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sse_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_attr" "rcp,other")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ ;; SSE SQRT
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_x" 14
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "SF,V4SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x9")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_xload" 21
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "SF,V4SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x9")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_y" 14
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V8SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*9")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_yload" 21
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V8SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*9")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_z" 26
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V16SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*22")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_zload" 33
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V16SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*22")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_x" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "DF,V2DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x15")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_xload" 27
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "DF,V2DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x15")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_y" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V4DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*15")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_yload" 27
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V4DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*15")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_z" 38
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V8DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*34")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_zload" 45
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V8DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*34")
+ 
+ ;; MSKLOG/MSKMOV
+ (define_insn_reservation "c86_4g_m7_avx512_msklog" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "msklog")
+ 				   (eq_attr "c86_decode" "direct")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_msklog_vector" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "msklog")
+ 				   (eq_attr "c86_decode" "vector")))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_reg_k" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mskmov")
+ 				  (and (match_operand 0 "register_operand" "r")
+ 				       (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_xy_k" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mskmov")
+ 				   (ior (match_operand:V2DI 0 "register_operand" "v")
+ 					(match_operand:V4DI 0 "register_operand" "v"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_z_k" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mskmov")
+ 				   (match_operand:V8DI 0 "register_operand" "v")))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_k" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mskmov")
+ 				  (and (match_operand 0 "register_operand" "k")
+ 				       (match_operand 1 "register_operand" "k"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_reg" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mskmov")
+ 				  (and (match_operand 0 "register_operand" "k")
+ 				       (match_operand 1 "register_operand" "r"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_m" 9
+ 			 (and (eq_attr "cpu" "c86_4g_m7,c86_4g_m8")
+ 			      (and (eq_attr "type" "mskmov")
+ 				  (and (match_operand 0 "register_operand" "k")
+ 				       (match_operand 1 "memory_operand"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load")
diff -Nrcpad gcc-16-20260627/gcc/config/i386/driver-i386.cc gcc-16-20260704/gcc/config/i386/driver-i386.cc
*** gcc-16-20260627/gcc/config/i386/driver-i386.cc	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/i386/driver-i386.cc	Sat Jul  4 22:32:07 2026
*************** const char *host_detect_local_cpu (int a
*** 508,515 ****
  	processor = PROCESSOR_C86_4G_M4;
        else if (model == 6)
  	processor = PROCESSOR_C86_4G_M6;
!       else if (model >= 7)
  	processor = PROCESSOR_C86_4G_M7;
      }
    else if (vendor == VENDOR_CENTAUR)
      {
--- 508,517 ----
  	processor = PROCESSOR_C86_4G_M4;
        else if (model == 6)
  	processor = PROCESSOR_C86_4G_M6;
!       else if (model == 7)
  	processor = PROCESSOR_C86_4G_M7;
+       else if (model >= 8)
+ 	processor = PROCESSOR_C86_4G_M8;
      }
    else if (vendor == VENDOR_CENTAUR)
      {
*************** const char *host_detect_local_cpu (int a
*** 869,874 ****
--- 871,879 ----
      case PROCESSOR_C86_4G_M7:
        cpu = "c86-4g-m7";
        break;
+     case PROCESSOR_C86_4G_M8:
+       cpu = "c86-4g-m8";
+       break;
  
      default:
        /* Use something reasonable.  */
diff -Nrcpad gcc-16-20260627/gcc/config/i386/i386-c.cc gcc-16-20260704/gcc/config/i386/i386-c.cc
*** gcc-16-20260627/gcc/config/i386/i386-c.cc	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/i386/i386-c.cc	Sat Jul  4 22:32:07 2026
*************** ix86_target_macros_internal (HOST_WIDE_I
*** 315,320 ****
--- 315,324 ----
        def_or_undef (parse_in, "__c86_4g_m7");
        def_or_undef (parse_in, "__c86_4g_m7__");
        break;
+     case PROCESSOR_C86_4G_M8:
+       def_or_undef (parse_in, "__c86_4g_m8");
+       def_or_undef (parse_in, "__c86_4g_m8__");
+       break;
      /* use PROCESSOR_max to not set/unset the arch macro.  */
      case PROCESSOR_max:
        break;
*************** ix86_target_macros_internal (HOST_WIDE_I
*** 532,537 ****
--- 536,544 ----
      case PROCESSOR_C86_4G_M7:
        def_or_undef (parse_in, "__tune_c86_4g_m7__");
        break;
+     case PROCESSOR_C86_4G_M8:
+       def_or_undef (parse_in, "__tune_c86_4g_m8__");
+       break;
      case PROCESSOR_INTEL:
      case PROCESSOR_GENERIC:
        break;
diff -Nrcpad gcc-16-20260627/gcc/config/i386/i386-features.cc gcc-16-20260704/gcc/config/i386/i386-features.cc
*** gcc-16-20260627/gcc/config/i386/i386-features.cc	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/i386/i386-features.cc	Sat Jul  4 22:32:07 2026
*************** ix86_broadcast_inner (rtx op, machine_mo
*** 3775,3780 ****
--- 3775,3785 ----
      return nullptr;
  
    rtx_insn *insn = DF_REF_INSN (ref);
+ 
+   /* Skip JUMP which happens with asm goto.  */
+   if (JUMP_P (insn))
+     return nullptr;
+ 
    rtx set = single_set (insn);
    if (!set)
      return nullptr;
diff -Nrcpad gcc-16-20260627/gcc/config/i386/i386-options.cc gcc-16-20260704/gcc/config/i386/i386-options.cc
*** gcc-16-20260627/gcc/config/i386/i386-options.cc	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/i386/i386-options.cc	Sat Jul  4 22:32:07 2026
*************** along with GCC; see the file COPYING3.
*** 188,194 ****
  #define m_C86_4G_M4 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M4)
  #define m_C86_4G_M6 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M6)
  #define m_C86_4G_M7 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M7)
! #define m_C86_4G (m_C86_4G_M4 | m_C86_4G_M6 | m_C86_4G_M7)
  
  #define m_GENERIC (HOST_WIDE_INT_1U<<PROCESSOR_GENERIC)
  
--- 188,196 ----
  #define m_C86_4G_M4 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M4)
  #define m_C86_4G_M6 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M6)
  #define m_C86_4G_M7 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M7)
! #define m_C86_4G_M8 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M8)
! #define m_C86_4G (m_C86_4G_M4 | m_C86_4G_M6 | m_C86_4G_M7 \
! 		  | m_C86_4G_M8)
  
  #define m_GENERIC (HOST_WIDE_INT_1U<<PROCESSOR_GENERIC)
  
*************** static const struct processor_costs *pro
*** 821,827 ****
    &znver5_cost,		/* PROCESSOR_ZNVER6.		*/
    &c86_4g_m4_cost,	/* PROCESSOR_C86_4G_M4.		*/
    &c86_4g_m6_cost,	/* PROCESSOR_C86_4G_M6.		*/
!   &c86_4g_m7_cost	/* PROCESSOR_C86_4G_M7.		*/
  };
  
  /* Guarantee that the array is aligned with enum processor_type.  */
--- 823,830 ----
    &znver5_cost,		/* PROCESSOR_ZNVER6.		*/
    &c86_4g_m4_cost,	/* PROCESSOR_C86_4G_M4.		*/
    &c86_4g_m6_cost,	/* PROCESSOR_C86_4G_M6.		*/
!   &c86_4g_m7_cost,	/* PROCESSOR_C86_4G_M7.		*/
!   &c86_4g_m8_cost	/* PROCESSOR_C86_4G_M8.		*/
  };
  
  /* Guarantee that the array is aligned with enum processor_type.  */
diff -Nrcpad gcc-16-20260627/gcc/config/i386/i386.cc gcc-16-20260704/gcc/config/i386/i386.cc
*** gcc-16-20260627/gcc/config/i386/i386.cc	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/i386/i386.cc	Sat Jul  4 22:32:07 2026
*************** ix86_reassociation_width (unsigned int o
*** 25832,25838 ****
  	   || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4
  	   || ix86_tune == PROCESSOR_C86_4G_M4
  	   || ix86_tune == PROCESSOR_C86_4G_M6
! 	   || ix86_tune == PROCESSOR_C86_4G_M7)
     	  && INTEGRAL_MODE_P (mode) && op != PLUS && op != MINUS)
  	return 1;
        /* Znver5 can do 2 integer multiplications per cycle with latency
--- 25832,25839 ----
  	   || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4
  	   || ix86_tune == PROCESSOR_C86_4G_M4
  	   || ix86_tune == PROCESSOR_C86_4G_M6
! 	   || ix86_tune == PROCESSOR_C86_4G_M7
! 	   || ix86_tune == PROCESSOR_C86_4G_M8)
     	  && INTEGRAL_MODE_P (mode) && op != PLUS && op != MINUS)
  	return 1;
        /* Znver5 can do 2 integer multiplications per cycle with latency
diff -Nrcpad gcc-16-20260627/gcc/config/i386/i386.h gcc-16-20260704/gcc/config/i386/i386.h
*** gcc-16-20260627/gcc/config/i386/i386.h	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/i386/i386.h	Sat Jul  4 22:32:07 2026
*************** enum processor_type
*** 2388,2393 ****
--- 2388,2394 ----
    PROCESSOR_C86_4G_M4,
    PROCESSOR_C86_4G_M6,
    PROCESSOR_C86_4G_M7,
+   PROCESSOR_C86_4G_M8,
    PROCESSOR_max
  };
  
*************** constexpr wide_int_bitmask PTA_PANTHERLA
*** 2497,2504 ****
  constexpr wide_int_bitmask PTA_DIAMONDRAPIDS = PTA_GRANITERAPIDS_D
    | PTA_AVXIFMA | PTA_AVXNECONVERT | PTA_AVXVNNIINT16 | PTA_AVXVNNIINT8
    | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_AVX10_2
!   | PTA_APX_F | PTA_AMX_AVX512 | PTA_AMX_FP8 | PTA_AMX_TF32 | PTA_MOVRS
!   | PTA_AMX_MOVRS;
  constexpr wide_int_bitmask PTA_NOVALAKE = PTA_PANTHERLAKE | PTA_PREFETCHI
    | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ
    | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_AVX512VNNI | PTA_AVX512VBMI2
--- 2498,2504 ----
  constexpr wide_int_bitmask PTA_DIAMONDRAPIDS = PTA_GRANITERAPIDS_D
    | PTA_AVXIFMA | PTA_AVXNECONVERT | PTA_AVXVNNIINT16 | PTA_AVXVNNIINT8
    | PTA_CMPCCXADD | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_AVX10_2
!   | PTA_APX_F | PTA_AMX_AVX512 | PTA_AMX_FP8 | PTA_MOVRS | PTA_AMX_MOVRS;
  constexpr wide_int_bitmask PTA_NOVALAKE = PTA_PANTHERLAKE | PTA_PREFETCHI
    | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ
    | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_AVX512VNNI | PTA_AVX512VBMI2
*************** constexpr wide_int_bitmask PTA_C86_4G_M7
*** 2565,2570 ****
--- 2565,2571 ----
    | PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ
    | PTA_AVX512VP2INTERSECT | PTA_VAES | PTA_AVXVNNI | PTA_VPCLMULQDQ
    | PTA_WBNOINVD | PTA_CLWB;
+ constexpr wide_int_bitmask PTA_C86_4G_M8 = PTA_C86_4G_M7;
  
  #ifndef GENERATOR_FILE
  
diff -Nrcpad gcc-16-20260627/gcc/config/i386/i386.md gcc-16-20260704/gcc/config/i386/i386.md
*** gcc-16-20260627/gcc/config/i386/i386.md	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/i386/i386.md	Sat Jul  4 22:32:07 2026
***************
*** 530,536 ****
  (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem,
  		    atom,slm,glm,haswell,generic,lujiazui,yongfeng,amdfam10,bdver1,
  		    bdver2,bdver3,bdver4,btver2,znver1,znver2,znver3,znver4,
! 		    znver5,znver6,c86_4g_m4,c86_4g_m6,c86_4g_m7"
    (const (symbol_ref "ix86_schedule")))
  
  ;; A basic instruction type.  Refinements due to arguments to be
--- 530,536 ----
  (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem,
  		    atom,slm,glm,haswell,generic,lujiazui,yongfeng,amdfam10,bdver1,
  		    bdver2,bdver3,bdver4,btver2,znver1,znver2,znver3,znver4,
! 		    znver5,znver6,c86_4g_m4,c86_4g_m6,c86_4g_m7,c86_4g_m8"
    (const (symbol_ref "ix86_schedule")))
  
  ;; A basic instruction type.  Refinements due to arguments to be
***************
*** 583,589 ****
  		    sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx,
  		    avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
  		    avx512bw,noavx512bw,avx512dq,noavx512dq,fma_or_avx512vl,
! 		    avx512vl,noavx512vl,avxvnni,avx512vnnivl,avx512fp16,avxifma,
  		    avx512ifmavl,avxneconvert,avx512bf16vl,vpclmulqdqvl,
  		    avx_noavx512f,avx_noavx512vl,vaes_avx512vl,noapx_nf,avx10_2"
    (const_string "base"))
--- 583,589 ----
  		    sse_noavx,sse2,sse2_noavx,sse3,sse3_noavx,sse4,sse4_noavx,
  		    avx,noavx,avx2,noavx2,bmi,bmi2,fma4,fma,avx512f,noavx512f,
  		    avx512bw,noavx512bw,avx512dq,noavx512dq,fma_or_avx512vl,
! 		    avx512vl,noavx512vl,avxvnni,avxvnniint8,avx512vnnivl,avx512fp16,avxifma,
  		    avx512ifmavl,avxneconvert,avx512bf16vl,vpclmulqdqvl,
  		    avx_noavx512f,avx_noavx512vl,vaes_avx512vl,noapx_nf,avx10_2"
    (const_string "base"))
***************
*** 967,972 ****
--- 967,973 ----
  	 (eq_attr "isa" "avx512vl") (symbol_ref "TARGET_AVX512VL")
  	 (eq_attr "isa" "noavx512vl") (symbol_ref "!TARGET_AVX512VL")
  	 (eq_attr "isa" "avxvnni") (symbol_ref "TARGET_AVXVNNI")
+ 	 (eq_attr "isa" "avxvnniint8") (symbol_ref "TARGET_AVXVNNIINT8")
  	 (eq_attr "isa" "avx512vnnivl")
  	   (symbol_ref "TARGET_AVX512VNNI && TARGET_AVX512VL")
  	 (eq_attr "isa" "avx512fp16")
***************
*** 1428,1434 ****
  (include "lujiazui.md")
  (include "yongfeng.md")
  (include "c86-4g.md")
! (include "c86-4g-m7.md")
  
  
  ;; Operand and operator predicates and constraints
--- 1429,1435 ----
  (include "lujiazui.md")
  (include "yongfeng.md")
  (include "c86-4g.md")
! (include "c86-4g-m7m8.md")
  
  
  ;; Operand and operator predicates and constraints
***************
*** 7193,7198 ****
--- 7194,7204 ----
        operands[1] = gen_lowpart (<LEAMODE>mode, operands[1]);
        operands[2] = gen_lowpart (<LEAMODE>mode, operands[2]);
      }
+   else
+     /* *lea<mode> and *add<mode>_1_nf have the same pattern, try_split
+        refuses to split an insn into itself, so just request
+        a new recog which will match *lea<mode> which comes first.  */
+     INSN_CODE (curr_insn) = -1;
  })
  
  ;; Convert add to the lea pattern to avoid flags dependency.
diff -Nrcpad gcc-16-20260627/gcc/config/i386/sse.md gcc-16-20260704/gcc/config/i386/sse.md
*** gcc-16-20260627/gcc/config/i386/sse.md	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/i386/sse.md	Sat Jul  4 22:32:07 2026
***************
*** 32508,32522 ****
  })
  
  (define_insn "vpdp<vpdotprodtype>_<mode>"
!   [(set (match_operand:VI4_AVX 0 "register_operand" "=v")
  	(unspec:VI4_AVX
! 	  [(match_operand:VI4_AVX 1 "register_operand" "0")
! 	   (match_operand:VI4_AVX 2 "register_operand" "v")
! 	   (match_operand:VI4_AVX 3 "nonimmediate_operand" "vm")]
  	  VPDOTPROD))]
    "TARGET_AVXVNNIINT8 || TARGET_AVX10_2"
    "vpdp<vpdotprodtype>\t{%3, %2, %0|%0, %2, %3}"
!    [(set_attr "prefix" "maybe_evex")])
  
  (define_insn "vpdp<vpdotprodtype>_v16si"
    [(set (match_operand:V16SI 0 "register_operand" "=v")
--- 32508,32524 ----
  })
  
  (define_insn "vpdp<vpdotprodtype>_<mode>"
!   [(set (match_operand:VI4_AVX 0 "register_operand" "=x,v")
  	(unspec:VI4_AVX
! 	  [(match_operand:VI4_AVX 1 "register_operand" "0,0")
! 	   (match_operand:VI4_AVX 2 "register_operand" "x,v")
! 	   (match_operand:VI4_AVX 3 "nonimmediate_operand" "xjm,vm")]
  	  VPDOTPROD))]
    "TARGET_AVXVNNIINT8 || TARGET_AVX10_2"
    "vpdp<vpdotprodtype>\t{%3, %2, %0|%0, %2, %3}"
!    [(set_attr "prefix" "maybe_evex")
!     (set_attr "addr" "gpr16,*")
!     (set_attr "isa" "avxvnniint8,avx10_2")])
  
  (define_insn "vpdp<vpdotprodtype>_v16si"
    [(set (match_operand:V16SI 0 "register_operand" "=v")
diff -Nrcpad gcc-16-20260627/gcc/config/i386/x86-tune-costs.h gcc-16-20260704/gcc/config/i386/x86-tune-costs.h
*** gcc-16-20260627/gcc/config/i386/x86-tune-costs.h	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/i386/x86-tune-costs.h	Sat Jul  4 22:32:07 2026
*************** struct processor_costs c86_4g_m7_cost =
*** 4612,4620 ****
  					   in SImode and DImode.  */
    2, 2, 3,				/* cost of moving XMM,YMM,ZMM
  					   register.  */
!   {6, 6, 10, 10, 12},			/* cost of loading SSE registers
  					   in 32,64,128,256 and 512-bit.  */
!   {8, 8, 8, 12, 12},			/* cost of storing SSE registers
  					   in 32,64,128,256 and 512-bit.  */
    6, 8,					/* SSE->integer and integer->SSE
  					   moves.  */
--- 4612,4620 ----
  					   in SImode and DImode.  */
    2, 2, 3,				/* cost of moving XMM,YMM,ZMM
  					   register.  */
!   {6, 6, 10, 10, 20},			/* cost of loading SSE registers
  					   in 32,64,128,256 and 512-bit.  */
!   {8, 8, 8, 12, 24},			/* cost of storing SSE registers
  					   in 32,64,128,256 and 512-bit.  */
    6, 8,					/* SSE->integer and integer->SSE
  					   moves.  */
*************** struct processor_costs c86_4g_m7_cost =
*** 4654,4665 ****
  					   Relative to reg-reg move (2).  */
    {8, 8, 8},				/* cost of storing integer
  					   registers.  */
!   {6, 6, 10, 10, 12},			/* cost of loading SSE registers
  					   in 32bit, 64bit, 128bit, 256bit and 512bit */
!   {8, 8, 8, 12, 12},			/* cost of storing SSE register
  					   in 32bit, 64bit, 128bit, 256bit and 512bit */
!   {6, 6, 10, 10, 12},			/* cost of unaligned loads.  */
!   {8, 8, 8, 12, 12},			/* cost of unaligned stores.  */
    2, 2, 3,				/* cost of moving XMM,YMM,ZMM
  					   register.  */
    6,					/* cost of moving SSE register to integer.  */
--- 4654,4665 ----
  					   Relative to reg-reg move (2).  */
    {8, 8, 8},				/* cost of storing integer
  					   registers.  */
!   {6, 6, 10, 10, 20},			/* cost of loading SSE registers
  					   in 32bit, 64bit, 128bit, 256bit and 512bit */
!   {8, 8, 8, 12, 24},			/* cost of storing SSE register
  					   in 32bit, 64bit, 128bit, 256bit and 512bit */
!   {6, 6, 10, 10, 20},			/* cost of unaligned loads.  */
!   {8, 8, 8, 12, 24},			/* cost of unaligned stores.  */
    2, 2, 3,				/* cost of moving XMM,YMM,ZMM
  					   register.  */
    6,					/* cost of moving SSE register to integer.  */
*************** struct processor_costs c86_4g_m7_cost =
*** 4720,4722 ****
--- 4720,4724 ----
    2,					/* Small unroll factor.  */
    COSTS_N_INSNS (2),			/* Branch mispredict scale.  */
  };
+ 
+ struct processor_costs c86_4g_m8_cost = c86_4g_m7_cost;
diff -Nrcpad gcc-16-20260627/gcc/config/i386/x86-tune-sched.cc gcc-16-20260704/gcc/config/i386/x86-tune-sched.cc
*** gcc-16-20260627/gcc/config/i386/x86-tune-sched.cc	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/i386/x86-tune-sched.cc	Sat Jul  4 22:32:07 2026
*************** ix86_issue_rate (void)
*** 94,99 ****
--- 94,100 ----
      case PROCESSOR_C86_4G_M4:
      case PROCESSOR_C86_4G_M6:
      case PROCESSOR_C86_4G_M7:
+     case PROCESSOR_C86_4G_M8:
        return 4;
  
      case PROCESSOR_ICELAKE_CLIENT:
*************** ix86_adjust_cost (rtx_insn *insn, int de
*** 446,451 ****
--- 447,453 ----
      case PROCESSOR_C86_4G_M4:
      case PROCESSOR_C86_4G_M6:
      case PROCESSOR_C86_4G_M7:
+     case PROCESSOR_C86_4G_M8:
        /* Stack engine allows to execute push&pop instructions in parall.  */
        if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
  	  && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
diff -Nrcpad gcc-16-20260627/gcc/config/i386/x86-tune.def gcc-16-20260704/gcc/config/i386/x86-tune.def
*** gcc-16-20260627/gcc/config/i386/x86-tune.def	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/i386/x86-tune.def	Sat Jul  4 22:32:07 2026
*************** DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "u
*** 545,551 ****
  /* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, "use_scatter_2parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7))
  
  
  /* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4
--- 545,551 ----
  /* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, "use_scatter_2parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7 | m_C86_4G_M8))
  
  
  /* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4
*************** DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "u
*** 558,564 ****
  /* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, "use_scatter_4parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7))
  
  /* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more
     elements.  */
--- 558,564 ----
  /* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, "use_scatter_4parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7 | m_C86_4G_M8))
  
  /* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more
     elements.  */
*************** DEF_TUNE (X86_TUNE_USE_GATHER_8PARTS, "u
*** 569,575 ****
  /* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_8PARTS, "use_scatter_8parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7))
  
  /* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or
     smaller FMA chain.  */
--- 569,575 ----
  /* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_8PARTS, "use_scatter_8parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7 | m_C86_4G_M8))
  
  /* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or
     smaller FMA chain.  */
*************** DEF_TUNE (X86_TUNE_SSE_MOVCC_USE_BLENDV,
*** 604,610 ****
  /* X86_TUNE_V4SI_REDUCTION_PREFER_SHUFD: Prefer pshuf to reduce V16QI,
     V8HI, V8HI, V4SI, V4FI, V2DI modes when lshr are costlier. */
  DEF_TUNE (X86_TUNE_SSE_REDUCTION_PREFER_PSHUF,
!    "sse_reduction_prefer_pshuf", m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7)
  
  /*****************************************************************************/
  /* AVX instruction selection tuning (some of SSE flags affects AVX, too)     */
--- 604,611 ----
  /* X86_TUNE_V4SI_REDUCTION_PREFER_SHUFD: Prefer pshuf to reduce V16QI,
     V8HI, V8HI, V4SI, V4FI, V2DI modes when lshr are costlier. */
  DEF_TUNE (X86_TUNE_SSE_REDUCTION_PREFER_PSHUF,
!    "sse_reduction_prefer_pshuf", m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7
! 				 | m_C86_4G_M8)
  
  /*****************************************************************************/
  /* AVX instruction selection tuning (some of SSE flags affects AVX, too)     */
*************** DEF_TUNE (X86_TUNE_AVX256_AVOID_VEC_PERM
*** 640,646 ****
  
  /* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX512 ops are split into two AVX256 ops.  */
  DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4
! 	  | m_C86_4G_M7)
  
  /* It's better to align MOVE_MAX with prefer_vector_width to reduce
     risk of STLF stalls(small store followed by big load.)  */
--- 641,647 ----
  
  /* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX512 ops are split into two AVX256 ops.  */
  DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4
! 	  | m_C86_4G_M7 | m_C86_4G_M8)
  
  /* It's better to align MOVE_MAX with prefer_vector_width to reduce
     risk of STLF stalls(small store followed by big load.)  */
*************** DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES
*** 653,659 ****
  /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
! 	   m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7)
  
  /* X86_TUNE_AVX512_TWO_EPILOGUES: Use two vector epilogues for 512-bit
     vectorized loops.  */
--- 654,660 ----
  /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
! 	   m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7 | m_C86_4G_M8)
  
  /* X86_TUNE_AVX512_TWO_EPILOGUES: Use two vector epilogues for 512-bit
     vectorized loops.  */
*************** DEF_TUNE (X86_TUNE_AVX512_TWO_EPILOGUES,
*** 663,669 ****
  /* X86_TUNE_AVX512_MAKED_EPILOGUES: Use two masked vector epilogues
     when fit.  */
  DEF_TUNE (X86_TUNE_AVX512_MASKED_EPILOGUES, "avx512_masked_epilogues",
! 	  m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7)
  
  /*****************************************************************************/
  /*****************************************************************************/
--- 664,670 ----
  /* X86_TUNE_AVX512_MAKED_EPILOGUES: Use two masked vector epilogues
     when fit.  */
  DEF_TUNE (X86_TUNE_AVX512_MASKED_EPILOGUES, "avx512_masked_epilogues",
! 	  m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7 | m_C86_4G_M8)
  
  /*****************************************************************************/
  /*****************************************************************************/
diff -Nrcpad gcc-16-20260627/gcc/config/loongarch/loongarch.md gcc-16-20260704/gcc/config/loongarch/loongarch.md
*** gcc-16-20260627/gcc/config/loongarch/loongarch.md	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/loongarch/loongarch.md	Sat Jul  4 22:32:07 2026
***************
*** 5000,5018 ****
    ""
  {
    loongarch_output_asm_load_canary (operands[2], operands[1], NULL_RTX);
!   output_asm_insn (which_alternative ? "stptr.d\t%2,%0" : "st.d\t%2,%0",
  		   operands);
    return "ori\t%2,$r0,0";
  }
    [(set_attr "type" "store")
!    (set_attr "length" "20")])
  
! (define_insn "@stack_protect_combined_set_extreme_<mode>"
!   [(set (match_operand:P 0 "memory_operand" "=m,ZC")
!         (unspec:P [(mem:P (match_operand:P 1 "ssp_operand"))] UNSPEC_SSP))
!    (set (match_scratch:P 2 "=&r,&r") (const_int 0))
!    (set (match_scratch:P 3 "=&r,&r") (const_int 0))]
!   ""
  {
    loongarch_output_asm_load_canary (operands[2], operands[1], operands[3]);
    output_asm_insn (which_alternative ? "stptr.d\t%2,%0" : "st.d\t%2,%0",
--- 5000,5024 ----
    ""
  {
    loongarch_output_asm_load_canary (operands[2], operands[1], NULL_RTX);
!   output_asm_insn (which_alternative ? "stptr.d\t%2,%0"
! 				     : "st.<d>\t%2,%0",
  		   operands);
    return "ori\t%2,$r0,0";
  }
    [(set_attr "type" "store")
!    (set_attr "length" "20")
!    (set (attr "enabled")
! 	(if_then_else
! 	  (match_test "!which_alternative || TARGET_64BIT")
! 	  (const_string "yes")
! 	  (const_string "no")))])
  
! (define_insn "stack_protect_combined_set_extreme"
!   [(set (match_operand:DI 0 "memory_operand" "=m,ZC")
!         (unspec:DI [(mem:DI (match_operand:DI 1 "ssp_operand"))] UNSPEC_SSP))
!    (set (match_scratch:DI 2 "=&r,&r") (const_int 0))
!    (set (match_scratch:DI 3 "=&r,&r") (const_int 0))]
!   "TARGET_ABI_LP64"
  {
    loongarch_output_asm_load_canary (operands[2], operands[1], operands[3]);
    output_asm_insn (which_alternative ? "stptr.d\t%2,%0" : "st.d\t%2,%0",
***************
*** 5035,5046 ****
    rtx t = (which_alternative >= 2 ? operands[0] : NULL_RTX);
    loongarch_output_asm_load_canary (operands[3], operands[2], t);
    output_asm_insn ((which_alternative & 1) ? "ldptr.d\t%0,%1"
! 					   : "ld.d\t%0,%1",
  		   operands);
    return "xor\t%0,%0,%3\n\tori\t%3,$r0,0";
  }
    [(set_attr "type" "load,load,load,load")
!    (set_attr "length" "24,24,36,36")])
  
  (define_expand "stack_protect_combined_set"
    [(match_operand 0 "memory_operand")
--- 5041,5057 ----
    rtx t = (which_alternative >= 2 ? operands[0] : NULL_RTX);
    loongarch_output_asm_load_canary (operands[3], operands[2], t);
    output_asm_insn ((which_alternative & 1) ? "ldptr.d\t%0,%1"
! 					   : "ld.<d>\t%0,%1",
  		   operands);
    return "xor\t%0,%0,%3\n\tori\t%3,$r0,0";
  }
    [(set_attr "type" "load,load,load,load")
!    (set_attr "length" "24,24,36,36")
!    (set (attr "enabled")
! 	(if_then_else
! 	  (match_test "!(which_alternative & 1) || TARGET_64BIT")
! 	  (const_string "yes")
! 	  (const_string "no")))])
  
  (define_expand "stack_protect_combined_set"
    [(match_operand 0 "memory_operand")
***************
*** 5048,5058 ****
    ""
  {
    rtx canary = XEXP (operands[1], 0);
!   auto fn = (ssp_normal_operand (canary, VOIDmode)
! 	     ? gen_stack_protect_combined_set_normal
! 	     : gen_stack_protect_combined_set_extreme);
! 
!   emit_insn (fn (Pmode, operands[0], canary));
    DONE;
  })
  
--- 5059,5070 ----
    ""
  {
    rtx canary = XEXP (operands[1], 0);
!   if (ssp_normal_operand (canary, VOIDmode))
!     emit_insn (gen_stack_protect_combined_set_normal (Pmode, operands[0],
! 						      canary));
!   else
!     emit_insn (gen_stack_protect_combined_set_extreme (operands[0],
! 						       canary));
    DONE;
  })
  
diff -Nrcpad gcc-16-20260627/gcc/config/rs6000/crypto.md gcc-16-20260704/gcc/config/rs6000/crypto.md
*** gcc-16-20260627/gcc/config/rs6000/crypto.md	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/rs6000/crypto.md	Sat Jul  4 22:32:07 2026
***************
*** 35,41 ****
     UNSPEC_VSBOX
     UNSPEC_VSHASIGMA
     UNSPEC_VPERMXOR
!    UNSPEC_VPMSUM])
  
  ;; Iterator for VPMSUM/VPERMXOR
  (define_mode_iterator CR_mode [V16QI V8HI V4SI V2DI])
--- 35,56 ----
     UNSPEC_VSBOX
     UNSPEC_VSHASIGMA
     UNSPEC_VPERMXOR
!    UNSPEC_VPMSUM
!    UNSPEC_XXAESENCP
!    UNSPEC_XXAES128ENCP
!    UNSPEC_XXAES192ENCP
!    UNSPEC_XXAES256ENCP
!    UNSPEC_XXAESDECP
!    UNSPEC_XXAES128DECP
!    UNSPEC_XXAES192DECP
!    UNSPEC_XXAES256DECP
!    UNSPEC_XXAESGENLKP
!    UNSPEC_XXAES128GENLKP
!    UNSPEC_XXAES192GENLKP
!    UNSPEC_XXAES256GENLKP
!    UNSPEC_XXGFMUL128
!    UNSPEC_XXGFMUL128GCM
!    UNSPEC_XXGFMUL128XTS])
  
  ;; Iterator for VPMSUM/VPERMXOR
  (define_mode_iterator CR_mode [V16QI V8HI V4SI V2DI])
***************
*** 62,67 ****
--- 77,116 ----
  			  (UNSPEC_VCIPHERLAST  "vcipherlast")
  			  (UNSPEC_VNCIPHERLAST "vncipherlast")])
  
+ ;; Iterator and attribute for AES encrypt/decrypt
+ (define_int_iterator AESACC_base_code [UNSPEC_XXAESENCP
+ 				       UNSPEC_XXAESDECP])
+ (define_int_attr AESACC_base_insn [(UNSPEC_XXAESENCP  "xxaesencp")
+ 				   (UNSPEC_XXAESDECP  "xxaesdecp")])
+ 
+ ;; Iterator and attribute for AES encrypt/decrypt extended mnemonics
+ (define_int_iterator AESACC_code [UNSPEC_XXAES128ENCP
+ 				  UNSPEC_XXAES192ENCP
+ 				  UNSPEC_XXAES256ENCP
+ 				  UNSPEC_XXAES128DECP
+ 				  UNSPEC_XXAES192DECP
+ 				  UNSPEC_XXAES256DECP])
+ (define_int_attr AESACC_insn [(UNSPEC_XXAES128ENCP  "xxaes128encp")
+ 			      (UNSPEC_XXAES192ENCP  "xxaes192encp")
+ 			      (UNSPEC_XXAES256ENCP  "xxaes256encp")
+ 			      (UNSPEC_XXAES128DECP  "xxaes128decp")
+ 			      (UNSPEC_XXAES192DECP  "xxaes192decp")
+ 			      (UNSPEC_XXAES256DECP  "xxaes256decp")])
+ 
+ ;; Iterator and attribute for AES gen last key extended mnemonics
+ (define_int_iterator AESGENLKP_code [UNSPEC_XXAES128GENLKP
+ 				     UNSPEC_XXAES192GENLKP
+ 				     UNSPEC_XXAES256GENLKP])
+ (define_int_attr AESGENLKP_insn [(UNSPEC_XXAES128GENLKP  "xxaes128genlkp")
+ 				 (UNSPEC_XXAES192GENLKP  "xxaes192genlkp")
+ 				 (UNSPEC_XXAES256GENLKP  "xxaes256genlkp")])
+ 
+ ;; Iterator and attribute for AES galois field mult extended mnemonics
+ (define_int_iterator AESGF_code [UNSPEC_XXGFMUL128GCM
+ 				 UNSPEC_XXGFMUL128XTS])
+ (define_int_attr AESGF_insn [(UNSPEC_XXGFMUL128GCM  "xxgfmul128gcm")
+ 			     (UNSPEC_XXGFMUL128XTS  "xxgfmul128xts")])
+ 
  ;; 2 operand crypto instructions
  (define_insn "crypto_<CR_insn>_<mode>"
    [(set (match_operand:CR_vqdi 0 "register_operand" "=v")
***************
*** 111,113 ****
--- 160,213 ----
    "TARGET_CRYPTO"
    "vshasigma<CR_char> %0,%1,%2,%3"
    [(set_attr "type" "vecsimple")])
+ 
+ ;; AES acceleration instructions
+ 
+ (define_insn "<AESACC_base_insn>"
+   [(set (match_operand:OO 0 "vsx_register_operand" "=wa")
+ 	(unspec:OO [(match_operand:OO 1 "vsx_register_operand" "wa")
+ 		    (match_operand:OO 2 "vsx_register_operand" "wa")
+ 		    (match_operand:SI 3 "const_0_to_3_operand" "n")]
+ 		   AESACC_base_code))]
+   "TARGET_FUTURE"
+   "<AESACC_base_insn> %x0,%x1,%x2,%3")
+ 
+ (define_insn "<AESACC_insn>"
+   [(set (match_operand:OO 0 "vsx_register_operand" "=wa")
+     (unspec:OO [(match_operand:OO 1 "vsx_register_operand" "wa")
+ 		(match_operand:OO 2 "vsx_register_operand" "wa")]
+ 	       AESACC_code))]
+   "TARGET_FUTURE"
+   "<AESACC_insn> %x0,%x1,%x2")
+ 
+ (define_insn "xxaesgenlkp"
+   [(set (match_operand:OO 0 "vsx_register_operand" "=wa")
+     (unspec:OO [(match_operand:OO 1 "vsx_register_operand" "wa")
+ 		(match_operand:SI 2 "const_0_to_3_operand" "n")]
+ 	       UNSPEC_XXAESGENLKP))]
+   "TARGET_FUTURE"
+   "xxaesgenlkp %x0,%x1,%2")
+ 
+ (define_insn "<AESGENLKP_insn>"
+   [(set (match_operand:OO 0 "vsx_register_operand" "=wa")
+     (unspec:OO [(match_operand:OO 1 "vsx_register_operand" "wa")]
+ 	       AESGENLKP_code))]
+   "TARGET_FUTURE"
+   "<AESGENLKP_insn> %x0,%x1")
+ 
+ (define_insn "xxgfmul128"
+   [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
+     (unspec:V16QI [(match_operand:V16QI 1 "vsx_register_operand" "wa")
+ 		   (match_operand:V16QI 2 "vsx_register_operand" "wa")
+ 		   (match_operand:SI 3 "const_0_to_1_operand" "n")]
+ 		  UNSPEC_XXGFMUL128))]
+   "TARGET_FUTURE"
+   "xxgfmul128 %x0,%x1,%x2,%3")
+ 
+ (define_insn "<AESGF_insn>"
+   [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa")
+     (unspec:V16QI [(match_operand:V16QI 1 "vsx_register_operand" "wa")
+ 		   (match_operand:V16QI 2 "vsx_register_operand" "wa")]
+ 		  AESGF_code))]
+   "TARGET_FUTURE"
+   "<AESGF_insn> %x0,%x1,%x2")
diff -Nrcpad gcc-16-20260627/gcc/config/rs6000/rs6000-builtin.cc gcc-16-20260704/gcc/config/rs6000/rs6000-builtin.cc
*** gcc-16-20260627/gcc/config/rs6000/rs6000-builtin.cc	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/rs6000/rs6000-builtin.cc	Sat Jul  4 22:32:07 2026
*************** rs6000_invalid_builtin (enum rs6000_gen_
*** 142,147 ****
--- 142,151 ----
      case ENB_FUTURE:
        error ("%qs requires the %qs option", name, "-mcpu=future");
        break;
+     case ENB_FUTURE_ALTIVEC:
+       error ("%qs requires the %qs and %qs options", name, "-mcpu=future",
+ 	     "-maltivec");
+       break;
      default:
      case ENB_ALWAYS:
        gcc_unreachable ();
*************** rs6000_builtin_is_supported (enum rs6000
*** 199,204 ****
--- 203,210 ----
        return TARGET_MMA;
      case ENB_FUTURE:
        return TARGET_FUTURE;
+     case ENB_FUTURE_ALTIVEC:
+       return TARGET_FUTURE && TARGET_ALTIVEC;
      default:
        gcc_unreachable ();
      }
*************** rs6000_expand_builtin (tree exp, rtx tar
*** 3304,3309 ****
--- 3310,3421 ----
        return expand_call (exp, target, ignore);
      }
  
+   if (fcode == RS6000_BIF_PPC_ATOMIC_CAS_QI
+       || fcode == RS6000_BIF_PPC_ATOMIC_CAS_HI
+       || fcode == RS6000_BIF_PPC_ATOMIC_CAS_SI
+       || fcode == RS6000_BIF_PPC_ATOMIC_CAS_DI
+       || fcode == RS6000_BIF_PPC_ATOMIC_CAS_TI)
+     {
+       machine_mode mode; // Get mode based on BIF ID (QImode, SImode, etc.)
+ 
+       switch (fcode)
+ 	{
+ 	case RS6000_BIF_PPC_ATOMIC_CAS_QI:
+ 	  mode = QImode;
+ 	  icode = CODE_FOR_atomic_compare_and_swap_localqi;
+ 	  break;
+ 	case RS6000_BIF_PPC_ATOMIC_CAS_HI:
+ 	  mode = HImode;
+ 	  icode = CODE_FOR_atomic_compare_and_swap_localhi;
+ 	  break;
+ 	case RS6000_BIF_PPC_ATOMIC_CAS_SI:
+ 	  mode = SImode;
+ 	  icode = CODE_FOR_atomic_compare_and_swap_localsi;
+ 	  break;
+ 	case RS6000_BIF_PPC_ATOMIC_CAS_DI:
+ 	  mode = DImode;
+ 	  icode = CODE_FOR_atomic_compare_and_swap_localdi;
+ 	  break;
+ 	case RS6000_BIF_PPC_ATOMIC_CAS_TI:
+ 	  mode = TImode;
+ 	  icode = CODE_FOR_atomic_compare_and_swap_localti;
+ 	  break;
+ 	default:
+ 	  gcc_unreachable ();
+ 	}
+ 
+       // For arg 0 (ptr to data)
+       rtx ptr = expand_expr (CALL_EXPR_ARG (exp, 0), NULL_RTX, Pmode,
+ 			     EXPAND_SUM);
+       ptr = convert_memory_address (Pmode, ptr);
+       rtx mem = gen_rtx_MEM (mode, ptr);
+ 
+       // For arg 1 (expected ptr)
+       rtx exp_ptr = expand_expr (CALL_EXPR_ARG (exp, 1), NULL_RTX, Pmode,
+ 				 EXPAND_SUM);
+       exp_ptr = convert_memory_address (Pmode, exp_ptr);
+       rtx expected_val = gen_reg_rtx (mode);
+       emit_move_insn (expected_val, gen_rtx_MEM (mode, exp_ptr));
+ 
+       // For arg 2 (desired ptr)
+       rtx desired_ptr = expand_expr (CALL_EXPR_ARG (exp, 2), NULL_RTX, Pmode,
+ 				     EXPAND_SUM);
+       desired_ptr = convert_memory_address (Pmode, desired_ptr);
+       rtx desired_val = gen_reg_rtx (mode);
+       emit_move_insn (desired_val, gen_rtx_MEM (mode, desired_ptr));
+ 
+       // Args 3, 4, 5: weak, succ, fail (constants)
+       rtx weak = expand_normal (CALL_EXPR_ARG (exp, 3));
+       rtx succ = expand_normal (CALL_EXPR_ARG (exp, 4));
+       rtx fail = expand_normal (CALL_EXPR_ARG (exp, 5));
+ 
+       // 0: Boolean return (Output)
+       struct expand_operand ops[8];
+       create_output_operand (&ops[0], target, SImode);
+ 
+       // 1: Old value return (Output)
+       rtx old_val = gen_reg_rtx (mode);
+       create_output_operand (&ops[1], old_val, mode);
+ 
+       // 2: The Memory (Fixed/Input - it's a MEM rtx)
+       // We use create_fixed_operand because it's a specific MEM location
+       create_fixed_operand (&ops[2], mem);
+ 
+       // 3: Expected Value (Input)
+       create_input_operand (&ops[3], expected_val, mode);
+ 
+       // 4: Desired Value (Input)
+       create_input_operand (&ops[4], desired_val, mode);
+ 
+       // 5, 6, 7: Weak, Success, Failure (Immediate/Constants)
+       create_input_operand (&ops[5], weak, SImode);
+       create_input_operand (&ops[6], succ, SImode);
+       create_input_operand (&ops[7], fail, SImode);
+ 
+       // Now call expand_insn with the ops array
+       if (!maybe_expand_insn (icode, 8, ops))
+ 	error ("invalid arguments to builtin");
+ 
+       // Create a label for the end of the function.
+       rtx done_label = gen_label_rtx ();
+ 
+       /* Standard Semantics: Update 'expected' ONLY on failure.
+ 	 If target (the boolean result) is NOT 0, the CAS succeeded.
+ 	 In the case of success, we jump straight to the end.  */
+ 
+       // If target != 0 (Success), skip the store.
+       emit_cmp_and_jump_insns (target, const0_rtx, NE, NULL_RTX,
+ 			       SImode, 1, done_label);
+ 
+       // FAILURE PATH: This code runs only if target == 0.
+       rtx expected_mem = gen_rtx_MEM (mode, copy_to_mode_reg (Pmode, exp_ptr));
+       emit_move_insn (expected_mem, old_val);
+ 
+       emit_label (done_label);
+ 
+       return target;
+     }
+ 
    if (bif_is_nosoft (*bifaddr)
        && rs6000_isa_flags & OPTION_MASK_SOFT_FLOAT)
      {
diff -Nrcpad gcc-16-20260627/gcc/config/rs6000/rs6000-builtins.def gcc-16-20260704/gcc/config/rs6000/rs6000-builtins.def
*** gcc-16-20260627/gcc/config/rs6000/rs6000-builtins.def	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/rs6000/rs6000-builtins.def	Sat Jul  4 22:32:07 2026
***************
*** 246,251 ****
--- 246,268 ----
    const double __builtin_unpack_longdouble (long double, const int<1>);
      UNPACK_TF unpacktf {ibmld}
  
+ ; Builtins for ppc specific atomic compare exchange
+   bool __builtin_ppc_atomic_cas_local_qi (char *, char *, char *, const int, \
+ 					  const int, const int);
+     PPC_ATOMIC_CAS_QI nothing {}
+   bool __builtin_ppc_atomic_cas_local_hi (short *, short *, short *, \
+ 					  const int, const int, const int);
+     PPC_ATOMIC_CAS_HI nothing {}
+   bool __builtin_ppc_atomic_cas_local_si (int *, int *, int *, const int, \
+ 					  const int, const int);
+     PPC_ATOMIC_CAS_SI nothing {}
+   bool __builtin_ppc_atomic_cas_local_di (long long *, long long *, \
+ 					  long long *, const int, const int, \
+ 					  const int);
+     PPC_ATOMIC_CAS_DI nothing {}
+   bool __builtin_ppc_atomic_cas_local_ti (__int128 *, __int128 *, __int128 *, \
+ 					  const int, const int, const int);
+     PPC_ATOMIC_CAS_TI nothing {}
  
  ; Builtins that have been around just about forever, but not quite.
  [power5]
***************
*** 3924,3926 ****
--- 3941,3989 ----
  
    void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);
      STXVP nothing {mma,pair}
+ 
+ [future]
+   const v256 __builtin_aes_encrypt_paired (v256, v256, const int<2>);
+     XXAESENCP xxaesencp {}
+ 
+   const v256 __builtin_aes128_encrypt_paired (v256, v256);
+     XXAES128ENCP xxaes128encp {}
+ 
+   const v256 __builtin_aes192_encrypt_paired (v256, v256);
+     XXAES192ENCP xxaes192encp {}
+ 
+   const v256 __builtin_aes256_encrypt_paired (v256, v256);
+     XXAES256ENCP xxaes256encp {}
+ 
+   const v256 __builtin_aes_decrypt_paired (v256, v256, const int<2>);
+     XXAESDECP xxaesdecp {}
+ 
+   const v256 __builtin_aes128_decrypt_paired (v256, v256);
+     XXAES128DECP xxaes128decp {}
+ 
+   const v256 __builtin_aes192_decrypt_paired (v256, v256);
+     XXAES192DECP xxaes192decp {}
+ 
+   const v256 __builtin_aes256_decrypt_paired (v256, v256);
+     XXAES256DECP xxaes256decp {}
+ 
+   const v256 __builtin_aes_genlastkey_paired (v256, const int<2>);
+     XXAESGENLKP xxaesgenlkp {}
+ 
+   const v256 __builtin_aes128_genlastkey_paired (v256);
+     XXAES128GENLKP xxaes128genlkp {}
+ 
+   const v256 __builtin_aes192_genlastkey_paired (v256);
+     XXAES192GENLKP xxaes192genlkp {}
+ 
+   const v256 __builtin_aes256_genlastkey_paired (v256);
+     XXAES256GENLKP xxaes256genlkp {}
+ 
+   const vuc __builtin_galois_field_mult (vuc, vuc, const int<1>);
+     XXGFMUL128 xxgfmul128 {}
+ 
+   const vuc __builtin_galois_field_mult_gcm (vuc, vuc);
+     XXGFMUL128GCM xxgfmul128gcm {}
+ 
+   const vuc __builtin_galois_field_mult_xts (vuc, vuc);
+     XXGFMUL128XTS xxgfmul128xts {}
diff -Nrcpad gcc-16-20260627/gcc/config/rs6000/rs6000-c.cc gcc-16-20260704/gcc/config/rs6000/rs6000-c.cc
*** gcc-16-20260627/gcc/config/rs6000/rs6000-c.cc	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/rs6000/rs6000-c.cc	Sat Jul  4 22:32:07 2026
*************** altivec_build_resolved_builtin (tree *ar
*** 929,935 ****
  
    /* If the number of arguments to an overloaded function increases,
       we must expand this switch.  */
!   gcc_assert (MAX_OVLD_ARGS <= 4);
  
    tree call;
    switch (n)
--- 929,935 ----
  
    /* If the number of arguments to an overloaded function increases,
       we must expand this switch.  */
!   gcc_assert (MAX_OVLD_ARGS <= 6);
  
    tree call;
    switch (n)
*************** altivec_build_resolved_builtin (tree *ar
*** 949,954 ****
--- 949,958 ----
      case 4:
        call = build_call_expr (fndecl, 4, args[0], args[1], args[2], args[3]);
        break;
+     case 6:
+       call = build_call_expr (fndecl, 6, args[0], args[1], args[2], args[3],
+ 			      args[4], args[5]);
+       break;
      default:
        gcc_unreachable ();
      }
*************** find_instance (bool *unsupported_builtin
*** 1710,1720 ****
  
  tree
  altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
! 				    void *passed_arglist, bool)
  {
    rs6000_gen_builtins fcode
      = (rs6000_gen_builtins) DECL_MD_FUNCTION_CODE (fndecl);
  
    /* Return immediately if this isn't an overload.  */
    if (fcode <= RS6000_OVLD_NONE)
      return NULL_TREE;
--- 1714,1835 ----
  
  tree
  altivec_resolve_overloaded_builtin (location_t loc, tree fndecl,
! 				    void *passed_arglist, bool complain)
  {
    rs6000_gen_builtins fcode
      = (rs6000_gen_builtins) DECL_MD_FUNCTION_CODE (fndecl);
  
+   /* Handle __builtin_ppc_atomic_cas_local before standard overload
+      processing.  */
+   if (fcode == RS6000_OVLD_PPC_ATOMIC_CAS)
+     {
+       vec<tree, va_gc> *arglist
+ 	= static_cast<vec<tree, va_gc> *> (passed_arglist);
+ 
+       /* Expected: (void *ptr, void *expected, void *desired,
+       bool weak, int success_order, int failure_order).  */
+       if (vec_safe_length (arglist) != 6)
+ 	{
+ 	  if (complain)
+ 	    error_at (loc, "%qE requires 6 arguments", fndecl);
+ 	  return error_mark_node;
+ 	}
+ 
+       /* Get the first argument to determine the actual type.  */
+       tree arg0 = (*arglist)[0];
+       tree type0 = TREE_TYPE (arg0);
+ 
+       /* Must be a pointer.  */
+       if (!POINTER_TYPE_P (type0))
+ 	{
+ 	  if (complain)
+ 	    error_at (loc, "first argument to %qE must be a pointer", fndecl);
+ 	  return error_mark_node;
+ 	}
+ 
+       /* Get the pointee type.  */
+       tree pointee_type = TREE_TYPE (type0);
+ 
+       /* Must be a complete type.  */
+       if (!COMPLETE_TYPE_P (pointee_type))
+ 	{
+ 	  if (complain)
+ 	    error_at (loc, "first argument to %qE must point to a complete"
+ 		      " type", fndecl);
+ 	  return error_mark_node;
+ 	}
+ 
+       /* Get size in bytes.  */
+       tree size_tree = TYPE_SIZE_UNIT (pointee_type);
+       if (!tree_fits_uhwi_p (size_tree))
+ 	{
+ 	  if (complain)
+ 	    error_at (loc, "type size must be constant");
+ 	  return error_mark_node;
+ 	}
+ 
+       unsigned HOST_WIDE_INT size = tree_to_uhwi (size_tree);
+ 
+       /* Determine which size-specific builtin to use.  */
+       rs6000_gen_builtins target_fcode;
+       tree int_type;
+ 
+       switch (size)
+ 	{
+ 	case 1:
+ 	  target_fcode = RS6000_BIF_PPC_ATOMIC_CAS_QI;
+ 	  int_type = unsigned_char_type_node;
+ 	  break;
+ 	case 2:
+ 	  target_fcode = RS6000_BIF_PPC_ATOMIC_CAS_HI;
+ 	  int_type = short_unsigned_type_node;
+ 	  break;
+ 	case 4:
+ 	  target_fcode = RS6000_BIF_PPC_ATOMIC_CAS_SI;
+ 	  int_type = unsigned_intSI_type_node;
+ 	  break;
+ 	case 8:
+ 	  target_fcode = RS6000_BIF_PPC_ATOMIC_CAS_DI;
+ 	  int_type = long_long_unsigned_type_node;
+ 	  break;
+ 	case 16:
+ 	  target_fcode = RS6000_BIF_PPC_ATOMIC_CAS_TI;
+ 	  int_type = unsigned_intTI_type_node;
+ 	  break;
+ 	default:
+ 	  if (complain)
+ 	    error_at (loc, "size %wu not supported for %qE "
+ 		      "(must be 1, 2, 4, 8, or 16 bytes)", size, fndecl);
+ 	  return error_mark_node;
+ 	}
+ 
+       /* Create pointer type to the appropriate integer type.  */
+       tree int_ptr_type = build_pointer_type (int_type);
+ 
+       /* Cast the three pointer arguments to the appropriate integer
+       pointer type.  */
+       tree new_arg0 = build1 (VIEW_CONVERT_EXPR, int_ptr_type, (*arglist)[0]);
+       tree new_arg1 = build1 (VIEW_CONVERT_EXPR, int_ptr_type, (*arglist)[1]);
+       tree new_arg2 = build1 (VIEW_CONVERT_EXPR, int_ptr_type, (*arglist)[2]);
+ 
+       /* Build new argument list with casted pointers.  */
+       vec<tree, va_gc> *new_arglist;
+       vec_alloc (new_arglist, 6);
+       new_arglist->quick_push (new_arg0);
+       new_arglist->quick_push (new_arg1);
+       new_arglist->quick_push (new_arg2);
+       new_arglist->quick_push ((*arglist)[3]);  /* weak (bool).  */
+       new_arglist->quick_push ((*arglist)[4]);  /* success_memorder.  */
+       new_arglist->quick_push ((*arglist)[5]);  /* failure_memorder.  */
+ 
+       /* Get the target builtin function.  */
+       tree new_fndecl = rs6000_builtin_decls[target_fcode];
+ 
+       /* Build and return the function call.  */
+       return build_function_call_vec (loc, vNULL, new_fndecl, new_arglist,
+ 				      NULL, fndecl);
+     }
+ 
    /* Return immediately if this isn't an overload.  */
    if (fcode <= RS6000_OVLD_NONE)
      return NULL_TREE;
diff -Nrcpad gcc-16-20260627/gcc/config/rs6000/rs6000-gen-builtins.cc gcc-16-20260704/gcc/config/rs6000/rs6000-gen-builtins.cc
*** gcc-16-20260627/gcc/config/rs6000/rs6000-gen-builtins.cc	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/rs6000/rs6000-gen-builtins.cc	Sat Jul  4 22:32:07 2026
*************** enum bif_stanza
*** 233,238 ****
--- 233,239 ----
   BSTZ_P10_64,
   BSTZ_MMA,
   BSTZ_FUTURE,
+  BSTZ_FUTURE_ALTIVEC,
   NUMBIFSTANZAS
  };
  
*************** static stanza_entry stanza_map[NUMBIFSTA
*** 267,273 ****
      { "power10",	BSTZ_P10	},
      { "power10-64",	BSTZ_P10_64	},
      { "mma",		BSTZ_MMA	},
!     { "future",	BSTZ_FUTURE	}
    };
  
  static const char *enable_string[NUMBIFSTANZAS] =
--- 268,275 ----
      { "power10",	BSTZ_P10	},
      { "power10-64",	BSTZ_P10_64	},
      { "mma",		BSTZ_MMA	},
!     { "future",	BSTZ_FUTURE	},
!     { "future-altivec", BSTZ_FUTURE_ALTIVEC }
    };
  
  static const char *enable_string[NUMBIFSTANZAS] =
*************** static const char *enable_string[NUMBIFS
*** 293,299 ****
      "ENB_P10",
      "ENB_P10_64",
      "ENB_MMA",
!     "ENB_FUTURE"
    };
  
  /* Function modifiers provide special handling for const, pure, and fpmath
--- 295,302 ----
      "ENB_P10",
      "ENB_P10_64",
      "ENB_MMA",
!     "ENB_FUTURE",
!     "ENB_FUTURE_ALTIVEC"
    };
  
  /* Function modifiers provide special handling for const, pure, and fpmath
*************** write_decls (void)
*** 2253,2259 ****
    fprintf (header_file, "  ENB_P10,\n");
    fprintf (header_file, "  ENB_P10_64,\n");
    fprintf (header_file, "  ENB_MMA,\n");
!   fprintf (header_file, "  ENB_FUTURE\n");
    fprintf (header_file, "};\n\n");
  
    fprintf (header_file, "#define PPC_MAXRESTROPNDS 3\n");
--- 2256,2263 ----
    fprintf (header_file, "  ENB_P10,\n");
    fprintf (header_file, "  ENB_P10_64,\n");
    fprintf (header_file, "  ENB_MMA,\n");
!   fprintf (header_file, "  ENB_FUTURE,\n");
!   fprintf (header_file, "  ENB_FUTURE_ALTIVEC\n");
    fprintf (header_file, "};\n\n");
  
    fprintf (header_file, "#define PPC_MAXRESTROPNDS 3\n");
diff -Nrcpad gcc-16-20260627/gcc/config/rs6000/rs6000-overload.def gcc-16-20260704/gcc/config/rs6000/rs6000-overload.def
*** gcc-16-20260627/gcc/config/rs6000/rs6000-overload.def	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/rs6000/rs6000-overload.def	Sat Jul  4 22:32:07 2026
***************
*** 79,84 ****
--- 79,92 ----
  ; a semicolon are also treated as blank lines.
  
  
+ ; The following function is not overloaded, but is internally substituted by
+ ; __builtin_ppc_atomic_cas_local_{qi,hi,si,di,ti} based on the first 3
+ ; arguments.
+ [PPC_ATOMIC_CAS, SKIP, __builtin_ppc_atomic_cas_local]
+   bool __builtin_ppc_atomic_cas_local (void *, void *, void *, const int, \
+ 				       const int, const int);
+     PPC_ATOMIC_CAS_QI PPC_ATOMIC_CAS_FAKERY
+ 
  [BCDADD, __builtin_bcdadd, __builtin_vec_bcdadd]
    vsq __builtin_vec_bcdadd (vsq, vsq, const int);
      BCDADD_V1TI
diff -Nrcpad gcc-16-20260627/gcc/config/rs6000/rs6000-protos.h gcc-16-20260704/gcc/config/rs6000/rs6000-protos.h
*** gcc-16-20260627/gcc/config/rs6000/rs6000-protos.h	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/rs6000/rs6000-protos.h	Sat Jul  4 22:32:07 2026
*************** extern bool rs6000_emit_set_const (rtx,
*** 127,133 ****
  extern bool rs6000_emit_cmove (rtx, rtx, rtx, rtx);
  extern bool rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
  extern void rs6000_emit_minmax (rtx, enum rtx_code, rtx, rtx);
! extern void rs6000_expand_atomic_compare_and_swap (rtx op[]);
  extern rtx swap_endian_selector_for_mode (machine_mode mode);
  
  extern void rs6000_expand_atomic_exchange (rtx op[]);
--- 127,133 ----
  extern bool rs6000_emit_cmove (rtx, rtx, rtx, rtx);
  extern bool rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
  extern void rs6000_emit_minmax (rtx, enum rtx_code, rtx, rtx);
! extern void rs6000_expand_atomic_compare_and_swap (rtx op[], bool local);
  extern rtx swap_endian_selector_for_mode (machine_mode mode);
  
  extern void rs6000_expand_atomic_exchange (rtx op[]);
diff -Nrcpad gcc-16-20260627/gcc/config/rs6000/rs6000.cc gcc-16-20260704/gcc/config/rs6000/rs6000.cc
*** gcc-16-20260627/gcc/config/rs6000/rs6000.cc	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/rs6000/rs6000.cc	Sat Jul  4 22:32:07 2026
*************** emit_unlikely_jump (rtx cond, rtx label)
*** 16748,16759 ****
  
  /* A subroutine of the atomic operation splitters.  Emit a load-locked
     instruction in MODE.  For QI/HImode, possibly use a pattern than includes
!    the zero_extend operation.  */
  
  static void
! emit_load_locked (machine_mode mode, rtx reg, rtx mem)
  {
!   rtx (*fn) (rtx, rtx) = NULL;
  
    switch (mode)
      {
--- 16748,16760 ----
  
  /* A subroutine of the atomic operation splitters.  Emit a load-locked
     instruction in MODE.  For QI/HImode, possibly use a pattern than includes
!    the zero_extend operation.  LOCAL indicates the EH bit value for the
!    load-locked instruction.  */
  
  static void
! emit_load_locked (machine_mode mode, rtx reg, rtx mem, rtx local)
  {
!   rtx (*fn) (rtx, rtx, rtx) = NULL;
  
    switch (mode)
      {
*************** emit_load_locked (machine_mode mode, rtx
*** 16780,16786 ****
      default:
        gcc_unreachable ();
      }
!   emit_insn (fn (reg, mem));
  }
  
  /* A subroutine of the atomic operation splitters.  Emit a store-conditional
--- 16781,16787 ----
      default:
        gcc_unreachable ();
      }
!   emit_insn (fn (reg, mem, local));
  }
  
  /* A subroutine of the atomic operation splitters.  Emit a store-conditional
*************** rs6000_finish_atomic_subword (rtx narrow
*** 16950,16956 ****
  /* Expand an atomic compare and swap operation.  */
  
  void
! rs6000_expand_atomic_compare_and_swap (rtx operands[])
  {
    rtx boolval, retval, mem, oldval, newval, cond;
    rtx label1, label2, x, mask, shift;
--- 16951,16957 ----
  /* Expand an atomic compare and swap operation.  */
  
  void
! rs6000_expand_atomic_compare_and_swap (rtx operands[], bool local)
  {
    rtx boolval, retval, mem, oldval, newval, cond;
    rtx label1, label2, x, mask, shift;
*************** rs6000_expand_atomic_compare_and_swap (r
*** 17013,17019 ****
      }
    label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
  
!   emit_load_locked (mode, retval, mem);
  
    x = retval;
    if (mask)
--- 17014,17020 ----
      }
    label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
  
!   emit_load_locked (mode, retval, mem, local ? const1_rtx : const0_rtx);
  
    x = retval;
    if (mask)
*************** rs6000_expand_atomic_exchange (rtx opera
*** 17111,17117 ****
    label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
    emit_label (XEXP (label, 0));
  
!   emit_load_locked (mode, retval, mem);
  
    x = val;
    if (mask)
--- 17112,17118 ----
    label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
    emit_label (XEXP (label, 0));
  
!   emit_load_locked (mode, retval, mem, const0_rtx);
  
    x = val;
    if (mask)
*************** rs6000_expand_atomic_op (enum rtx_code c
*** 17216,17222 ****
    if (before == NULL_RTX)
      before = gen_reg_rtx (mode);
  
!   emit_load_locked (mode, before, mem);
  
    if (code == NOT)
      {
--- 17217,17223 ----
    if (before == NULL_RTX)
      before = gen_reg_rtx (mode);
  
!   emit_load_locked (mode, before, mem, const0_rtx);
  
    if (code == NOT)
      {
diff -Nrcpad gcc-16-20260627/gcc/config/rs6000/sync.md gcc-16-20260704/gcc/config/rs6000/sync.md
*** gcc-16-20260627/gcc/config/rs6000/sync.md	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config/rs6000/sync.md	Sat Jul  4 22:32:07 2026
***************
*** 329,345 ****
  (define_insn "load_locked<mode>"
    [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r")
  	(unspec_volatile:ATOMIC
!          [(match_operand:ATOMIC 1 "memory_operand" "Z")] UNSPECV_LL))]
    ""
!   "<larx> %0,%y1"
    [(set_attr "type" "load_l")])
  
  (define_insn "load_locked<QHI:mode>_si"
    [(set (match_operand:SI 0 "int_reg_operand" "=r")
  	(unspec_volatile:SI
! 	  [(match_operand:QHI 1 "memory_operand" "Z")] UNSPECV_LL))]
    "TARGET_SYNC_HI_QI"
!   "<QHI:larx> %0,%y1"
    [(set_attr "type" "load_l")])
  
  ;; Use PTImode to get even/odd register pairs.
--- 329,347 ----
  (define_insn "load_locked<mode>"
    [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r")
  	(unspec_volatile:ATOMIC
! 	  [(match_operand:ATOMIC 1 "memory_operand" "Z")
! 	   (match_operand:QI 2 "u1bit_cint_operand" "n")] UNSPECV_LL))]
    ""
!   "<larx> %0,%y1,%2"
    [(set_attr "type" "load_l")])
  
  (define_insn "load_locked<QHI:mode>_si"
    [(set (match_operand:SI 0 "int_reg_operand" "=r")
  	(unspec_volatile:SI
! 	  [(match_operand:QHI 1 "memory_operand" "Z")
! 	   (match_operand:QI 2 "u1bit_cint_operand" "n")] UNSPECV_LL))]
    "TARGET_SYNC_HI_QI"
!   "<QHI:larx> %0,%y1,%2"
    [(set_attr "type" "load_l")])
  
  ;; Use PTImode to get even/odd register pairs.
***************
*** 353,359 ****
  
  (define_expand "load_lockedti"
    [(use (match_operand:TI 0 "quad_int_reg_operand"))
!    (use (match_operand:TI 1 "memory_operand"))]
    "TARGET_SYNC_TI"
  {
    rtx op0 = operands[0];
--- 355,362 ----
  
  (define_expand "load_lockedti"
    [(use (match_operand:TI 0 "quad_int_reg_operand"))
!    (use (match_operand:TI 1 "memory_operand"))
!    (use (match_operand:QI 2 "u1bit_cint_operand"))]
    "TARGET_SYNC_TI"
  {
    rtx op0 = operands[0];
***************
*** 367,373 ****
        operands[1] = op1 = change_address (op1, TImode, new_addr);
      }
  
!   emit_insn (gen_load_lockedpti (pti, op1));
    if (WORDS_BIG_ENDIAN)
      emit_move_insn (op0, gen_lowpart (TImode, pti));
    else
--- 370,376 ----
        operands[1] = op1 = change_address (op1, TImode, new_addr);
      }
  
!   emit_insn (gen_load_lockedpti (pti, op1, operands[2]));
    if (WORDS_BIG_ENDIAN)
      emit_move_insn (op0, gen_lowpart (TImode, pti));
    else
***************
*** 381,391 ****
  (define_insn "load_lockedpti"
    [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")
  	(unspec_volatile:PTI
!          [(match_operand:TI 1 "indexed_or_indirect_operand" "Z")] UNSPECV_LL))]
    "TARGET_SYNC_TI
     && !reg_mentioned_p (operands[0], operands[1])
     && quad_int_reg_operand (operands[0], PTImode)"
!   "lqarx %0,%y1"
    [(set_attr "type" "load_l")
     (set_attr "size" "128")])
  
--- 384,395 ----
  (define_insn "load_lockedpti"
    [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r")
  	(unspec_volatile:PTI
! 	  [(match_operand:TI 1 "indexed_or_indirect_operand" "Z")
! 	   (match_operand:QI 2 "u1bit_cint_operand" "n")] UNSPECV_LL))]
    "TARGET_SYNC_TI
     && !reg_mentioned_p (operands[0], operands[1])
     && quad_int_reg_operand (operands[0], PTImode)"
!   "lqarx %0,%y1,%2"
    [(set_attr "type" "load_l")
     (set_attr "size" "128")])
  
***************
*** 462,468 ****
     (match_operand:SI 7 "const_int_operand")]		;; model fail
    ""
  {
!   rs6000_expand_atomic_compare_and_swap (operands);
    DONE;
  })
  
--- 466,487 ----
     (match_operand:SI 7 "const_int_operand")]		;; model fail
    ""
  {
!   rs6000_expand_atomic_compare_and_swap (operands, false);
!   DONE;
! })
! 
! (define_expand "atomic_compare_and_swap_local<mode>"
!   [(match_operand:SI 0 "int_reg_operand")		;; bool out
!    (match_operand:AINT 1 "int_reg_operand")		;; val out
!    (match_operand:AINT 2 "memory_operand")		;; memory
!    (match_operand:AINT 3 "reg_or_short_operand")	;; expected
!    (match_operand:AINT 4 "int_reg_operand")		;; desired
!    (match_operand:SI 5 "const_int_operand")		;; is_weak
!    (match_operand:SI 6 "const_int_operand")		;; model succ
!    (match_operand:SI 7 "const_int_operand")]		;; model fail
!   ""
! {
!   rs6000_expand_atomic_compare_and_swap (operands, true);
    DONE;
  })
  
diff -Nrcpad gcc-16-20260627/gcc/config/s390/s390.cc gcc-16-20260704/gcc/config/s390/s390.cc
*** gcc-16-20260627/gcc/config/s390/s390.cc	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/config/s390/s390.cc	Sat Jul  4 22:32:07 2026
*************** s390_rtx_costs (rtx x, machine_mode mode
*** 3977,3989 ****
      case MEM:
        *total = 0;
        return true;
!       case SET: {
  	rtx dst = SET_DEST (x);
  	rtx src = SET_SRC (x);
  
  	switch (GET_CODE (src))
  	  {
! 	    case IF_THEN_ELSE: {
  	      /* Without this a conditional move instruction would be
  		 accounted as 3 * COSTS_N_INSNS (set, if_then_else,
  		 comparison operator).  That's a bit pessimistic.  */
--- 3977,3991 ----
      case MEM:
        *total = 0;
        return true;
!     case SET:
!       {
  	rtx dst = SET_DEST (x);
  	rtx src = SET_SRC (x);
  
  	switch (GET_CODE (src))
  	  {
! 	  case IF_THEN_ELSE:
! 	    {
  	      /* Without this a conditional move instruction would be
  		 accounted as 3 * COSTS_N_INSNS (set, if_then_else,
  		 comparison operator).  That's a bit pessimistic.  */
*************** s390_rtx_costs (rtx x, machine_mode mode
*** 3992,3997 ****
--- 3994,4005 ----
  		return false;
  
  	      rtx cond = XEXP (src, 0);
+ 	      /* Intermediate RTXs may have a non-compare condition as e.g. a
+ 		 constant like r108={(0x1)?r113:r109} which get folded later
+ 		 on.  */
+ 	      if (GET_RTX_CLASS (GET_CODE (cond)) != RTX_COMPARE
+ 		  && GET_RTX_CLASS (GET_CODE (cond)) != RTX_COMM_COMPARE)
+ 		return false;
  	      if (!CC_REG_P (XEXP (cond, 0)) || !CONST_INT_P (XEXP (cond, 1)))
  		return false;
  
*************** s390_rtx_costs (rtx x, machine_mode mode
*** 4050,4056 ****
  	      /* Otherwise just cost the src.  */
  	      *total += rtx_cost (src, mode, SET, 1, speed);
  	    return true;
! 	    case MEM: {
  	      rtx address = XEXP (dst, 0);
  	      rtx tmp;
  	      HOST_WIDE_INT tmp2;
--- 4058,4065 ----
  	      /* Otherwise just cost the src.  */
  	      *total += rtx_cost (src, mode, SET, 1, speed);
  	    return true;
! 	  case MEM:
! 	    {
  	      rtx address = XEXP (dst, 0);
  	      rtx tmp;
  	      HOST_WIDE_INT tmp2;
diff -Nrcpad gcc-16-20260627/gcc/config.gcc gcc-16-20260704/gcc/config.gcc
*** gcc-16-20260627/gcc/config.gcc	Sat Jun 27 22:32:06 2026
--- gcc-16-20260704/gcc/config.gcc	Sat Jul  4 22:32:07 2026
*************** sapphirerapids alderlake rocketlake eden
*** 768,774 ****
  nano-x2 eden-x4 nano-x4 lujiazui yongfeng shijidadao x86-64 x86-64-v2 \
  x86-64-v3 x86-64-v4 sierraforest graniterapids graniterapids-d grandridge \
  arrowlake arrowlake-s clearwaterforest pantherlake diamondrapids novalake \
! c86-4g-m4 c86-4g-m6 c86-4g-m7 native"
  
  # Additional x86 processors supported by --with-cpu=.  Each processor
  # MUST be separated by exactly one space.
--- 768,774 ----
  nano-x2 eden-x4 nano-x4 lujiazui yongfeng shijidadao x86-64 x86-64-v2 \
  x86-64-v3 x86-64-v4 sierraforest graniterapids graniterapids-d grandridge \
  arrowlake arrowlake-s clearwaterforest pantherlake diamondrapids novalake \
! c86-4g-m4 c86-4g-m6 c86-4g-m7 c86-4g-m8 native"
  
  # Additional x86 processors supported by --with-cpu=.  Each processor
  # MUST be separated by exactly one space.
*************** case ${target} in
*** 4018,4023 ****
--- 4018,4027 ----
  	arch=c86-4g-m7
  	cpu=c86-4g-m7
  	;;
+       c86_4g_m8-*)
+ 	arch=c86-4g-m8
+ 	cpu=c86-4g-m8
+ 	;;
        *)
  	arch=pentiumpro
  	cpu=generic
*************** case ${target} in
*** 4132,4137 ****
--- 4136,4145 ----
  	arch=c86-4g-m7
  	cpu=c86-4g-m7
  	;;
+       c86_4g_m8-*)
+ 	arch=c86-4g-m8
+ 	cpu=c86-4g-m8
+ 	;;
        *)
  	arch=x86-64
  	cpu=generic
diff -Nrcpad gcc-16-20260627/gcc/cp/ChangeLog gcc-16-20260704/gcc/cp/ChangeLog
*** gcc-16-20260627/gcc/cp/ChangeLog	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/cp/ChangeLog	Sat Jul  4 22:32:08 2026
***************
*** 1,3 ****
--- 1,33 ----
+ 2026-07-02  Jason Merrill  <jason@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-07-01  Jason Merrill  <jason@redhat.com>
+ 
+ 	PR c++/124584
+ 	* decl.cc (cp_finish_decl): Use get_temp_regvar for decomp guards.
+ 
+ 2026-07-02  Jason Merrill  <jason@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-07-01  Jason Merrill  <jason@redhat.com>
+ 
+ 	PR c++/121094
+ 	PR c++/117259
+ 	* coroutines.cc (replace_proxy): Handle TARGET_EXPR from.
+ 	(flatten_await_stmt): Pass it.
+ 
+ 2026-07-02  Marek Polacek  <polacek@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-05-19  Marek Polacek  <polacek@redhat.com>
+ 
+ 	PR c++/123536
+ 	* cp-tree.h (process_outer_var_ref): Remove a parameter's name.
+ 	* semantics.cc (mark_use): Return if mark_rvalue_use returns
+ 	error_mark_node.
+ 	(process_outer_var_ref): Return decl when it is
+ 	instantiation-dependent.
+ 
  2026-06-26  Marek Polacek  <polacek@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-16-20260627/gcc/cp/coroutines.cc gcc-16-20260704/gcc/cp/coroutines.cc
*** gcc-16-20260627/gcc/cp/coroutines.cc	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/cp/coroutines.cc	Sat Jul  4 22:32:08 2026
*************** replace_proxy (tree *here, int *do_subtr
*** 2087,2093 ****
  {
    proxy_replace *data = (proxy_replace *) d;
  
!   if (*here == data->from)
      {
        *here = data->to;
        *do_subtree = 0;
--- 2087,2095 ----
  {
    proxy_replace *data = (proxy_replace *) d;
  
!   if (*here == data->from
!       || (TREE_CODE (data->from) == TARGET_EXPR
! 	  && *here == TARGET_EXPR_SLOT (data->from)))
      {
        *here = data->to;
        *do_subtree = 0;
*************** flatten_await_stmt (var_nest_node *n, ha
*** 3326,3333 ****
  		= new var_nest_node (var, init, n->prev, n);
  	      /* We have to replace the target expr... */
  	      *v.entry = var;
! 	      /* ... and any uses of its var.  */
! 	      proxy_replace pr = {TARGET_EXPR_SLOT (t), var};
  	      cp_walk_tree (&n->init, replace_proxy, &pr, NULL);
  	      /* Compiler-generated temporaries can also have uses in
  		 following arms of compound expressions, which will be listed
--- 3328,3335 ----
  		= new var_nest_node (var, init, n->prev, n);
  	      /* We have to replace the target expr... */
  	      *v.entry = var;
! 	      /* ... and any other uses of it or its slot.  */
! 	      proxy_replace pr = {t, var};
  	      cp_walk_tree (&n->init, replace_proxy, &pr, NULL);
  	      /* Compiler-generated temporaries can also have uses in
  		 following arms of compound expressions, which will be listed
diff -Nrcpad gcc-16-20260627/gcc/cp/cp-tree.h gcc-16-20260704/gcc/cp/cp-tree.h
*** gcc-16-20260627/gcc/cp/cp-tree.h	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/cp/cp-tree.h	Sat Jul  4 22:32:08 2026
*************** extern tree finish_base_specifier		(tree
*** 8579,8585 ****
  extern void finish_member_declaration		(tree);
  extern bool outer_automatic_var_p		(tree);
  extern bool parsing_lambda_declarator		();
! extern tree process_outer_var_ref		(tree, tsubst_flags_t, bool force_use = false);
  extern cp_expr finish_id_expression		(tree, tree, tree,
  						 cp_id_kind *,
  						 bool, bool, bool *,
--- 8579,8586 ----
  extern void finish_member_declaration		(tree);
  extern bool outer_automatic_var_p		(tree);
  extern bool parsing_lambda_declarator		();
! extern tree process_outer_var_ref		(tree, tsubst_flags_t,
! 						 bool = false);
  extern cp_expr finish_id_expression		(tree, tree, tree,
  						 cp_id_kind *,
  						 bool, bool, bool *,
diff -Nrcpad gcc-16-20260627/gcc/cp/decl.cc gcc-16-20260704/gcc/cp/decl.cc
*** gcc-16-20260627/gcc/cp/decl.cc	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/cp/decl.cc	Sat Jul  4 22:32:08 2026
*************** cp_finish_decl (tree decl, tree init, bo
*** 10114,10123 ****
  	      tree guard = NULL_TREE;
  	      if (cleanups || cleanup)
  		{
! 		  guard = get_internal_target_expr (boolean_false_node);
! 		  add_stmt (guard);
! 		  guard = TARGET_EXPR_SLOT (guard);
  		}
  	      tree sl = push_stmt_list ();
  	      initialize_local_var (decl, init, true);
  	      if (guard)
--- 10114,10127 ----
  	      tree guard = NULL_TREE;
  	      if (cleanups || cleanup)
  		{
! 		  /* Since the CLEANUP_STMT will refer to the guard, we need it
! 		      to be a variable with the same lifetime.  ??? It might be
! 		      better to use wrap_temporary_cleanups.  */
! 		  guard = get_temp_regvar (boolean_type_node, boolean_false_node);
! 		  /* And make sure register_local_var_uses sees it.  */
! 		  pushdecl (guard);
  		}
+ 
  	      tree sl = push_stmt_list ();
  	      initialize_local_var (decl, init, true);
  	      if (guard)
*************** cp_finish_decl (tree decl, tree init, bo
*** 10143,10151 ****
  		     popped that all, so push those extra cleanups around
  		     the whole sequence with a guard variable.  */
  		  gcc_assert (TREE_CODE (sl) == STATEMENT_LIST);
! 		  guard = get_internal_target_expr (integer_zero_node);
! 		  add_stmt (guard);
! 		  guard = TARGET_EXPR_SLOT (guard);
  		  for (unsigned i = 0; i < n_extra_cleanups; ++i)
  		    {
  		      tree_stmt_iterator tsi = tsi_last (sl);
--- 10147,10154 ----
  		     popped that all, so push those extra cleanups around
  		     the whole sequence with a guard variable.  */
  		  gcc_assert (TREE_CODE (sl) == STATEMENT_LIST);
! 		  guard = get_temp_regvar (integer_type_node, integer_zero_node);
! 		  pushdecl (guard);
  		  for (unsigned i = 0; i < n_extra_cleanups; ++i)
  		    {
  		      tree_stmt_iterator tsi = tsi_last (sl);
diff -Nrcpad gcc-16-20260627/gcc/cp/semantics.cc gcc-16-20260704/gcc/cp/semantics.cc
*** gcc-16-20260627/gcc/cp/semantics.cc	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/cp/semantics.cc	Sat Jul  4 22:32:08 2026
*************** set_contract_capture_flag (tree d, bool
*** 4595,4601 ****
     id-expression, and we do lambda capture.  */
  
  tree
! process_outer_var_ref (tree decl, tsubst_flags_t complain, bool odr_use)
  {
    if (cp_unevaluated_operand)
      {
--- 4595,4602 ----
     id-expression, and we do lambda capture.  */
  
  tree
! process_outer_var_ref (tree decl, tsubst_flags_t complain,
! 		       bool odr_use/*=false*/)
  {
    if (cp_unevaluated_operand)
      {
*************** process_outer_var_ref (tree decl, tsubst
*** 4697,4702 ****
--- 4698,4707 ----
       constant without odr-use.  So don't complain yet.  */
    else if (!odr_use && decl_constant_var_p (var))
      return var;
+   /* Don't complain when DECL is dependent, because it can turn out to
+      be constant (and therefore needing no capture) when instantiating.  */
+   else if (VAR_P (var) && instantiation_dependent_expression_p (var))
+     return var;
    else if (lambda_expr)
      {
        if (complain & tf_error)
*************** process_outer_var_ref (tree decl, tsubst
*** 4715,4721 ****
  	}
        return error_mark_node;
      }
!   else if (processing_contract_condition && (TREE_CODE (decl) == PARM_DECL))
      /* Use of a parameter in a contract condition is fine.  */
      return decl;
    else
--- 4720,4726 ----
  	}
        return error_mark_node;
      }
!   else if (processing_contract_condition && TREE_CODE (decl) == PARM_DECL)
      /* Use of a parameter in a contract condition is fine.  */
      return decl;
    else
diff -Nrcpad gcc-16-20260627/gcc/doc/extend.texi gcc-16-20260704/gcc/doc/extend.texi
*** gcc-16-20260627/gcc/doc/extend.texi	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/doc/extend.texi	Sat Jul  4 22:32:08 2026
*************** defined, then the @code{__builtin_set_fp
*** 23948,23953 ****
--- 23948,23976 ----
  fields.  If not defined, the @code{__builtin_set_fpscr_rn} does not return a
  value.  If the @option{-msoft-float} option is used, the
  @code{__builtin_set_fpscr_rn} built-in will not return a value.
+ @defbuiltin{bool __builtin_ppc_atomic_cas_local (@var{type} *@var{ptr}, @var{type} *@var{expected}, @var{type} *@var{desired}, bool @var{weak}, int @var{success_memorder}, int @var{failure_memorder})}
+ This built-in function implements a PowerPC-specific atomic compare and
+ exchange operation.  It behaves identically to the generic
+ @code{__atomic_compare_exchange} built-in function, with one key difference:
+ it uses an EH (Extended Hint) value of 1 in the @code{lbarx}, @code{lharx},
+ @code{lwarx}, or @code{ldarx} instruction (load-and-reserve indexed).
+ 
+ The EH bit provides a hint to the processor that the program will perform a
+ subsequent store to the specified location.  This hint helps optimize lock
+ contention on PowerPC systems by keeping the lock cacheline in the local
+ processor longer, reducing performance penalties from cache coherence protocol
+ traffic.
+ 
+ For details on the behavior and semantics of the arguments, refer to the
+ @code{__atomic_compare_exchange} documentation.
+ 
+ The first three pointer arguments (@var{ptr}, @var{expected}, and
+ @var{desired}) must point to complete types, and the size of the types they
+ point to must be the same and known at compile time.  The types themselves may
+ differ.  The supported type sizes are 1, 2, 4, 8, or 16 bytes.
+ 
+ @enddefbuiltin
+ 
  
  @node Basic PowerPC Built-in Functions Available on ISA 2.05
  @subsubsection Basic PowerPC Built-in Functions Available on ISA 2.05
*************** The PVIPR documents the following overlo
*** 24696,24701 ****
--- 24719,24725 ----
  * PowerPC AltiVec Built-in Functions Available on ISA 2.07::
  * PowerPC AltiVec Built-in Functions Available on ISA 3.0::
  * PowerPC AltiVec Built-in Functions Available on ISA 3.1::
+ * PowerPC AltiVec/VSX Built-in Functions Available on Future ISA::
  @end menu
  
  @node PowerPC AltiVec Built-in Functions on ISA 2.05
*************** vector unsigned char);
*** 26729,26734 ****
--- 26753,26808 ----
  vector unsigned char);
  @end smallexample
  
+ @node PowerPC AltiVec/VSX Built-in Functions Available on Future ISA
+ @subsubsection PowerPC AltiVec/VSX Built-in Functions Available on Future ISA
+ 
+ The following additional built-in functions are available for the
+ PowerPC family of processors, starting with Future ISA.
+ 
+ Future ISA of the PowerPC may add new instructions for accelerating AES
+ algorithm. GCC provides support for these new instructions through the
+ following built-in functions. The third argument to
+ @var{__builtin_aes_encrypt_paired} and @var{__builtin_aes_decrypt_paired} must
+ be a constant integer that is 0, 1 or 2. The values correspond to 128, 192 and
+ 256 bit AES encryption/decryption respectively. The third argument to
+ @var{__builtin_galois_field_mult} must be a constant integer that is 0 or 1.
+ The values correspond to gcm and xts variant respectively.
+ 
+ @smallexample
+ __vector_pair  __builtin_aes_encrypt_paired (__vector_pair, __vector_pair,
+                                              int);
+ 
+ __vector_pair  __builtin_aes128_encrypt_paired (__vector_pair, __vector_pair);
+ 
+ __vector_pair  __builtin_aes192_encrypt_paired (__vector_pair, __vector_pair);
+ 
+ __vector_pair  __builtin_aes256_encrypt_paired (__vector_pair, __vector_pair);
+ 
+ __vector_pair  __builtin_aes_decrypt_paired (__vector_pair, __vector_pair,
+                                              int);
+ 
+ __vector_pair  __builtin_aes128_decrypt_paired (__vector_pair, __vector_pair);
+ 
+ __vector_pair  __builtin_aes192_decrypt_paired (__vector_pair, __vector_pair);
+ 
+ __vector_pair  __builtin_aes256_decrypt_paired (__vector_pair, __vector_pair);
+ 
+ __vector_pair  __builtin_aes_genlastkey_paired (__vector_pair, int);
+ 
+ __vector_pair  __builtin_aes128_genlastkey_paired (__vector_pair);
+ 
+ __vector_pair  __builtin_aes192_genlastkey_paired (__vector_pair);
+ 
+ __vector_pair  __builtin_aes256_genlastkey_paired (__vector_pair);
+ 
+ vec_t __builtin_galois_field_mult (vec_t, vec_t, int);
+ 
+ vec_t __builtin_galois_field_mult_gcm (vec_t, vec_t);
+ 
+ vec_t __builtin_galois_field_mult_xts (vec_t, vec_t);
+ @end smallexample
+ 
+ 
  @node PowerPC Hardware Transactional Memory Built-in Functions
  @subsection PowerPC Hardware Transactional Memory Built-in Functions
  GCC provides two interfaces for accessing the Hardware Transactional
*************** HYGON Family 18h model 6 shanghai CPU.
*** 29101,29106 ****
--- 29175,29183 ----
  
  @item c86-4g-m7
  HYGON Family 18h model 7 chengdu CPU.
+ 
+ @item c86-4g-m8
+ HYGON Family 18h model 8 suzhou CPU.
  @end table
  
  Here is an example:
diff -Nrcpad gcc-16-20260627/gcc/doc/invoke.texi gcc-16-20260704/gcc/doc/invoke.texi
*** gcc-16-20260627/gcc/doc/invoke.texi	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/doc/invoke.texi	Sat Jul  4 22:32:08 2026
*************** MOVDIRI, MOVDIR64B, ENQCMD, CLDEMOTE, PT
*** 35115,35121 ****
  UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16, AVX512BF16, AMX-FP16,
  PREFETCHI, AMX-COMPLEX, AVX10.1-512, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16,
  AVX-VNNI-INT8, CMPccXADD, SHA512, SM3, SM4, AVX10.2-512, APX_F, AMX-AVX512,
! AMX-FP8, AMX-TF32, MOVRS and AMX-MOVRS instruction set support.
  
  @item bonnell
  @itemx atom
--- 35115,35121 ----
  UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16, AVX512BF16, AMX-FP16,
  PREFETCHI, AMX-COMPLEX, AVX10.1-512, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT16,
  AVX-VNNI-INT8, CMPccXADD, SHA512, SM3, SM4, AVX10.2-512, APX_F, AMX-AVX512,
! AMX-FP8, MOVRS and AMX-MOVRS instruction set support.
  
  @item bonnell
  @itemx atom
*************** HYGON c86-4g-m7 CPU with x86-64, MMX, SS
*** 35409,35414 ****
--- 35409,35423 ----
  SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA,
  XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO,
  CLFLUSHOPT, XSAVES, LZCNT, POPCNT, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD,
+ AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, GFNI, AVX512VNNI, VAES,
+ AVX512BITALG, AVX512VPOPCNTDQ, AVX512VP2INTERSECT, AVXVNNI, VPCLMULQDQ,
+ WBNOINVD instruction set support.
+ 
+ @item c86-4g-m8
+ HYGON c86-4g-m8 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3,
+ SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA,
+ XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO,
+ CLFLUSHOPT, XSAVES, LZCNT, POPCNT, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD,
  AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, GFNI, AVX512VNNI, VAES,
  AVX512BITALG, AVX512VPOPCNTDQ, AVX512VP2INTERSECT, AVXVNNI, VPCLMULQDQ,
  WBNOINVD instruction set support.
diff -Nrcpad gcc-16-20260627/gcc/fortran/ChangeLog gcc-16-20260704/gcc/fortran/ChangeLog
*** gcc-16-20260627/gcc/fortran/ChangeLog	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/fortran/ChangeLog	Sat Jul  4 22:32:08 2026
***************
*** 1,3 ****
--- 1,33 ----
+ 2026-07-03  Jerry DeLisle  <jvdelisle@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-07-03  Jerry DeLisle  <jvdelisle@gcc.gnu.org>
+ 
+ 	PR fortran/126018
+ 	* match.cc (gfc_match_stopcode): Adjust the f2008 error check.If the
+ 	STOP code expr type is unknown, do not error. It will be checked in
+ 	gfc_resolve_code.
+ 	* resolve.cc (gfc_resolve_code): Add checks for EXEC_STOP and
+ 	EXEC_ERROR_STOP.
+ 
+ 2026-06-29  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-05-10  Andre Vehreschild  <vehre@gcc.gnu.org>
+ 		    Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/125051
+ 	* trans-decl.cc (gfc_get_symbol_decl): gfc_defer_symbol_init
+ 	must not be called for PDT types, classes or types with PDT
+ 	(gfc_generate_function_code): If gfc_current_ns is not the same
+ 	as the function namespace, stash it,change it to the function
+ 	namespace and restore after translation of the code.
+ 	* trans-intrinsic.cc (gfc_conv_intrinsic_caf_get): If the array
+ 	is in a module, use the symbol namespace.
+ 	* trans-openmp.cc (gfc_trans_omp_array_reduction_or_udr): If the
+ 	current namespace is not that of the procedure, change to the
+ 	procedure namspace and revert on leaving this function.
+ 
  2026-06-26  Harald Anlauf  <anlauf@gmx.de>
  
  	Backported from master:
diff -Nrcpad gcc-16-20260627/gcc/fortran/match.cc gcc-16-20260704/gcc/fortran/match.cc
*** gcc-16-20260627/gcc/fortran/match.cc	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/fortran/match.cc	Sat Jul  4 22:32:08 2026
*************** checks:
*** 3960,3978 ****
  	  goto cleanup;
  	}
  
!       /* Use the machinery for an initialization expression to reduce the
! 	 stop-code to a constant.  */
!       gfc_reduce_init_expr (e);
! 
!       /* Test for F2008 style STOP stop-code.  */
!       if (e->expr_type != EXPR_CONSTANT && f08)
  	{
! 	  gfc_error ("STOP code at %L must be a scalar default CHARACTER or "
! 		     "INTEGER constant expression", &e->where);
! 	  goto cleanup;
  	}
  
!       if (!(e->ts.type == BT_CHARACTER || e->ts.type == BT_INTEGER))
  	{
  	  gfc_error ("STOP code at %L must be either INTEGER or CHARACTER type",
  		     &e->where);
--- 3960,3981 ----
  	  goto cleanup;
  	}
  
!       /* If this is F2008, it could be an init expression.  */
!       if (f08)
  	{
! 	  gfc_reduce_init_expr (e);
! 	  if (e->expr_type != EXPR_CONSTANT)
! 	    {
! 	      gfc_error ("STOP code at %L must be a scalar constant "
! 			 "expression", &e->where);
! 	      goto cleanup;
! 	    }
  	}
  
!       /* For types known at parse time, check immediately.  For BT_UNKNOWN
! 	 (e.g. a forward-referenced contained function) defer to resolve.  */
!       if (e->ts.type != BT_UNKNOWN
! 	  && !(e->ts.type == BT_CHARACTER || e->ts.type == BT_INTEGER))
  	{
  	  gfc_error ("STOP code at %L must be either INTEGER or CHARACTER type",
  		     &e->where);
diff -Nrcpad gcc-16-20260627/gcc/fortran/resolve.cc gcc-16-20260704/gcc/fortran/resolve.cc
*** gcc-16-20260627/gcc/fortran/resolve.cc	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/fortran/resolve.cc	Sat Jul  4 22:32:08 2026
*************** start:
*** 14316,14321 ****
--- 14316,14340 ----
  
  	case EXEC_STOP:
  	case EXEC_ERROR_STOP:
+ 	  if (code->expr1 != NULL && t)
+ 	    {
+ 	      if (!(code->expr1->ts.type == BT_CHARACTER
+ 		    || code->expr1->ts.type == BT_INTEGER))
+ 		gfc_error ("STOP code at %L must be either INTEGER or CHARACTER "
+ 			   "type", &code->expr1->where);
+ 	      else if (code->expr1->rank != 0)
+ 		gfc_error ("STOP code at %L must be scalar",
+ 			   &code->expr1->where);
+ 	      else if (code->expr1->ts.type == BT_CHARACTER
+ 		       && code->expr1->ts.kind != gfc_default_character_kind)
+ 		gfc_error ("STOP code at %L must be default character KIND=%d",
+ 			   &code->expr1->where, (int) gfc_default_character_kind);
+ 	      else if (code->expr1->ts.type == BT_INTEGER
+ 		       && code->expr1->ts.kind != gfc_default_integer_kind)
+ 		gfc_notify_std (GFC_STD_F2018, "STOP code at %L must be default "
+ 				"integer KIND=%d", &code->expr1->where,
+ 				(int) gfc_default_integer_kind);
+ 	    }
  	  if (code->expr2 != NULL
  	      && (code->expr2->ts.type != BT_LOGICAL
  		  || code->expr2->rank != 0))
diff -Nrcpad gcc-16-20260627/gcc/fortran/trans-decl.cc gcc-16-20260704/gcc/fortran/trans-decl.cc
*** gcc-16-20260627/gcc/fortran/trans-decl.cc	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/fortran/trans-decl.cc	Sat Jul  4 22:32:08 2026
*************** gfc_get_symbol_decl (gfc_symbol * sym)
*** 1707,1720 ****
        && (gfc_current_ns == sym->ns
  	  || (gfc_current_ns == sym->ns->parent
  	      && gfc_current_ns->proc_name->attr.flavor != FL_MODULE))
!       && !(sym->attr.use_assoc || sym->attr.dummy))
      gfc_defer_symbol_init (sym);
  
    if ((sym->ts.type == BT_DERIVED && sym->ts.u.derived->attr.pdt_comp)
        && (gfc_current_ns == sym->ns
  	  || (gfc_current_ns == sym->ns->parent
  	      && gfc_current_ns->proc_name->attr.flavor != FL_MODULE))
!       && !(sym->attr.use_assoc || sym->attr.dummy))
      gfc_defer_symbol_init (sym);
  
    /* Dummy PDT 'len' parameters should be checked when they are explicit.  */
--- 1707,1720 ----
        && (gfc_current_ns == sym->ns
  	  || (gfc_current_ns == sym->ns->parent
  	      && gfc_current_ns->proc_name->attr.flavor != FL_MODULE))
!       && !(sym->attr.use_assoc || sym->attr.dummy || sym->attr.result))
      gfc_defer_symbol_init (sym);
  
    if ((sym->ts.type == BT_DERIVED && sym->ts.u.derived->attr.pdt_comp)
        && (gfc_current_ns == sym->ns
  	  || (gfc_current_ns == sym->ns->parent
  	      && gfc_current_ns->proc_name->attr.flavor != FL_MODULE))
!       && !(sym->attr.use_assoc || sym->attr.dummy || sym->attr.result))
      gfc_defer_symbol_init (sym);
  
    /* Dummy PDT 'len' parameters should be checked when they are explicit.  */
*************** gfc_generate_function_code (gfc_namespac
*** 8311,8317 ****
  
    finish_oacc_declare (ns, sym, false);
  
!   tmp = gfc_trans_code (ns->code);
    gfc_add_expr_to_block (&body, tmp);
  
    /* This permits the return value to be correctly initialized, even when the
--- 8311,8326 ----
  
    finish_oacc_declare (ns, sym, false);
  
!   if (gfc_current_ns != ns)
!     {
!       gfc_namespace *old_current_ns = gfc_current_ns;
!       gfc_current_ns = ns;
!       tmp = gfc_trans_code (ns->code);
!       gfc_current_ns = old_current_ns;
!     }
!   else
!     tmp = gfc_trans_code (ns->code);
! 
    gfc_add_expr_to_block (&body, tmp);
  
    /* This permits the return value to be correctly initialized, even when the
diff -Nrcpad gcc-16-20260627/gcc/fortran/trans-intrinsic.cc gcc-16-20260704/gcc/fortran/trans-intrinsic.cc
*** gcc-16-20260627/gcc/fortran/trans-intrinsic.cc	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/fortran/trans-intrinsic.cc	Sat Jul  4 22:32:08 2026
*************** gfc_conv_intrinsic_caf_get (gfc_se *se,
*** 1238,1243 ****
--- 1238,1244 ----
    array_expr = expr->value.function.actual->expr;
    ns = array_expr->expr_type == EXPR_VARIABLE
  	   && !array_expr->symtree->n.sym->attr.associate_var
+ 	   && !array_expr->symtree->n.sym->module
  	 ? array_expr->symtree->n.sym->ns
  	 : gfc_current_ns;
    type = gfc_typenode_for_spec (&array_expr->ts);
diff -Nrcpad gcc-16-20260627/gcc/fortran/trans-openmp.cc gcc-16-20260704/gcc/fortran/trans-openmp.cc
*** gcc-16-20260627/gcc/fortran/trans-openmp.cc	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/fortran/trans-openmp.cc	Sat Jul  4 22:32:08 2026
*************** gfc_trans_omp_array_reduction_or_udr (tr
*** 2917,2922 ****
--- 2917,2927 ----
    const char *iname;
    bool t;
    gfc_omp_udr *udr = n->u2.udr ? n->u2.udr->udr : NULL;
+   gfc_namespace *old_ns = gfc_current_ns;
+ 
+   if (gfc_current_ns->proc_name
+       && gfc_current_ns->proc_name->ns != gfc_current_ns)
+     gfc_current_ns = gfc_current_ns->proc_name->ns;
  
    decl = OMP_CLAUSE_DECL (c);
    gfc_current_locus = where;
*************** gfc_trans_omp_array_reduction_or_udr (tr
*** 3199,3204 ****
--- 3204,3211 ----
  	  *udr->omp_orig = omp_var_copy[3];
  	}
      }
+ 
+   gfc_current_ns = old_ns;
  }
  
  static tree
diff -Nrcpad gcc-16-20260627/gcc/ira.cc gcc-16-20260704/gcc/ira.cc
*** gcc-16-20260627/gcc/ira.cc	Sat Jun 27 22:32:07 2026
--- gcc-16-20260704/gcc/ira.cc	Sat Jul  4 22:32:08 2026
*************** combine_and_move_insns (void)
*** 3982,3987 ****
--- 3982,3988 ----
  	continue;
  
        rtx_insn *use_insn = 0;
+       bool multiple_insns = false;
        for (df_ref use = DF_REG_USE_CHAIN (regno);
  	   use;
  	   use = DF_REF_NEXT_REG (use))
*************** combine_and_move_insns (void)
*** 3989,3999 ****
  	  {
  	    if (DEBUG_INSN_P (DF_REF_INSN (use)))
  	      continue;
! 	    gcc_assert (!use_insn);
  	    use_insn = DF_REF_INSN (use);
  	  }
        gcc_assert (use_insn);
  
        /* Don't substitute into jumps.  indirect_jump_optimize does
  	 this for anything we are prepared to handle.  */
        if (JUMP_P (use_insn))
--- 3990,4009 ----
  	  {
  	    if (DEBUG_INSN_P (DF_REF_INSN (use)))
  	      continue;
! 	    if (use_insn && DF_REF_INSN (use) != use_insn)
! 	      {
! 		multiple_insns = true;
! 		break;
! 	      }
  	    use_insn = DF_REF_INSN (use);
  	  }
        gcc_assert (use_insn);
  
+       /* If a register is used by more than one insn, we cannot trivially move
+ 	 or delete the definition anymore.  */
+       if (multiple_insns)
+ 	continue;
+ 
        /* Don't substitute into jumps.  indirect_jump_optimize does
  	 this for anything we are prepared to handle.  */
        if (JUMP_P (use_insn))
diff -Nrcpad gcc-16-20260627/gcc/testsuite/ChangeLog gcc-16-20260704/gcc/testsuite/ChangeLog
*** gcc-16-20260627/gcc/testsuite/ChangeLog	Sat Jun 27 22:32:10 2026
--- gcc-16-20260704/gcc/testsuite/ChangeLog	Sat Jul  4 22:32:11 2026
***************
*** 1,3 ****
--- 1,177 ----
+ 2026-07-03  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 
+ 	Backported from master:
+ 	2026-05-07  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 
+ 	* gcc.target/powerpc/aes-builtin-1.c: New test.
+ 	* gcc.target/powerpc/aes-builtin-2.c: New test.
+ 	* gcc.target/powerpc/aes-builtin-3.c: New test.
+ 
+ 2026-07-03  Jerry DeLisle  <jvdelisle@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-07-03  Jerry DeLisle  <jvdelisle@gcc.gnu.org>
+ 
+ 	PR fortran/126018
+ 	* gfortran.dg/stop_function_code_1.f90: New test.
+ 
+ 2026-07-02  Jason Merrill  <jason@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-07-01  Jason Merrill  <jason@redhat.com>
+ 
+ 	PR c++/124584
+ 	* g++.dg/coroutines/torture/tuple-decomp-pr124584.C: New test.
+ 
+ 2026-07-02  Jason Merrill  <jason@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-07-01  Jason Merrill  <jason@redhat.com>
+ 
+ 	PR c++/121094
+ 	PR c++/117259
+ 	* g++.dg/coroutines/pmf-121094.C: New test.
+ 
+ 2026-07-02  Marek Polacek  <polacek@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-05-19  Marek Polacek  <polacek@redhat.com>
+ 
+ 	PR c++/123536
+ 	* g++.dg/cpp0x/lambda/lambda-const12.C: New test.
+ 	* g++.dg/cpp0x/lambda/lambda-const13.C: New test.
+ 	* g++.dg/cpp0x/lambda/lambda-const14.C: New test.
+ 	* g++.dg/template/local11.C: New test.
+ 
+ 2026-07-02  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	Backported from master:
+ 	2026-06-30  Xi Ruoyao  <xry111@xry111.site>
+ 
+ 	* gcc.target/loongarch/ssp-ilp32.c: New test.
+ 
+ 2026-07-01  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-06-26  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	PR target/125972
+ 	* gcc.target/s390/pr125972.c: New test.
+ 
+ 2026-07-01  Eric Botcazou  <ebotcazou@adacore.com>
+ 
+ 	* gnat.dg/opt109.adb: New test.
+ 	* gnat.dg/opt109_pkg.ads, gnat.dg/opt109_pkg.adb: New helper.
+ 
+ 2026-07-01  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 
+ 	Backported from master:
+ 	2026-06-30  Avinash Jayakar  <avinashd@linux.ibm.com>
+ 		    Surya Kumari Jangala  <jskumari@linux.ibm.com>
+ 
+ 	* gcc.target/powerpc/acmp-tst-32bit.c: New test.
+ 	* gcc.target/powerpc/acmp-tst.c: New test.
+ 	* gcc.target/powerpc/acmp-tst-indexed.c: New test.
+ 
+ 2026-07-01  Kewen Lin  <linkewen@hygon.cn>
+ 
+ 	* gcc.target/i386/c86-4g-m7-vect-load-cost-reduc.c: Adjust with
+ 	--param ix86-vect-compare-costs=1.
+ 
+ 2026-07-01  Xin Liu  <liulxx@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-06-23  Xin Liu  <liulxx@hygon.cn>
+ 
+ 	* g++.target/i386/mv33.C: Add c86-4g-m8 target clone test.
+ 	* gcc.target/i386/funcspec-56.inc: Add c86-4g-m8 arch and tune
+ 	target attribute tests.
+ 
+ 2026-07-01  Zhongjie Guo  <guozhongjie@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-06-17  Zhongjie Guo  <guozhongjie@hygon.cn>
+ 
+ 	* gcc.target/i386/c86-4g-m7-vect-load-cost-reduc.c: New test.
+ 
+ 2026-06-30  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-06-12  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	PR rtl-optimization/125173
+ 	* gcc.dg/pr125173-1.c: New test.
+ 
+ 2026-06-30  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	Backported from master:
+ 	2026-04-22  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	PR target/124908
+ 	* gcc.target/aarch64/sve/acle/general/ld1rq_2.c: New test.
+ 
+ 2026-06-30  Alfie Richards  <alfie.richards@arm.com>
+ 
+ 	PR target/125838
+ 	* gcc.target/aarch64/preserve_none_5.c: Update to use AAPCS.
+ 
+ 2026-06-30  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2026-06-21  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	PR target/125883
+ 	* gcc.target/i386/pr125883.c: New test.
+ 
+ 2026-06-29  Alex Coplan  <alex.coplan@arm.com>
+ 
+ 	Backported from master:
+ 	2026-06-23  Alex Coplan  <alex.coplan@arm.com>
+ 
+ 	PR target/125818
+ 	* gcc.target/aarch64/torture/pr125818.c: New test.
+ 
+ 2026-06-29  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-05-28  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR target/125469
+ 	* gcc.target/i386/apx-nf-pr125469.c: New test.
+ 
+ 2026-06-29  Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-05-10  Andre Vehreschild  <vehre@gcc.gnu.org>
+ 		    Paul Thomas  <pault@gcc.gnu.org>
+ 
+ 	PR fortran/125051
+ 	* gfortran.dg/coarray/pr125051.f90: New test.
+ 
+ 2026-06-29  vekumar  <Venkataramanan.Kumar@amd.com>
+ 
+ 	Backported from master:
+ 	2026-06-26  vekumar  <Venkataramanan.Kumar@amd.com>
+ 
+ 	PR target/125949
+ 	* gcc.target/i386/pr125949.c: New test.
+ 
+ 2026-06-29  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	Backported from master:
+ 	2026-06-26  H.J. Lu  <hjl.tools@gmail.com>
+ 
+ 	* gcc.target/i386/builtin-memmove-bounded-1a.c: New test.
+ 	* gcc.target/i386/builtin-memmove-bounded-1b.c: Likewise.
+ 
+ 2026-06-27  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-27  Jakub Jelinek  <jakub@redhat.com>
+ 
+ 	PR target/125992
+ 	* gcc.target/s390/pr125992.c: New test.
+ 
  2026-06-26  Marek Polacek  <polacek@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-16-20260627/gcc/testsuite/g++.dg/coroutines/pmf-121094.C gcc-16-20260704/gcc/testsuite/g++.dg/coroutines/pmf-121094.C
*** gcc-16-20260627/gcc/testsuite/g++.dg/coroutines/pmf-121094.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/g++.dg/coroutines/pmf-121094.C	Sat Jul  4 22:32:12 2026
***************
*** 0 ****
--- 1,23 ----
+ // PR c++/121094
+ 
+ #include <coroutine>
+ 
+ struct Future {
+   struct promise_type {
+     Future get_return_object() { return {}; }
+     std::suspend_never initial_suspend() noexcept { return {}; }
+     std::suspend_never final_suspend() noexcept { return {}; }
+     void return_void() {}
+     void unhandled_exception() {}
+   };
+   bool await_ready() { return true; }
+   void await_suspend(std::coroutine_handle<>) {}
+   void await_resume() {}
+ };
+ 
+ struct Foo {
+   Future test(Future (Foo::*fn)()) {
+     co_await (this->*fn)();
+     co_return;
+   }
+ };
diff -Nrcpad gcc-16-20260627/gcc/testsuite/g++.dg/coroutines/torture/tuple-decomp-pr124584.C gcc-16-20260704/gcc/testsuite/g++.dg/coroutines/torture/tuple-decomp-pr124584.C
*** gcc-16-20260627/gcc/testsuite/g++.dg/coroutines/torture/tuple-decomp-pr124584.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/g++.dg/coroutines/torture/tuple-decomp-pr124584.C	Sat Jul  4 22:32:12 2026
***************
*** 0 ****
--- 1,54 ----
+ #include <coroutine>
+ #include <tuple>
+ 
+ static int g_dtor_count = 0;
+ 
+ struct guard {
+   bool live_ = true;
+   ~guard() { if (live_) ++g_dtor_count; }
+   guard() = default;
+   guard(guard&& o) noexcept
+     : live_(o.live_) {o.live_ = false;}
+ };
+ 
+ static std::coroutine_handle<> g_pending;
+ 
+ struct yield_aw {
+   bool await_ready() const noexcept { return false; }
+   void await_suspend(std::coroutine_handle<> h) noexcept
+   { g_pending = h; }
+   void await_resume() const noexcept {}
+ };
+ 
+ struct task {
+   struct promise_type {
+     task get_return_object() noexcept {
+       return {std::coroutine_handle<
+ 	promise_type>::from_promise(*this)};
+     }
+     std::suspend_never  initial_suspend() noexcept { return {}; }
+     std::suspend_always final_suspend()   noexcept { return {}; }
+     void return_void() noexcept {}
+     void unhandled_exception() { __builtin_abort(); }
+   };
+   std::coroutine_handle<promise_type> h_;
+   ~task() { if (h_) h_.destroy(); }
+ };
+ 
+ std::tuple<guard> make_guarded_tuple() { return {guard{}}; }
+ 
+ task test_fn() {
+   auto [g] = make_guarded_tuple();   // not co_await
+   co_await yield_aw{};                // binding crosses suspend
+   (void)g;
+ }
+ 
+ int main() {
+   auto t = test_fn();
+   auto h = g_pending;
+   g_pending = nullptr;
+   h.resume();
+   __builtin_printf("dtor_count = %d  %s\n",
+ 		   g_dtor_count, g_dtor_count > 0 ? "OK" : "BUG");
+   return g_dtor_count > 0 ? 0 : 1;
+ }
diff -Nrcpad gcc-16-20260627/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const12.C gcc-16-20260704/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const12.C
*** gcc-16-20260627/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const12.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const12.C	Sat Jul  4 22:32:12 2026
***************
*** 0 ****
--- 1,74 ----
+ // PR c++/123536
+ // { dg-do compile { target c++11 } }
+ 
+ int g;
+ 
+ struct S {
+   static int static_data_member;
+ };
+ 
+ template<int = 1>
+ void
+ fn1 ()
+ {
+   int &c = g;
+   auto l = [] { c++; };
+   l();
+ }
+ 
+ template<int N = 1>
+ void
+ fn2 ()
+ {
+   const int &c = N;
+   // TODO This will be valid once we implement P2686.
+   auto l = [] { int i = c; (void) i; }; // { dg-error ".c. is not captured" }
+   l();
+ }
+ 
+ void
+ fn3 ()
+ {
+   int &c = g;
+   auto l = [] { c++; };
+   l();
+ }
+ 
+ void
+ fn4 ()
+ {
+   int n = 42;
+   const int &c = n;
+   auto l = [] { int i = c; (void) i; }; // { dg-error ".c. is not captured" }
+   l();
+ }
+ 
+ template<class T>
+ void
+ fn5 ()
+ {
+   int& c = T::static_data_member;
+   auto l = [] { c++; };
+   l();
+ }
+ 
+ template<class T>
+ void
+ fn6 ()
+ {
+   int& c = T::static_data_member;
+   [&c] {
+     [] { c++; }();
+   };
+ }
+ 
+ void
+ bar ()
+ {
+   fn1 ();
+   fn2 ();
+   fn3 ();
+   fn4 ();
+   fn5<S>();
+   fn6<S>();
+ }
diff -Nrcpad gcc-16-20260627/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const13.C gcc-16-20260704/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const13.C
*** gcc-16-20260627/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const13.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const13.C	Sat Jul  4 22:32:12 2026
***************
*** 0 ****
--- 1,19 ----
+ // PR c++/123536
+ // { dg-do compile { target c++11 } }
+ 
+ int g;
+ 
+ template<class T>
+ void
+ fn1 ()
+ {
+   T c = g;
+   auto l = [] { c++; };
+   l();
+ }
+ 
+ void
+ bar ()
+ {
+   fn1<int&> ();
+ }
diff -Nrcpad gcc-16-20260627/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const14.C gcc-16-20260704/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const14.C
*** gcc-16-20260627/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const14.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-const14.C	Sat Jul  4 22:32:12 2026
***************
*** 0 ****
--- 1,16 ----
+ // PR c++/123536
+ // { dg-do compile { target c++11 } }
+ 
+ template<class T>
+ void
+ f ()
+ {
+   int& c = T::x;	// { dg-error ".x. is not a member of .int." }
+   auto l = [] { c++; };	// { dg-error ".c. is not captured" }
+ }
+ 
+ void
+ g ()
+ {
+   f<int>();
+ }
diff -Nrcpad gcc-16-20260627/gcc/testsuite/g++.dg/template/local11.C gcc-16-20260704/gcc/testsuite/g++.dg/template/local11.C
*** gcc-16-20260627/gcc/testsuite/g++.dg/template/local11.C	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/g++.dg/template/local11.C	Sat Jul  4 22:32:13 2026
***************
*** 0 ****
--- 1,18 ----
+ // PR c++/123536
+ 
+ int g;
+ 
+ template<class T>
+ void
+ fn1 ()
+ {
+   T c = g;
+   struct A { static void f() { c++; } };
+   A::f();
+ }
+ 
+ void
+ bar ()
+ {
+   fn1<int&> ();
+ }
diff -Nrcpad gcc-16-20260627/gcc/testsuite/g++.target/i386/mv33.C gcc-16-20260704/gcc/testsuite/g++.target/i386/mv33.C
*** gcc-16-20260627/gcc/testsuite/g++.target/i386/mv33.C	Sat Jun 27 22:32:12 2026
--- gcc-16-20260704/gcc/testsuite/g++.target/i386/mv33.C	Sat Jul  4 22:32:13 2026
*************** int __attribute__ ((target("arch=c86-4g-
*** 25,30 ****
--- 25,34 ----
    return 3;
  }
  
+ int __attribute__ ((target("arch=c86-4g-m8"))) foo () {
+   return 4;
+ }
+ 
  int main ()
  {
    int val = foo ();
*************** int main ()
*** 35,40 ****
--- 39,46 ----
      assert (val == 2);
    else if (__builtin_cpu_is ("c86-4g-m7"))
      assert (val == 3);
+   else if (__builtin_cpu_is ("c86-4g-m8"))
+     assert (val == 4);
    else
      assert (val == 0);
  
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.dg/pr125173-1.c gcc-16-20260704/gcc/testsuite/gcc.dg/pr125173-1.c
*** gcc-16-20260627/gcc/testsuite/gcc.dg/pr125173-1.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.dg/pr125173-1.c	Sat Jul  4 22:32:14 2026
***************
*** 0 ****
--- 1,17 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O1 -fno-fuse-ops-with-volatile-access -fno-forward-propagate --param=max-cse-insns=0" } */
+ 
+ int a;
+ volatile short b;
+ 
+ struct
+ {
+   char c;
+   int d;
+ } s;
+ 
+ void
+ foo ()
+ {
+   __asm__ ("":"+m" (b), "+m" (s.d), "+m" (a));
+ }
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/aarch64/preserve_none_5.c gcc-16-20260704/gcc/testsuite/gcc.target/aarch64/preserve_none_5.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/aarch64/preserve_none_5.c	Sat Jun 27 22:32:13 2026
--- gcc-16-20260704/gcc/testsuite/gcc.target/aarch64/preserve_none_5.c	Sat Jul  4 22:32:14 2026
***************
*** 6,40 ****
  #include <stdarg.h>
  int foo [[gnu::preserve_none]] (...);
  
! /* Check the pcs argument order is correct. Should be x20-28, x0-7, x10-14, x9, x15 and that the return arg is x0 */
  
  /*
  ** bar:
  ** ...
! **	mov	w15, 23
! **	mov	w9, 22
! **	mov	w14, 21
! **	mov	w13, 20
! **	mov	w12, 19
! **	mov	w11, 18
! **	mov	w10, 17
! **	mov	w7, 16
! **	mov	w6, 15
! **	mov	w5, 14
! **	mov	w4, 13
! **	mov	w3, 12
! **	mov	w2, 11
! **	mov	w1, 10
  **	mov	w0, 9
! **	mov	w28, 8
! **	mov	w27, 7
! **	mov	w26, 6
! **	mov	w25, 5
! **	mov	w24, 4
! **	mov	w23, 3
! **	mov	w22, 2
! **	mov	w21, 1
! **	mov	w20, 0
  **	bl	foo
  **	add	w0, w0, 1
  ** ...
--- 6,56 ----
  #include <stdarg.h>
  int foo [[gnu::preserve_none]] (...);
  
! /* Check preserve_none falls back to AAPCS for variadic functions. */
  
  /*
  ** bar:
  ** ...
! **	mov	w0, 23
! **	mov	w7, 7
! **	mov	w6, 6
! **	mov	w5, 5
! **	mov	w4, 4
! **	mov	w3, 3
! **	mov	w2, 2
! **	mov	w1, 1
! **	str	w0, \[sp, 120\]
! **	mov	w0, 22
! **	str	w0, \[sp, 112\]
! **	mov	w0, 21
! **	str	w0, \[sp, 104\]
! **	mov	w0, 20
! **	str	w0, \[sp, 96\]
! **	mov	w0, 19
! **	str	w0, \[sp, 88\]
! **	mov	w0, 18
! **	str	w0, \[sp, 80\]
! **	mov	w0, 17
! **	str	w0, \[sp, 72\]
! **	mov	w0, 16
! **	str	w0, \[sp, 64\]
! **	mov	w0, 15
! **	str	w0, \[sp, 56\]
! **	mov	w0, 14
! **	str	w0, \[sp, 48\]
! **	mov	w0, 13
! **	str	w0, \[sp, 40\]
! **	mov	w0, 12
! **	str	w0, \[sp, 32\]
! **	mov	w0, 11
! **	str	w0, \[sp, 24\]
! **	mov	w0, 10
! **	str	w0, \[sp, 16\]
  **	mov	w0, 9
! **	str	w0, \[sp, 8\]
! **	mov	w0, 8
! **	str	w0, \[sp\]
! **	mov	w0, 0
  **	bl	foo
  **	add	w0, w0, 1
  ** ...
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/aarch64/sve/acle/general/ld1rq_2.c gcc-16-20260704/gcc/testsuite/gcc.target/aarch64/sve/acle/general/ld1rq_2.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/aarch64/sve/acle/general/ld1rq_2.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/aarch64/sve/acle/general/ld1rq_2.c	Sat Jul  4 22:32:14 2026
***************
*** 0 ****
--- 1,37 ----
+ /* PR target/124908 */
+ /* { dg-options "-O2 -msve-vector-bits=128" } */
+ 
+ #include <arm_sve.h>
+ 
+ /* Verify that folding svld1rq does not ICE with -msve-vector-bits=128.  */
+ 
+ svuint8_t
+ f_u8 (const uint8_t *p)
+ {
+   return svld1rq_u8 (svptrue_b8 (), p);
+ }
+ 
+ svint8_t
+ f_s8 (const int8_t *p)
+ {
+   return svld1rq_s8 (svptrue_b8 (), p);
+ }
+ 
+ svuint16_t
+ f_u16 (const uint16_t *p)
+ {
+   return svld1rq_u16 (svptrue_b16 (), p);
+ }
+ 
+ svuint32_t
+ f_u32 (const uint32_t *p)
+ {
+   return svld1rq_u32 (svptrue_b32 (), p);
+ }
+ 
+ svfloat64_t
+ f_f64 (const float64_t *p)
+ {
+   return svld1rq_f64 (svptrue_b64 (), p);
+ }
+ 
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/aarch64/torture/pr125818.c gcc-16-20260704/gcc/testsuite/gcc.target/aarch64/torture/pr125818.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/aarch64/torture/pr125818.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/aarch64/torture/pr125818.c	Sat Jul  4 22:32:15 2026
***************
*** 0 ****
--- 1,6 ----
+ /* { dg-do compile } */
+ /* { dg-additional-options "-march=armv8.2-a+sve" } */
+ #include <arm_sve.h>
+ void f(svfloat32x2_t *tp, const svfloat32x2_t *tuple, const svfloat32_t *vp) {
+   *tp = svset2_f32(*tuple, 0, *vp);
+ }
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/i386/apx-nf-pr125469.c gcc-16-20260704/gcc/testsuite/gcc.target/i386/apx-nf-pr125469.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/i386/apx-nf-pr125469.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/i386/apx-nf-pr125469.c	Sat Jul  4 22:32:15 2026
***************
*** 0 ****
--- 1,11 ----
+ /* PR target/125469 */
+ /* { dg-do compile { target int128 } } */
+ /* { dg-options "-Ofast -mapx-features=nf" } */
+ 
+ int s;
+ 
+ void
+ foo ()
+ {
+   s /= ((__int128) 0x33333333333333333333333333333333uwb) + 1i;
+ }
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/i386/builtin-memmove-bounded-1a.c gcc-16-20260704/gcc/testsuite/gcc.target/i386/builtin-memmove-bounded-1a.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/i386/builtin-memmove-bounded-1a.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/i386/builtin-memmove-bounded-1a.c	Sat Jul  4 22:32:15 2026
***************
*** 0 ****
--- 1,132 ----
+ /* { dg-do run } */
+ /* { dg-options "-O2 -minline-all-stringops" } */
+ 
+ /* Test -O2 -minline-all-stringops on memmove with various bounds.  */
+ 
+ #include <stdlib.h>
+ 
+ #define MAX_LENGTH 512
+ #define TOTAL (4 * MAX_LENGTH)
+ 
+ #define MEMMOVE_BOUND(BOUND) \
+ __attribute__ ((noipa, noinline)) \
+ static char * \
+ memmove_##BOUND (char *dest, char *src, size_t len) \
+ { \
+   if (len <= BOUND) \
+     return __builtin_memmove (dest, src, len); \
+   else \
+     return dest; \
+ }
+ 
+ #define CHECK_MEMMOVE_BOUND(BOUND, SIZE) \
+   { \
+     char *dest, *src; \
+     unsigned int offset; \
+     for (i = 0; i < SIZE; i++) \
+       buf[i] = 'a'; \
+     for (; i < 2 * SIZE; i++) \
+       buf[i] = 'A'; \
+     for (; i < 3 * SIZE; i++) \
+       buf[i] = 'b'; \
+     for (i = 0; i < 3 * SIZE; i++) \
+       copy[i] = buf[i]; \
+     offset = SIZE - (SIZE) / 2; \
+     dest = &buf[0]; \
+     src = &buf[offset]; \
+     p = memmove_##BOUND (dest, src, SIZE); \
+     if (p != dest) \
+       abort (); \
+     for (i = 0; i < SIZE; i++) \
+       if (dest[i] != copy[offset + i]) \
+         abort (); \
+     for (i = 0; i < 3 * SIZE; i++) \
+       buf[i] = copy[i]; \
+     dest = &buf[offset]; \
+     src = &buf[0]; \
+     p = memmove_##BOUND (dest, src, SIZE); \
+     if (p != dest) \
+       abort (); \
+     for (i = 0; i < SIZE; i++) \
+       if (dest[i] != copy[i]) \
+         abort (); \
+   }
+ 
+ #define CHECK_MEMMOVE(SIZE) \
+   CHECK_MEMMOVE_BOUND (SIZE, SIZE) \
+   if (SIZE > 1) \
+     CHECK_MEMMOVE_BOUND (SIZE, SIZE - 1) \
+   if (SIZE > 2) \
+     CHECK_MEMMOVE_BOUND (SIZE, SIZE - 2) \
+   if (SIZE > 3) \
+     CHECK_MEMMOVE_BOUND (SIZE, SIZE - 3) \
+   if (SIZE > 4) \
+     CHECK_MEMMOVE_BOUND (SIZE, SIZE - 4) \
+   if (SIZE > 5) \
+     CHECK_MEMMOVE_BOUND (SIZE, SIZE - 5) \
+   if (SIZE > 6) \
+     CHECK_MEMMOVE_BOUND (SIZE, SIZE - 6) \
+   if (SIZE > 7) \
+     CHECK_MEMMOVE_BOUND (SIZE, SIZE - 7)
+ 
+ char buf[TOTAL];
+ char copy[TOTAL];
+ 
+ MEMMOVE_BOUND (0);
+ MEMMOVE_BOUND (1);
+ MEMMOVE_BOUND (2);
+ MEMMOVE_BOUND (3);
+ MEMMOVE_BOUND (4);
+ MEMMOVE_BOUND (5);
+ MEMMOVE_BOUND (7);
+ MEMMOVE_BOUND (8);
+ MEMMOVE_BOUND (9);
+ MEMMOVE_BOUND (15);
+ MEMMOVE_BOUND (16);
+ MEMMOVE_BOUND (17);
+ MEMMOVE_BOUND (31);
+ MEMMOVE_BOUND (32);
+ MEMMOVE_BOUND (33);
+ MEMMOVE_BOUND (63);
+ MEMMOVE_BOUND (64);
+ MEMMOVE_BOUND (65);
+ MEMMOVE_BOUND (127);
+ MEMMOVE_BOUND (128);
+ MEMMOVE_BOUND (129);
+ MEMMOVE_BOUND (255);
+ MEMMOVE_BOUND (256);
+ MEMMOVE_BOUND (257);
+ 
+ int
+ main (void)
+ {
+   unsigned int i;
+   char *p;
+ 
+   CHECK_MEMMOVE (0);
+   CHECK_MEMMOVE (1);
+   CHECK_MEMMOVE (2);
+   CHECK_MEMMOVE (3);
+   CHECK_MEMMOVE (4);
+   CHECK_MEMMOVE (5);
+   CHECK_MEMMOVE (7);
+   CHECK_MEMMOVE (8);
+   CHECK_MEMMOVE (9);
+   CHECK_MEMMOVE (15);
+   CHECK_MEMMOVE (16);
+   CHECK_MEMMOVE (17);
+   CHECK_MEMMOVE (31);
+   CHECK_MEMMOVE (32);
+   CHECK_MEMMOVE (33);
+   CHECK_MEMMOVE (63);
+   CHECK_MEMMOVE (64);
+   CHECK_MEMMOVE (65);
+   CHECK_MEMMOVE (127);
+   CHECK_MEMMOVE (128);
+   CHECK_MEMMOVE (129);
+   CHECK_MEMMOVE (255);
+   CHECK_MEMMOVE (256);
+   CHECK_MEMMOVE (257);
+ 
+   return 0;
+ }
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/i386/builtin-memmove-bounded-1b.c gcc-16-20260704/gcc/testsuite/gcc.target/i386/builtin-memmove-bounded-1b.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/i386/builtin-memmove-bounded-1b.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/i386/builtin-memmove-bounded-1b.c	Sat Jul  4 22:32:15 2026
***************
*** 0 ****
--- 1,6 ----
+ /* { dg-do run } */
+ /* { dg-options "-O0 -minline-all-stringops" } */
+ 
+ /* Test -O0 -minline-all-stringops on memmove with various bounds.  */
+ 
+ #include "builtin-memmove-bounded-1a.c"
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/i386/c86-4g-m7-vect-load-cost-reduc.c gcc-16-20260704/gcc/testsuite/gcc.target/i386/c86-4g-m7-vect-load-cost-reduc.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/i386/c86-4g-m7-vect-load-cost-reduc.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/i386/c86-4g-m7-vect-load-cost-reduc.c	Sat Jul  4 22:32:15 2026
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O3 -march=c86-4g-m7 -mprefer-vector-width=512 --param ix86-vect-compare-costs=1 -ffast-math -fdump-tree-vect-details" } */
+ 
+ #define N 1024
+ 
+ void foo (double *__restrict a, double *__restrict b, double *out)
+ {
+   double sum = 1.0;
+ 
+   for (int i = 0; i < N; ++i)
+     sum += a[i] * b[i];
+ 
+   out[0] = sum;
+ }
+ 
+ /* On c86-4g-m7, 512-bit memory costs should model two 256-bit operations on
+    split-regs targets.  This loop exercises the load side of that model: once
+    the normalized body cost no longer favors 64-byte vectors, the reduction
+    epilogue cost makes 32-byte vectorization preferable.  */
+ /* { dg-final { scan-tree-dump-times "optimized: loop vectorized using 32 byte vectors" 1 "vect" } } */
+ /* { dg-final { scan-tree-dump-not "optimized: loop vectorized using 64 byte vectors" "vect" } } */
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/i386/funcspec-56.inc gcc-16-20260704/gcc/testsuite/gcc.target/i386/funcspec-56.inc
*** gcc-16-20260627/gcc/testsuite/gcc.target/i386/funcspec-56.inc	Sat Jun 27 22:32:14 2026
--- gcc-16-20260704/gcc/testsuite/gcc.target/i386/funcspec-56.inc	Sat Jul  4 22:32:15 2026
*************** extern void test_arch_znver6 (void)
*** 242,247 ****
--- 242,248 ----
  extern void test_arch_c86_4g_m4 (void)          __attribute__((__target__("arch=c86-4g-m4")));
  extern void test_arch_c86_4g_m6 (void)          __attribute__((__target__("arch=c86-4g-m6")));
  extern void test_arch_c86_4g_m7 (void)          __attribute__((__target__("arch=c86-4g-m7")));
+ extern void test_arch_c86_4g_m8 (void)          __attribute__((__target__("arch=c86-4g-m8")));
  
  extern void test_tune_nocona (void)		__attribute__((__target__("tune=nocona")));
  extern void test_tune_core2 (void)		__attribute__((__target__("tune=core2")));
*************** extern void test_tune_znver6 (void)
*** 273,278 ****
--- 274,280 ----
  extern void test_tune_c86_4g_m4 (void)          __attribute__((__target__("tune=c86-4g-m4")));
  extern void test_tune_c86_4g_m6 (void)          __attribute__((__target__("tune=c86-4g-m6")));
  extern void test_tune_c86_4g_m7 (void)          __attribute__((__target__("tune=c86-4g-m7")));
+ extern void test_tune_c86_4g_m8 (void)          __attribute__((__target__("tune=c86-4g-m8")));
  
  extern void test_fpmath_sse (void)		__attribute__((__target__("sse2,fpmath=sse")));
  extern void test_fpmath_387 (void)		__attribute__((__target__("sse2,fpmath=387")));
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/i386/pr125883.c gcc-16-20260704/gcc/testsuite/gcc.target/i386/pr125883.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/i386/pr125883.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/i386/pr125883.c	Sat Jul  4 22:32:15 2026
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O3 -march=x86-64" } */
+ 
+ int a, b;
+ int c[0], d[0];
+ void
+ foo (void)
+ {
+   __asm__ goto("" : "=r"(a) : : : f);
+ f:
+   for (; b; b++)
+     c[b] = d[b] = c[b] + a;
+ }
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/i386/pr125949.c gcc-16-20260704/gcc/testsuite/gcc.target/i386/pr125949.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/i386/pr125949.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/i386/pr125949.c	Sat Jul  4 22:32:15 2026
***************
*** 0 ****
--- 1,38 ----
+ /* PR target/125949 */
+ /* On a target with AVX-VNNI-INT8 the vpdpb{ss,su,uu}d[s] instructions only
+    have a VEX encoding.  Even under register pressure the compiler must stay
+    within xmm/ymm0-15 for these insns and must not allocate xmm/ymm16-31 and
+    emit an EVEX-encoded vpdpb* using a high register.  -mavx512vl exposes the
+    xmm/ymm16-31 register file so the allocator would otherwise be tempted to
+    use it.  */
+ /* { dg-do compile } */
+ /* { dg-options "-O2 -mavxvnniint8 -mavx512vl" } */
+ /* { dg-final { scan-assembler-not "vpdpb\[a-z\]+\[ \\t\]+\[^\n\]*%\[xy\]mm(1\[6-9\]|2\[0-9\]|3\[01\])" } } */
+ 
+ #include <immintrin.h>
+ 
+ #define NACC 32
+ 
+ void
+ foo (unsigned int *restrict out, const unsigned char *restrict a,
+      const unsigned char *restrict b, int n)
+ {
+   __m256i acc[NACC];
+ 
+   for (int k = 0; k < NACC; k++)
+     acc[k] = _mm256_setzero_si256 ();
+ 
+   for (int i = 0; i < n; i++)
+     {
+       __m256i vb = _mm256_loadu_si256 ((const __m256i *) (b + 32 * (i & 7)));
+       for (int k = 0; k < NACC; k++)
+ 	{
+ 	  __m256i va
+ 	    = _mm256_loadu_si256 ((const __m256i *) (a + 32 * ((i + k) & 15)));
+ 	  acc[k] = _mm256_dpbuud_epi32 (acc[k], va, vb);
+ 	}
+     }
+ 
+   for (int k = 0; k < NACC; k++)
+     _mm256_storeu_si256 ((__m256i *) (out + 8 * k), acc[k]);
+ }
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/loongarch/ssp-ilp32.c gcc-16-20260704/gcc/testsuite/gcc.target/loongarch/ssp-ilp32.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/loongarch/ssp-ilp32.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/loongarch/ssp-ilp32.c	Sat Jul  4 22:32:15 2026
***************
*** 0 ****
--- 1,9 ----
+ /* { dg-options "-march=la32v1.0 -mabi=ilp32s -fstack-protector-strong" } */
+ /* { dg-final { scan-assembler-not "ld\\\.d" } } */
+ /* { dg-final { scan-assembler-not "st\\\.d" } } */
+ 
+ void test()
+ {
+ 	int x;
+ 	asm("":"+m"(x));
+ }
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/powerpc/acmp-tst-32bit.c gcc-16-20260704/gcc/testsuite/gcc.target/powerpc/acmp-tst-32bit.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/powerpc/acmp-tst-32bit.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/powerpc/acmp-tst-32bit.c	Sat Jul  4 22:32:15 2026
***************
*** 0 ****
--- 1,61 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target ilp32 } */
+ 
+ /* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+ 
+ bool
+ word_exchange_qi (signed char *ptr, signed char *expected, signed char *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_uqi (unsigned char *ptr, unsigned char *expected,
+                    unsigned char *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_hi (short *ptr, short *expected, short *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_shi (signed short *ptr, signed short *expected,
+                    signed short *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_uhi (unsigned short *ptr, unsigned short *expected,
+                    unsigned short *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_si (int *ptr, int *expected, int *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_ssi (signed int *ptr, signed int *expected, signed int *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_usi (unsigned int *ptr, unsigned int *expected,
+                    unsigned int *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ 
+ /* { dg-final { scan-assembler-times {\mlbarx +[0-9]+,[0-9]+,[0-9]+,1} 2 } } */
+ /* { dg-final { scan-assembler-times {\mlharx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */
+ /* { dg-final { scan-assembler-times {\mlwarx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/powerpc/acmp-tst-indexed.c gcc-16-20260704/gcc/testsuite/gcc.target/powerpc/acmp-tst-indexed.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/powerpc/acmp-tst-indexed.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/powerpc/acmp-tst-indexed.c	Sat Jul  4 22:32:15 2026
***************
*** 0 ****
--- 1,165 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+ 
+ // Need power8 for l<b,h,q>arx
+ /* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+ 
+ typedef struct udt_1
+ {
+   char *a;
+ } udt_1t;
+ typedef struct udt_2
+ {
+   char a;
+   char b;
+ } udt_2t;
+ typedef struct udt_4
+ {
+   short a;
+   short b;
+ } udt_4t;
+ typedef struct udt_8
+ {
+   int a;
+   int b;
+ } udt_8t;
+ bool
+ word_exchange_nqi (char *ptr, char *expected, char *desired,
+ 		   unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_qi (signed char *ptr, signed char *expected, signed char *desired,
+ 		  unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_uqi (unsigned char *ptr, unsigned char *expected,
+                    unsigned char *desired, unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_hi (short *ptr, short *expected, short *desired,
+ 		  unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_shi (signed short *ptr, signed short *expected,
+                    signed short *desired, unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_uhi (unsigned short *ptr, unsigned short *expected,
+                    unsigned short *desired, unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_si (int *ptr, int *expected, int *desired, unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_ssi (signed int *ptr, signed int *expected, signed int *desired,
+ 		   unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_usi (unsigned int *ptr, unsigned int *expected,
+                    unsigned int *desired, unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_di (long long *ptr, long long *expected, long long *desired,
+ 		  unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_sdi (signed long long *ptr, signed long long *expected,
+                    signed long long *desired, unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udi (unsigned long long *ptr, unsigned long long *expected,
+                    unsigned long long *desired, unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_f32 (float *ptr, float *expected, float *desired,
+ 		   unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_f64 (double *ptr, double *expected, double *desired,
+ 		   unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_1 (udt_1t *ptr, udt_1t *expected, udt_1t *desired,
+ 		     unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_2 (udt_2t *ptr, udt_2t *expected, udt_2t *desired,
+ 		     unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_4 (udt_4t *ptr, udt_4t *expected, udt_4t *desired,
+ 		     unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_8 (udt_8t *ptr, udt_8t *expected, udt_8t *desired,
+ 		     unsigned long long n)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr+n, expected+n, desired+n, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ 
+ /* Test if indexed mode addresses are used, r6 must be used which corresponds
+    to the argument n in all functions.  */
+ 
+ /* { dg-final { scan-assembler-times {\mlbarx +[0-9]+,[0-9]+,6,1} 3 } } */
+ /* { dg-final { scan-assembler-times {\mstbcx. +[0-9]+,[0-9]+,6} 3 } } */
+ 
+ /* { dg-final { scan-assembler-times {\mlharx +[0-9]+,[0-9]+,6,1} 4 } } */
+ /* { dg-final { scan-assembler-times {\msthcx. +[0-9]+,[0-9]+,6} 4 } } */
+ 
+ /* { dg-final { scan-assembler-times {\mlwarx +[0-9]+,[0-9]+,6,1} 5 } } */
+ /* { dg-final { scan-assembler-times {\mstwcx. +[0-9]+,[0-9]+,6} 5 } } */
+ 
+ /* { dg-final { scan-assembler-times {\mldarx +[0-9]+,[0-9]+,6,1} 6 } } */
+ /* { dg-final { scan-assembler-times {\mstdcx. +[0-9]+,[0-9]+,6} 6 } } */
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/powerpc/acmp-tst.c gcc-16-20260704/gcc/testsuite/gcc.target/powerpc/acmp-tst.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/powerpc/acmp-tst.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/powerpc/acmp-tst.c	Sat Jul  4 22:32:15 2026
***************
*** 0 ****
--- 1,176 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target lp64 } */
+ 
+ // Need power8 for l<b,h,q>arx
+ /* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+ 
+ typedef struct udt_1
+ {
+   char *a;
+ } udt_1t;
+ typedef struct udt_2
+ {
+   char a;
+   char b;
+ } udt_2t;
+ typedef struct udt_4
+ {
+   short a;
+   short b;
+ } udt_4t;
+ typedef struct udt_8
+ {
+   int a;
+   int b;
+ } udt_8t;
+ typedef struct udt_16
+ {
+   long long a;
+   long long b;
+ } udt_16t;
+ bool
+ word_exchange_nqi (char *ptr, char *expected, char *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_qi (signed char *ptr, signed char *expected, signed char *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_uqi (unsigned char *ptr, unsigned char *expected,
+                    unsigned char *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_hi (short *ptr, short *expected, short *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_shi (signed short *ptr, signed short *expected,
+                    signed short *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_uhi (unsigned short *ptr, unsigned short *expected,
+                    unsigned short *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_si (int *ptr, int *expected, int *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_ssi (signed int *ptr, signed int *expected, signed int *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_usi (unsigned int *ptr, unsigned int *expected,
+                    unsigned int *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_di (long long *ptr, long long *expected, long long *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_sdi (signed long long *ptr, signed long long *expected,
+                    signed long long *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udi (unsigned long long *ptr, unsigned long long *expected,
+                    unsigned long long *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_sti (signed __int128 *ptr, signed __int128 *expected,
+                    signed __int128 *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_uti (unsigned __int128 *ptr, unsigned __int128 *expected,
+                    unsigned __int128 *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_f32 (float *ptr, float *expected, float *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_f64 (double *ptr, double *expected, double *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_f128 (__ieee128 *ptr, __ieee128 *expected, __ieee128 *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_1 (udt_1t *ptr, udt_1t *expected, udt_1t *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_2 (udt_2t *ptr, udt_2t *expected, udt_2t *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_4 (udt_4t *ptr, udt_4t *expected, udt_4t *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_8 (udt_8t *ptr, udt_8t *expected, udt_8t *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ bool
+ word_exchange_udt_16 (udt_16t *ptr, udt_16t *expected, udt_16t *desired)
+ {
+   return __builtin_ppc_atomic_cas_local (ptr, expected, desired, 0,
+ 					 __ATOMIC_SEQ_CST, __ATOMIC_ACQUIRE);
+ }
+ 
+ /* { dg-final { scan-assembler-times {\mlbarx +[0-9]+,[0-9]+,[0-9]+,1} 3 } } */
+ /* { dg-final { scan-assembler-times {\mlharx +[0-9]+,[0-9]+,[0-9]+,1} 4 } } */
+ /* { dg-final { scan-assembler-times {\mlwarx +[0-9]+,[0-9]+,[0-9]+,1} 5 } } */
+ /* { dg-final { scan-assembler-times {\mldarx +[0-9]+,[0-9]+,[0-9]+,1} 6 } } */
+ /* { dg-final { scan-assembler-times {\mlqarx +[0-9]+,[0-9]+,[0-9]+,1} 4 } } */
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/powerpc/aes-builtin-1.c gcc-16-20260704/gcc/testsuite/gcc.target/powerpc/aes-builtin-1.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/powerpc/aes-builtin-1.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/powerpc/aes-builtin-1.c	Sat Jul  4 22:32:15 2026
***************
*** 0 ****
--- 1,155 ----
+ /* { dg-do compile } */
+ /* { dg-options "-mdejagnu-cpu=future -O2" } */
+ 
+ void
+ aes_enc_pair_0 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes_encrypt_paired (t, k, 0);
+   *res = c;
+ }
+ void
+ aes_enc_pair_1 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes_encrypt_paired (t, k, 1);
+   *res = c;
+ }
+ void
+ aes_enc_pair_2 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes_encrypt_paired (t, k, 2);
+   *res = c;
+ }
+ void
+ aes_enc_pair_128 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes128_encrypt_paired (t, k);
+   *res = c;
+ }
+ void
+ aes_enc_pair_192 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes192_encrypt_paired (t, k);
+   *res = c;
+ }
+ void
+ aes_enc_pair_256 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes256_encrypt_paired (t, k);
+   *res = c;
+ }
+ void
+ aes_dec_pair_0 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes_decrypt_paired (t, k, 0);
+   *res = c;
+ }
+ void
+ aes_dec_pair_1 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes_decrypt_paired (t, k, 1);
+   *res = c;
+ }
+ void
+ aes_dec_pair_2 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes_decrypt_paired (t, k, 2);
+   *res = c;
+ }
+ void
+ aes_dec_pair_128 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes128_decrypt_paired (t, k);
+   *res = c;
+ }
+ void
+ aes_dec_pair_192 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes192_decrypt_paired (t, k);
+   *res = c;
+ }
+ void
+ aes_dec_pair_256 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes256_decrypt_paired (t, k);
+   *res = c;
+ }
+ void
+ aes_genlastkey_paired_0 (__vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes_genlastkey_paired (k, 0);
+   *res = c;
+ }
+ void
+ aes_genlastkey_paired_1 (__vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes_genlastkey_paired (k, 1);
+   *res = c;
+ }
+ void
+ aes_genlastkey_paired_2 (__vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes_genlastkey_paired (k, 2);
+   *res = c;
+ }
+ void
+ aes_genlastkey_paired_128 (__vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes128_genlastkey_paired (k);
+   *res = c;
+ }
+ void
+ aes_genlastkey_paired_192 (__vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes192_genlastkey_paired (k);
+   *res = c;
+ }
+ void
+ aes_genlastkey_paired_256 (__vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair k = *key;
+   __vector_pair c = __builtin_aes256_genlastkey_paired (k);
+   *res = c;
+ }
+ 
+ 
+ /* { dg-final { scan-assembler-times {\mxxaesencp\M} 3 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes128encp\M} 1 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes192encp\M} 1 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes256encp\M} 1 } } */
+ /* { dg-final { scan-assembler-times {\mxxaesdecp\M} 3 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes128decp\M} 1 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes192decp\M} 1 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes256decp\M} 1 } } */
+ /* { dg-final { scan-assembler-times {\mxxaesgenlkp\M} 3 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes128genlkp\M} 1 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes192genlkp\M} 1 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes256genlkp\M} 1 } } */
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/powerpc/aes-builtin-2.c gcc-16-20260704/gcc/testsuite/gcc.target/powerpc/aes-builtin-2.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/powerpc/aes-builtin-2.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/powerpc/aes-builtin-2.c	Sat Jul  4 22:32:15 2026
***************
*** 0 ****
--- 1,34 ----
+ /* { dg-do compile } */
+ /* { dg-options "-mdejagnu-cpu=future -O2" } */
+ 
+ typedef unsigned char vec_t __attribute__((vector_size(16)));
+ 
+ void
+ gfmul (vec_t *a, vec_t *b, vec_t *res)
+ {
+   vec_t A = *a;
+   vec_t B = *b;
+   vec_t R = __builtin_galois_field_mult (A, B, 0);
+   R = __builtin_galois_field_mult (R, B, 1);
+   *res = R;
+ }
+ void
+ gfmul_gcm (vec_t *a, vec_t *b, vec_t *res)
+ {
+   vec_t A = *a;
+   vec_t B = *b;
+   vec_t R = __builtin_galois_field_mult_gcm (A, B);
+   *res = R;
+ }
+ void
+ gfmul_xts (vec_t *a, vec_t *b, vec_t *res)
+ {
+   vec_t A = *a;
+   vec_t B = *b;
+   vec_t R = __builtin_galois_field_mult_xts (A, B);
+   *res = R;
+ }
+ 
+ /* { dg-final { scan-assembler-times {\mxxgfmul128\M} 2 } } */
+ /* { dg-final { scan-assembler-times {\mxxgfmul128gcm\M} 1 } } */
+ /* { dg-final { scan-assembler-times {\mxxgfmul128xts\M} 1 } } */
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/powerpc/aes-builtin-3.c gcc-16-20260704/gcc/testsuite/gcc.target/powerpc/aes-builtin-3.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/powerpc/aes-builtin-3.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/powerpc/aes-builtin-3.c	Sat Jul  4 22:32:15 2026
***************
*** 0 ****
--- 1,52 ----
+ /* { dg-do compile } */
+ /* { dg-options "-mdejagnu-cpu=future -O2" } */
+ 
+ void
+ aes_dec_pair (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair lk = __builtin_aes_genlastkey_paired (k, 0);
+   __vector_pair c = __builtin_aes_decrypt_paired (t, lk, 0);
+   lk = __builtin_aes_genlastkey_paired (k, 1);
+   c = __builtin_aes_decrypt_paired (c, lk, 1);
+   lk = __builtin_aes_genlastkey_paired (k, 2);
+   c = __builtin_aes_decrypt_paired (c, lk, 2);
+   *res = c;
+ }
+ void
+ aes_dec_pair_128 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair lk = __builtin_aes128_genlastkey_paired (k);
+   __vector_pair c = __builtin_aes128_decrypt_paired (t, lk);
+   *res = c;
+ }
+ void
+ aes_dec_pair_192 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair lk = __builtin_aes192_genlastkey_paired (k);
+   __vector_pair c = __builtin_aes192_decrypt_paired (t, lk);
+   *res = c;
+ }
+ void
+ aes_dec_pair_256 (__vector_pair *text, __vector_pair *key, __vector_pair *res)
+ {
+   __vector_pair t = *text;
+   __vector_pair k = *key;
+   __vector_pair lk = __builtin_aes256_genlastkey_paired (k);
+   __vector_pair c = __builtin_aes256_decrypt_paired (t, lk);
+   *res = c;
+ }
+ 
+ /* { dg-final { scan-assembler-times {\mxxaesdecp\M} 3 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes128decp\M} 1 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes192decp\M} 1 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes256decp\M} 1 } } */
+ /* { dg-final { scan-assembler-times {\mxxaesgenlkp\M} 3 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes128genlkp\M} 1 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes192genlkp\M} 1 } } */
+ /* { dg-final { scan-assembler-times {\mxxaes256genlkp\M} 1 } } */
\ No newline at end of file
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gcc.target/s390/pr125972.c gcc-16-20260704/gcc/testsuite/gcc.target/s390/pr125972.c
*** gcc-16-20260627/gcc/testsuite/gcc.target/s390/pr125972.c	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gcc.target/s390/pr125972.c	Sat Jul  4 22:32:16 2026
***************
*** 0 ****
--- 1,20 ----
+ /* { dg-do compile { target int128 } } */
+ /* { dg-options "-march=z16 -O3" } */
+ 
+ int a, b, c;
+ long d, e;
+ int *f;
+ __int128 g;
+ void h() {
+   g = 0;
+   for (; g <= 33; ++g) {
+     int *i = &c;
+     *i = d - a;
+     if (*i) {
+       c = 0;
+       for (; c <= 8; ++c)
+         f = &b;
+     } else
+       ++e;
+   }
+ }
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gfortran.dg/coarray/pr125051.f90 gcc-16-20260704/gcc/testsuite/gfortran.dg/coarray/pr125051.f90
*** gcc-16-20260627/gcc/testsuite/gfortran.dg/coarray/pr125051.f90	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gfortran.dg/coarray/pr125051.f90	Sat Jul  4 22:32:16 2026
***************
*** 0 ****
--- 1,34 ----
+ !{ dg-do link }
+ 
+ ! Contributed by Paul Thomas  <pault@gcc.gnu.org>
+ ! Check PR fortran/125051 is fixed.
+ 
+ module m
+   integer, parameter :: ncells = 8, nsize = ncells+2
+   integer, parameter :: head =2, tail = ncells + 1
+   real :: second_derivative(ncells+2, ncells+2)
+   type :: density_t
+     real :: density(nsize)
+     real:: derivative(nsize)
+   end type
+   type (density_t) :: n[*]
+   real :: n_tail[*] = 0.0
+   real :: n_head[*] = 0.0
+ contains
+   subroutine sub
+     integer :: image_no
+     image_no = this_image()
+     sync all
+     if (image_no > 1) n_head = n[image_no -1]%density(tail)
+     if (image_no < num_images()) n_tail = n[image_no +1]%density(head)
+     sync all
+   end
+ end module
+ 
+ program main
+   use m
+   implicit none
+   call sub
+ contains
+ end program
+ 
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gfortran.dg/stop_function_code_1.f90 gcc-16-20260704/gcc/testsuite/gfortran.dg/stop_function_code_1.f90
*** gcc-16-20260627/gcc/testsuite/gfortran.dg/stop_function_code_1.f90	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gfortran.dg/stop_function_code_1.f90	Sat Jul  4 22:32:17 2026
***************
*** 0 ****
--- 1,14 ----
+ ! { dg-do compile }
+ ! PR fortran/126018 - Stop code may be a function call (CHARACTER or INTEGER)
+ program p
+   implicit none
+   error stop character_stop ()   ! was: "must be either INTEGER or CHARACTER"
+   stop integer_stop ()           ! likewise for integer
+ contains
+   character (1) function character_stop ()
+     character_stop = "a"
+   end function character_stop
+   integer function integer_stop ()
+     integer_stop = 1
+   end function integer_stop
+ end program p
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gnat.dg/opt109.adb gcc-16-20260704/gcc/testsuite/gnat.dg/opt109.adb
*** gcc-16-20260627/gcc/testsuite/gnat.dg/opt109.adb	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gnat.dg/opt109.adb	Sat Jul  4 22:32:17 2026
***************
*** 0 ****
--- 1,13 ----
+ -- { dg-do run }
+ -- { dg-options "-O" }
+ 
+ with Opt109_Pkg; use Opt109_Pkg;
+ 
+ procedure Opt109 is
+   S : constant String := "Hello World!";
+   R : constant Rec := F (S);
+ begin
+   if R.B.Data.all /= S then
+     raise Program_Error;
+   end if;
+ end;
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gnat.dg/opt109_pkg.adb gcc-16-20260704/gcc/testsuite/gnat.dg/opt109_pkg.adb
*** gcc-16-20260627/gcc/testsuite/gnat.dg/opt109_pkg.adb	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gnat.dg/opt109_pkg.adb	Sat Jul  4 22:32:17 2026
***************
*** 0 ****
--- 1,16 ----
+ package body Opt109_Pkg is
+ 
+    function F (Value : String) return Rec is
+    begin
+       if Value'Length > Max then
+          return Result : Rec (Is_Small => False) do
+             Result.B.Data := new String'(Value);
+          end return;
+       else
+          return Result : Rec (Is_Small => True) do
+             Result.S.Data (Value'Length + 1 .. Max) := (others => ' ');
+          end return;
+       end if;
+    end;
+ 
+ end Opt109_Pkg;
diff -Nrcpad gcc-16-20260627/gcc/testsuite/gnat.dg/opt109_pkg.ads gcc-16-20260704/gcc/testsuite/gnat.dg/opt109_pkg.ads
*** gcc-16-20260627/gcc/testsuite/gnat.dg/opt109_pkg.ads	Thu Jan  1 00:00:00 1970
--- gcc-16-20260704/gcc/testsuite/gnat.dg/opt109_pkg.ads	Sat Jul  4 22:32:17 2026
***************
*** 0 ****
--- 1,33 ----
+ with System;
+ 
+ package Opt109_Pkg is
+ 
+    Max : constant Natural := 7;
+    subtype Small_String_Size is Natural range 0 .. Max;
+ 
+    type Small_String is record
+       Is_Small : Boolean;
+       Length   : Small_String_Size;
+       Data     : aliased String (1 .. Max);
+    end record;
+ 
+    type Big_String_Access is access all String;
+ 
+    type Big_String is record
+       Data : Big_String_Access := null;
+    end record;
+ 
+    for Big_String use record
+       Data at 0 range 0 .. System.Word_Size - 1;
+    end record;
+ 
+    type Rec (Is_Small : Boolean := True) is record
+       case Is_Small is
+          when True  => S : Small_String;
+          when False => B : Big_String;
+       end case;
+    end record with Unchecked_Union;
+ 
+    function F (Value : String) return Rec;
+ 
+ end Opt109_Pkg;
diff -Nrcpad gcc-16-20260627/gcc/tree-ssa-structalias.cc gcc-16-20260704/gcc/tree-ssa-structalias.cc
*** gcc-16-20260627/gcc/tree-ssa-structalias.cc	Sat Jun 27 22:32:16 2026
--- gcc-16-20260704/gcc/tree-ssa-structalias.cc	Sat Jul  4 22:32:17 2026
*************** static void
*** 745,756 ****
  set_uids_in_ptset (bitmap into, bitmap from, struct pt_solution *pt,
  		   tree fndecl)
  {
    unsigned int i;
    bitmap_iterator bi;
-   varinfo_t escaped_vi = get_varinfo (var_rep[escaped_id]);
-   varinfo_t escaped_return_vi = get_varinfo (var_rep[escaped_return_id]);
-   bool everything_escaped
-     = escaped_vi->solution && bitmap_bit_p (escaped_vi->solution, anything_id);
  
    EXECUTE_IF_SET_IN_BITMAP (from, 0, i, bi)
      {
--- 745,759 ----
  set_uids_in_ptset (bitmap into, bitmap from, struct pt_solution *pt,
  		   tree fndecl)
  {
+   const varinfo_t escaped_vi = get_varinfo (var_rep[escaped_id]);
+   const varinfo_t escaped_return_vi = get_varinfo (var_rep[escaped_return_id]);
+   const bool everything_escaped
+     = escaped_vi->solution && bitmap_bit_p (escaped_vi->solution, anything_id);
+   const bool everything_escaped_return
+     = escaped_return_vi->solution
+       && bitmap_bit_p (escaped_return_vi->solution, anything_id);
    unsigned int i;
    bitmap_iterator bi;
  
    EXECUTE_IF_SET_IN_BITMAP (from, 0, i, bi)
      {
*************** set_uids_in_ptset (bitmap into, bitmap f
*** 766,773 ****
  	  pt->vars_contains_escaped = true;
  	  pt->vars_contains_escaped_heap |= vi->is_heap_var;
  	}
!       if (escaped_return_vi->solution
! 	  && bitmap_bit_p (escaped_return_vi->solution, i))
  	pt->vars_contains_escaped_heap |= vi->is_heap_var;
  
        if (vi->is_restrict_var)
--- 769,778 ----
  	  pt->vars_contains_escaped = true;
  	  pt->vars_contains_escaped_heap |= vi->is_heap_var;
  	}
! 
!       if (everything_escaped_return
! 	  || (escaped_return_vi->solution
! 	      && bitmap_bit_p (escaped_return_vi->solution, i)))
  	pt->vars_contains_escaped_heap |= vi->is_heap_var;
  
        if (vi->is_restrict_var)
diff -Nrcpad gcc-16-20260627/libgcc/config/avr/libf7/ChangeLog gcc-16-20260704/libgcc/config/avr/libf7/ChangeLog
*** gcc-16-20260627/libgcc/config/avr/libf7/ChangeLog	Sat Jun 27 22:32:16 2026
--- gcc-16-20260704/libgcc/config/avr/libf7/ChangeLog	Sat Jul  4 22:32:18 2026
***************
*** 1,3 ****
--- 1,21 ----
+ 2026-06-28  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2026-06-28  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/125752
+ 	* libf7.c (d_to_ufx, d_to_sfx): Remove prototypes.
+ 	(__fractdfda, __fractdfuda, __fractdfta, __fractdfuta)
+ 	(__fractdfdq, __fractdfudq): Move implementation to...
+ 	* libf7-asm.sx: ...here.
+ 	(d_to_fx64): Remove.
+ 	* libf7-common.mk (F7_ASM_PARTS): Add D2dq, D2udq, D2da,
+ 	D2uda, D2ta, D2uta.
+ 	(F7F_asm): Remove d_to_fx64.
+ 	* t-libf7 (LIBF7_DF_CONV): Remove fractdfda, fractdfta,
+ 	fractdfdq, fractdfuda, fractdfuta, fractdfudq.
+ 	* f7-renames.h: Rebuild.
+ 
  2026-06-11  Georg-Johann Lay  <avr@gjlay.de>
  
  	Backported from master:
diff -Nrcpad gcc-16-20260627/libgcc/config/avr/libf7/f7-renames.h gcc-16-20260704/libgcc/config/avr/libf7/f7-renames.h
*** gcc-16-20260627/libgcc/config/avr/libf7/f7-renames.h	Sat Jun 27 22:32:16 2026
--- gcc-16-20260704/libgcc/config/avr/libf7/f7-renames.h	Sat Jul  4 22:32:18 2026
***************
*** 222,228 ****
  #define f7_sqrt16_floor_asm __f7_sqrt16_floor_asm
  #define f7_lshrdi3_asm __f7_lshrdi3_asm
  #define f7_ashldi3_asm __f7_ashldi3_asm
- #define f7_d_to_fx64_asm __f7_d_to_fx64_asm
  #define f7_ufx64_to_d_asm __f7_ufx64_to_d_asm
  #define f7_sfx64_to_d_asm __f7_sfx64_to_d_asm
  #define f7_class_D_asm __f7_class_D_asm
--- 222,227 ----
diff -Nrcpad gcc-16-20260627/libgcc/config/avr/libf7/libf7-asm.sx gcc-16-20260704/libgcc/config/avr/libf7/libf7-asm.sx
*** gcc-16-20260627/libgcc/config/avr/libf7/libf7-asm.sx	Sat Jun 27 22:32:16 2026
--- gcc-16-20260704/libgcc/config/avr/libf7/libf7-asm.sx	Sat Jul  4 22:32:18 2026
*************** _DEFUN __fractdfusa
*** 2465,2512 ****
  _ENDF __fractdfusa
  #endif /* F7MOD_D2usa_ */
  
  
! #ifdef F7MOD_D2fx_
! ;;; Convert double R18 to a 64-bit fixed point value.
! ;;; R18 d_to_fx64 (double R18, int8_t fbit R16);
! ;;; |FBIT| accounts for the extra fbits compared to [u]int64_t.
! ;;; FBIT < 0 indicates a signed conversion.
! ;;; FBIT > 0 indicates an unsigned conversion.
! DEFUN d_to_fx64
!     do_prologue_saves  4, F7_SIZEOF
! 
!     ;; Y = FramePointer + 1
!     adiw    Y,      1
! 
!     ;; FP + 1 = (f7_t) arg
!     wmov    r16,    Y
! 
!     ;; Convert double R18 to f7_t *R16.
!     XCALL   F7_NAME (set_double_impl)
  
!     ;; Prepare for *R24 = ldexp (*R24, R22).  ldexp() accounts for the
!     ;; fractional bits of the fixed point value, i.e. we have to <<= FBIT.
!     wmov    r24,    r16
!     ;; Zero-extend FBIT.
!     clr     r23
!     ;; R16 has been clobbered.  Fetch it from where prologue_saves put it.
!     ldd     r22,    Y + F7_SIZEOF + 3       ; Saved R16
!     tst     r22
!     brmi 1f
  
!     ;; Positive FBIT indicates an unsigned conversion.
!     XCALL   F7_NAME (Ildexp)
!     XCALL   F7_NAME (get_u64)
!     rjmp 9f
  
! 1:  ;; Negative FBIT indicates a signed conversion.
!     neg     r22                 ; FBIT := |FBIT|
!     XCALL   F7_NAME (Ildexp)
!     XCALL   F7_NAME (get_s64)
  
! 9:  do_epilogue_restores  4, F7_SIZEOF
! ENDF d_to_fx64
! #endif /* F7MOD_D2fx_ */
  
  
  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
--- 2465,2520 ----
  _ENDF __fractdfusa
  #endif /* F7MOD_D2usa_ */
  
+ #ifdef F7MOD_D2da_
+ _DEFUN __fractdfda
+     ;; Multiply with 2^FBIT to get a DA result in r25:r18.
+     subi    r24, dex_lo (-__DA_FBIT__)
+     sbci    r25, dex_hi (-__DA_FBIT__)
+     XJMP    __fixdfdi
+ _ENDF __fractdfda
+ #endif /* F7MOD_D2da_ */
  
! #ifdef F7MOD_D2uda_
! _DEFUN __fractdfuda
!     ;; Multiply with 2^FBIT to get an UDA result in r25:r18.
!     subi    r25, dex_hi (-__UDA_FBIT__)
!     XJMP    __fixunsdfdi
! _ENDF __fractdfuda
! #endif /* F7MOD_D2uda_ */
  
! #ifdef F7MOD_D2ta_
! _DEFUN __fractdfta
!     ;; Multiply with 2^FBIT to get a TA result in r25:r18.
!     subi    r24, dex_lo (-__TA_FBIT__)
!     sbci    r25, dex_hi (-__TA_FBIT__)
!     XJMP    __fixdfdi
! _ENDF __fractdfta
! #endif /* F7MOD_D2ta_ */
  
! #ifdef F7MOD_D2uta_
! _DEFUN __fractdfuta
!     ;; Multiply with 2^FBIT to get an UTA result in r25:r18.
!     subi    r25, dex_hi (-__UTA_FBIT__)
!     XJMP    __fixunsdfdi
! _ENDF __fractdfuta
! #endif /* F7MOD_D2uta_ */
  
! #ifdef F7MOD_D2dq_
! _DEFUN __fractdfdq
!     ;; Multiply with 2^FBIT to get a DQ result in r25:r18.
!     subi    r24, dex_lo (-__DQ_FBIT__)
!     sbci    r25, dex_hi (-__DQ_FBIT__)
!     XJMP    __fixdfdi
! _ENDF __fractdfdq
! #endif /* F7MOD_D2dq_ */
  
! #ifdef F7MOD_D2udq_
! _DEFUN __fractdfudq
!     ;; Multiply with 2^FBIT to get an UDQ result in r25:r18.
!     subi    r25, dex_hi (-__UDQ_FBIT__)
!     XJMP    __fixunsdfdi
! _ENDF __fractdfudq
! #endif /* F7MOD_D2udq_ */
  
  
  ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff -Nrcpad gcc-16-20260627/libgcc/config/avr/libf7/libf7-common.mk gcc-16-20260704/libgcc/config/avr/libf7/libf7-common.mk
*** gcc-16-20260627/libgcc/config/avr/libf7/libf7-common.mk	Sat Jun 27 22:32:16 2026
--- gcc-16-20260704/libgcc/config/avr/libf7/libf7-common.mk	Sat Jul  4 22:32:18 2026
*************** F7_ASM_PARTS +=            ha2D uha2D sa
*** 34,42 ****
  F7_ASM_PARTS += fx2D
  
  # Double -> fixed-point conversions
! F7_ASM_PARTS += D2qq D2uqq D2hq D2uhq
! F7_ASM_PARTS +=            D2ha D2uha D2sa D2usa
! F7_ASM_PARTS += D2fx
  
  # Integer -> double conversions
  F7_ASM_PARTS += D_floatsidf D_floatunsidf
--- 34,41 ----
  F7_ASM_PARTS += fx2D
  
  # Double -> fixed-point conversions
! F7_ASM_PARTS += D2qq D2uqq D2hq D2uhq            D2dq D2udq
! F7_ASM_PARTS +=            D2ha D2uha D2sa D2usa D2da D2uda D2ta D2uta
  
  # Integer -> double conversions
  F7_ASM_PARTS += D_floatsidf D_floatunsidf
*************** F7F_asm += set_u64 set_s64 addsub_mant_s
*** 109,115 ****
  F7F_asm += to_integer to_unsigned clr_mant_lsbs
  F7F_asm += div sqrt_approx sqrt16_round sqrt16_floor
  F7F_asm += lshrdi3 ashldi3
! F7F_asm += d_to_fx64 ufx64_to_d sfx64_to_d
  F7F_asm += class_D
  
  F7F_asm += call_ddd call_xdd call_ddx
--- 108,114 ----
  F7F_asm += to_integer to_unsigned clr_mant_lsbs
  F7F_asm += div sqrt_approx sqrt16_round sqrt16_floor
  F7F_asm += lshrdi3 ashldi3
! F7F_asm += ufx64_to_d sfx64_to_d
  F7F_asm += class_D
  
  F7F_asm += call_ddd call_xdd call_ddx
diff -Nrcpad gcc-16-20260627/libgcc/config/avr/libf7/libf7.c gcc-16-20260704/libgcc/config/avr/libf7/libf7.c
*** gcc-16-20260627/libgcc/config/avr/libf7/libf7.c	Sat Jun 27 22:32:16 2026
--- gcc-16-20260704/libgcc/config/avr/libf7/libf7.c	Sat Jul  4 22:32:18 2026
*************** f7_double_t __floatdidf (int64_t x)
*** 140,197 ****
  #endif // F7MOD_floatdidf_
  
  
- extern uint64_t d_to_ufx (f7_double_t, int8_t) F7ASM(f7_d_to_fx64_asm);
- extern int64_t  d_to_sfx (f7_double_t, int8_t) F7ASM(f7_d_to_fx64_asm);
- 
- #ifdef F7MOD_fractdfda_
- F7_WEAK
- int64_t __fractdfda (f7_double_t d)
- {
-   return d_to_sfx (d, -__DA_FBIT__);
- }
- #endif // F7MOD_fractdfda_
- 
- #ifdef F7MOD_fractdfuda_
- F7_WEAK
- uint64_t __fractdfuda (f7_double_t d)
- {
-   return d_to_ufx (d, __UDA_FBIT__);
- }
- #endif // F7MOD_fractdfuda_
- 
- #ifdef F7MOD_fractdfta_
- F7_WEAK
- int64_t __fractdfta (f7_double_t d)
- {
-   return d_to_sfx (d, -__TA_FBIT__);
- }
- #endif // F7MOD_fractdfta_
- 
- #ifdef F7MOD_fractdfuta_
- F7_WEAK
- uint64_t __fractdfuta (f7_double_t d)
- {
-   return d_to_ufx (d, __UTA_FBIT__);
- }
- #endif // F7MOD_fractdfuta_
- 
- #ifdef F7MOD_fractdfdq_
- F7_WEAK
- int64_t __fractdfdq (f7_double_t d)
- {
-   return d_to_sfx (d, -__DQ_FBIT__);
- }
- #endif // F7MOD_fractdfdq_
- 
- #ifdef F7MOD_fractdfudq_
- F7_WEAK
- uint64_t __fractdfudq (f7_double_t d)
- {
-   return d_to_ufx (d, __UDQ_FBIT__);
- }
- #endif // F7MOD_fractdfudq_
- 
- 
  #ifdef F7MOD_init_
  f7_t* f7_init_impl (uint64_t mant, uint8_t flags, f7_t *cc, int16_t expo)
  {
--- 140,145 ----
diff -Nrcpad gcc-16-20260627/libgcc/config/avr/libf7/t-libf7 gcc-16-20260704/libgcc/config/avr/libf7/t-libf7
*** gcc-16-20260627/libgcc/config/avr/libf7/t-libf7	Sat Jun 27 22:32:16 2026
--- gcc-16-20260704/libgcc/config/avr/libf7/t-libf7	Sat Jul  4 22:32:18 2026
*************** F7_PREFIX = __f7_
*** 9,16 ****
  include $(libf7)/libf7-common.mk
  
  LIBF7_DF_CONV +=  floatundidf floatdidf # floatunsidf floatsidf
- LIBF7_DF_CONV +=  fractdfda fractdfta fractdfdq
- LIBF7_DF_CONV +=  fractdfuda fractdfuta fractdfudq
  
  # Wrappers like f7_lt_impl for f7_lt etc. because the latter is inline.
  LIBF7_DF_CMP  += lt le gt ge ne eq unord
--- 9,14 ----
diff -Nrcpad gcc-16-20260627/libgcc/config/t-darwin-ehs gcc-16-20260704/libgcc/config/t-darwin-ehs
*** gcc-16-20260627/libgcc/config/t-darwin-ehs	Sat Jun 27 22:32:17 2026
--- gcc-16-20260704/libgcc/config/t-darwin-ehs	Sat Jul  4 22:32:18 2026
***************
*** 3,7 ****
  
  LIBEHSOBJS = unwind-dw2_s.o unwind-dw2-fde-darwin_s.o unwind-c_s.o
  
! unwind-dw2_s.o: gthr-default.h md-unwind-support.h unwind.h
  $(LIBEHSOBJS): libgcc_tm.h
--- 3,7 ----
  
  LIBEHSOBJS = unwind-dw2_s.o unwind-dw2-fde-darwin_s.o unwind-c_s.o
  
! unwind-dw2_s.o: gthr-default.h md-unwind-support.h md-unwind-def.h unwind.h
  $(LIBEHSOBJS): libgcc_tm.h
diff -Nrcpad gcc-16-20260627/libstdc++-v3/ChangeLog gcc-16-20260704/libstdc++-v3/ChangeLog
*** gcc-16-20260627/libstdc++-v3/ChangeLog	Sat Jun 27 22:32:18 2026
--- gcc-16-20260704/libstdc++-v3/ChangeLog	Sat Jul  4 22:32:20 2026
***************
*** 1,3 ****
--- 1,83 ----
+ 2026-07-01  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	Backported from master:
+ 	2026-07-01  Matthias Kretz  <m.kretz@gsi.de>
+ 
+ 	* include/bits/simd_details.h (_ScalarAbi): Remove.
+ 	(__scalar_abi_tag): Identify _Abi<N, N> as scalar now.
+ 	(__native_abi): Replace _ScalarAbi<1> with _Abi_t<1, 1, ...>.
+ 	(__abi_rebind): Refactor rebinding from/to __scalar_abi_tag.
+ 	* include/bits/simd_mask.h (_S_use_bitmask): Only true if
+ 	!_S_is_scalar.
+ 	(_M_and_neighbors, _M_or_neighbors): Add case for _S_is_scalar
+ 	where the and/or must be executed one step earlier.
+ 	(_M_reduce_min_index, _M_reduce_max_index): Delete dead code.
+ 	* include/bits/simd_vec.h (_S_use_bitmask): Inherit the value
+ 	from the first data member.
+ 	* testsuite/std/simd/traits_impl.cc: Adjust for the removal of
+ 	_ScalarAbi.
+ 
+ 2026-07-01  Yi Chen  <chencyy@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-07-01  Yi Chen  <chencyy@hygon.cn>
+ 
+ 	* src/c++11/random.cc (random_device::_M_init): Add signature_HYGON_ebx to
+ 	the RDSEED and RDRAND CPUID vendor allowlists.  For the default device on
+ 	Hygon, prefer RDRAND via a dedicated check at the top of the function.
+ 
+ 2026-07-01  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-29  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	* include/bits/chrono_io.h: Fix comment typo.
+ 
+ 2026-07-01  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-25  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	PR libstdc++/125956
+ 	* src/c++20/format.cc [_GLIBCXX_HAVE_ICONV] (iconv_input): New
+ 	concept.
+ 	(__encoding::conv) [_GLIBCXX_HAVE_ICONV]: Use iconv_input to
+ 	decide which type to cast the input pointer to.
+ 
+ 2026-07-01  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-24  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	* testsuite/27_io/filesystem/operations/copy_symlink/1.cc: Add
+ 	dg-require-target-fs-symlinks.
+ 	* testsuite/27_io/filesystem/operations/copy_symlink/2.cc:
+ 	Likewise.
+ 	* testsuite/27_io/filesystem/operations/copy_symlink/3.cc:
+ 	Likewise.
+ 	* testsuite/27_io/filesystem/operations/copy_symlink/4.cc:
+ 	Likewise.
+ 
+ 2026-07-01  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-06-24  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	PR libstdc++/118158
+ 	* testsuite/27_io/filesystem/operations/pr118158.cc: Add
+ 	dg-require-mkfifo.
+ 
+ 2026-07-01  Dragon Archer  <dragon-archer@outlook.com>
+ 
+ 	Backported from master:
+ 	2026-05-16  Dragon Archer  <dragon-archer@outlook.com>
+ 
+ 	PR libstdc++/125228
+ 	* src/c++11/debug.cc: Replace assert with __glibcxx_assert,
+ 	and remove the include of <cassert>.
+ 	* src/c++17/floating_to_chars.cc: Likewise, but redefine
+ 	assert as __glibcxx_assert.
+ 
  2026-06-25  Jakub Jelinek  <jakub@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-16-20260627/libstdc++-v3/include/bits/chrono_io.h gcc-16-20260704/libstdc++-v3/include/bits/chrono_io.h
*** gcc-16-20260627/libstdc++-v3/include/bits/chrono_io.h	Sat Jun 27 22:32:18 2026
--- gcc-16-20260704/libstdc++-v3/include/bits/chrono_io.h	Sat Jul  4 22:32:20 2026
*************** namespace __format
*** 3358,3364 ****
  		__cd._M_zone_abbrev = *__zt._M_abbrev;
  	      else
  		{
! 		  // TODO: use resize_for_override
  		  __zone_store.resize(__zt._M_abbrev->size());
  		  auto& __ct = use_facet<ctype<_CharT>>(_M_f._M_locale(__fc));
  		  __ct.widen(__zt._M_abbrev->data(),
--- 3358,3364 ----
  		__cd._M_zone_abbrev = *__zt._M_abbrev;
  	      else
  		{
! 		  // TODO: use resize_and_overwrite
  		  __zone_store.resize(__zt._M_abbrev->size());
  		  auto& __ct = use_facet<ctype<_CharT>>(_M_f._M_locale(__fc));
  		  __ct.widen(__zt._M_abbrev->data(),
diff -Nrcpad gcc-16-20260627/libstdc++-v3/include/bits/simd_details.h gcc-16-20260704/libstdc++-v3/include/bits/simd_details.h
*** gcc-16-20260627/libstdc++-v3/include/bits/simd_details.h	Sat Jun 27 22:32:18 2026
--- gcc-16-20260704/libstdc++-v3/include/bits/simd_details.h	Sat Jul  4 22:32:20 2026
*************** namespace simd
*** 241,290 ****
  #endif
  
    /** @internal
!    * This ABI tag describes basic_vec objects that store one element per data member and basic_mask
!    * objects that store one bool data members.
     *
!    * @tparam _Np   The number of elements, which also matches the number of data members in
!    *               basic_vec and basic_mask.
!    */
!   template <int _Np = 1>
!     struct _ScalarAbi
!     {
!       static constexpr int _S_size = _Np;
! 
!       static constexpr int _S_nreg = _Np;
! 
!       static constexpr _AbiVariant _S_variant = {};
! 
!       template <typename _Tp>
! 	using _DataType = __canonical_vec_type_t<_Tp>;
! 
!       static constexpr bool _S_is_vecmask = false;
! 
!       // in principle a bool is a 1-bit bitmask, but this is asking for an AVX512 bitmask
!       static constexpr bool _S_is_bitmask = false;
! 
!       template <size_t>
! 	using _MaskDataType = bool;
! 
!       template <int _N2, int _Nreg2 = _N2>
! 	static consteval _ScalarAbi<_N2>
! 	_S_resize()
! 	{
! 	  static_assert(_N2 == _Nreg2);
! 	  return {};
! 	}
!     };
! 
!   /** @internal
!    * This ABI tag describes basic_vec objects that store one or more objects declared with the
!    * [[gnu::vector_size(N)]] attribute.
!    * Applied to basic_mask objects, this ABI tag either describes corresponding vector-mask objects
!    * or bit-mask objects. Which one is used is determined via @p _Var.
     *
     * @tparam _Np    The number of elements.
!    * @tparam _Nreg  The number of registers needed to store @p _Np elements.
!    * @tparam _Var   Determines how complex value-types are layed out and whether mask types use
     *                bit-masks or vector-masks.
     */
    template <int _Np, int _Nreg, underlying_type_t<_AbiVariant> _Var>
--- 241,265 ----
  #endif
  
    /** @internal
!    * @brief This ABI tag determines the data member(s) of basic_vec and basic_mask.
     *
!    * `_Nreg` determines the number of recursive basic_vec/basic_mask data members where `_Nreg` is
!    * equal to 1. With `_Nreg` equal to 1, the basic_vec/basic_mask holds one vector builtin ( `_Np`
!    * greater than 1) or a scalar (`_Np` equal to 1).
!    * @f$\lceil\frac{\mathtt{Np}}{\mathtt{Nreg}}\rceil@f$ therefore determines the number of elements
!    * in a register (except for a remainder where it can be smaller). If `_Np` equals `_Nreg`, (the
!    * aforementioned quotient is 1), then basic_vec (recursively) holds non-vector data members and
!    * basic_mask holds bools.
!    *
!    * The `_Var` parameter determines details about the data member in the one register case. Masks
!    * can be represented as vector masks (the default comparison result of GNU vector builtins),
!    * bit-masks as used by AVX-512, bit-masks as used by ARM SVE (not yet implemented), or a single
!    * bool (for the `_Np` equals 1 case). For basic_mask it determines the actual data layout and
!    * for basic_mask it determines the result of compares.
     *
     * @tparam _Np    The number of elements.
!    * @tparam _Nreg  The number of registers needed to store `_Np` elements.
!    * @tparam _Var   Determines how complex value-types are laid out and whether mask types use
     *                bit-masks or vector-masks.
     */
    template <int _Np, int _Nreg, underlying_type_t<_AbiVariant> _Var>
*************** namespace simd
*** 391,399 ****
  	    { __x.template _S_resize<_Tp::_S_size, _Tp::_S_nreg>() } -> same_as<_Tp>;
  	  };
  
    template <typename _Tp>
      concept __scalar_abi_tag
!       = same_as<_Tp, _ScalarAbi<_Tp::_S_size>> && __abi_tag<_Tp>;
  
    // Determine if math functions must *raise* floating-point exceptions.
    // math_errhandling may expand to an extern symbol, in which case we must assume fp exceptions
--- 366,378 ----
  	    { __x.template _S_resize<_Tp::_S_size, _Tp::_S_nreg>() } -> same_as<_Tp>;
  	  };
  
+   /** @internal
+    * Satisfied if `_Tp` is a valid simd ABI tag and one element is stored per register (number of
+    * registers equals size).
+    */
    template <typename _Tp>
      concept __scalar_abi_tag
!       = same_as<_Tp, _Abi_t<_Tp::_S_size, _Tp::_S_size, _Tp::_S_variant>> && __abi_tag<_Tp>;
  
    // Determine if math functions must *raise* floating-point exceptions.
    // math_errhandling may expand to an extern symbol, in which case we must assume fp exceptions
*************** namespace simd
*** 760,766 ****
        else if constexpr (_Traits._M_have_avx512f())
  	return _Abi_t<64 / __adj_sizeof, 1, _AbiVariant::_BitMask>();
        else if constexpr (is_same_v<_Tp, _Float16> && !_Traits._M_have_f16c())
! 	return _ScalarAbi<1>();
        else if constexpr (_Traits._M_have_avx2())
  	return _Abi_t<32 / __adj_sizeof, 1>();
        else if constexpr (_Traits._M_have_avx() && is_floating_point_v<_Tp>)
--- 739,745 ----
        else if constexpr (_Traits._M_have_avx512f())
  	return _Abi_t<64 / __adj_sizeof, 1, _AbiVariant::_BitMask>();
        else if constexpr (is_same_v<_Tp, _Float16> && !_Traits._M_have_f16c())
! 	return _Abi_t<1, 1>();
        else if constexpr (_Traits._M_have_avx2())
  	return _Abi_t<32 / __adj_sizeof, 1>();
        else if constexpr (_Traits._M_have_avx() && is_floating_point_v<_Tp>)
*************** namespace simd
*** 772,778 ****
  	return _Abi_t<16 / __adj_sizeof, 1>();
        // no MMX: we can't emit EMMS where it would be necessary
        else
! 	return _ScalarAbi<1>();
      }
  
  #else
--- 751,757 ----
  	return _Abi_t<16 / __adj_sizeof, 1>();
        // no MMX: we can't emit EMMS where it would be necessary
        else
! 	return _Abi_t<1, 1>();
      }
  
  #else
*************** namespace simd
*** 794,800 ****
        if constexpr (!__vectorizable<_Tp>)
  	return _InvalidAbi();
        else
! 	return _ScalarAbi<1>();
      }
  
  #endif
--- 773,779 ----
        if constexpr (!__vectorizable<_Tp>)
  	return _InvalidAbi();
        else
! 	return _Abi_t<1, 1>();
      }
  
  #endif
*************** namespace simd
*** 850,866 ****
        if constexpr (_Np <= 0 || !__vectorizable<_Tp>)
  	return _InvalidAbi();
  
-       else if constexpr (__scalar_abi_tag<_A0>)
- 	return _A0::template _S_resize<_Np>();
- 
        else
  	{
  	  using _Native = remove_const_t<decltype(std::simd::__native_abi<_Tp>())>;
  	  static_assert(0 != _Native::_S_size);
  	  constexpr int __nreg = __div_ceil(_Np, _Native::_S_size);
  
! 	  if constexpr (__scalar_abi_tag<_Native>)
! 	    return _Native::template _S_resize<_Np>();
  	  else
  	    return _Abi_t<_Native::_S_size, 1, __filter_abi_variant(_A0::_S_variant,
  								    _AbiVariant::_MaskVariants)
--- 829,847 ----
        if constexpr (_Np <= 0 || !__vectorizable<_Tp>)
  	return _InvalidAbi();
  
        else
  	{
  	  using _Native = remove_const_t<decltype(std::simd::__native_abi<_Tp>())>;
  	  static_assert(0 != _Native::_S_size);
  	  constexpr int __nreg = __div_ceil(_Np, _Native::_S_size);
  
! 	  // __scalar_abi_tag is sticky (unless we reach size 1, where we can't know whether it was
! 	  // an explicit __scalar_abi_tag before some resize_t)
! 	  if constexpr (__scalar_abi_tag<_Native> || (__scalar_abi_tag<_A0> && _A0::_S_size >= 2))
! 	    {
! 		return _A0::template _S_resize<_Np, _Np>();
! 	    }
! 
  	  else
  	    return _Abi_t<_Native::_S_size, 1, __filter_abi_variant(_A0::_S_variant,
  								    _AbiVariant::_MaskVariants)
*************** namespace simd
*** 885,893 ****
        if constexpr (_Bytes == 0 || _Np <= 0)
  	return _InvalidAbi();
  
-       else if constexpr (__scalar_abi_tag<_A0>)
- 	return _A0::template _S_resize<_Np>();
- 
  #if _GLIBCXX_X86
        // AVX w/o AVX2:
        // e.g. resize_t<8, mask<float, Whatever>> needs to be _Abi<8, 1> not _Abi<8, 2>
--- 866,871 ----
*************** namespace simd
*** 919,925 ****
     * On IvyBridge, (vec<float> == 0.f) == (rebind_t<int, vec<float>> == 0) does not compile. It does
     * compile on basically every other target, though. This is due to the difference in ABI tag:
     * _Abi<8, 1, [...]> vs. _Abi<8, 2, [...]> (8 elements, 1 vs. 2 registers).
!    * I know how to define this funtion for libstdc++ to avoid interconvertible masks. The question
     * is whether we can specify this in general for C++29.
     *
     * Idea: Is rebind_t<integer-from<...>, mask>::abi_type the same type as
--- 897,903 ----
     * On IvyBridge, (vec<float> == 0.f) == (rebind_t<int, vec<float>> == 0) does not compile. It does
     * compile on basically every other target, though. This is due to the difference in ABI tag:
     * _Abi<8, 1, [...]> vs. _Abi<8, 2, [...]> (8 elements, 1 vs. 2 registers).
!    * I know how to define this function for libstdc++ to avoid interconvertible masks. The question
     * is whether we can specify this in general for C++29.
     *
     * Idea: Is rebind_t<integer-from<...>, mask>::abi_type the same type as
*************** namespace simd
*** 939,950 ****
        if (__b0 != __b1)
  	return true;
  
-       // everything is better than _ScalarAbi, except when converting to a single bool
-       if constexpr (__scalar_abi_tag<_To>)
- 	return __n > 1;
-       else if constexpr (__scalar_abi_tag<_From>)
- 	return true;
- 
        // converting to a bit-mask is better
        else if constexpr (_To::_S_is_vecmask != _From::_S_is_vecmask)
  	return _To::_S_is_vecmask; // to vector-mask is explicit
--- 917,922 ----
diff -Nrcpad gcc-16-20260627/libstdc++-v3/include/bits/simd_mask.h gcc-16-20260704/libstdc++-v3/include/bits/simd_mask.h
*** gcc-16-20260627/libstdc++-v3/include/bits/simd_mask.h	Sat Jun 27 22:32:18 2026
--- gcc-16-20260704/libstdc++-v3/include/bits/simd_mask.h	Sat Jul  4 22:32:20 2026
*************** namespace simd
*** 543,549 ****
  
        static constexpr bool _S_is_scalar = _S_has_bool_member;
  
!       static constexpr bool _S_use_bitmask = _Ap::_S_is_bitmask;
  
        static constexpr int _S_full_size = [] {
  	if constexpr (_S_is_scalar)
--- 543,549 ----
  
        static constexpr bool _S_is_scalar = _S_has_bool_member;
  
!       static constexpr bool _S_use_bitmask = _Ap::_S_is_bitmask && !_S_is_scalar;
  
        static constexpr int _S_full_size = [] {
  	if constexpr (_S_is_scalar)
*************** namespace simd
*** 1519,1526 ****
        constexpr basic_mask&
        _M_and_neighbors()
        {
! 	_M_data0._M_and_neighbors();
! 	_M_data1._M_and_neighbors();
  	return *this;
        }
  
--- 1519,1534 ----
        constexpr basic_mask&
        _M_and_neighbors()
        {
! 	if constexpr (_S_size == 2)
! 	  {
! 	    static_assert(_S_is_scalar);
! 	    _M_data0 = _M_data1 = _M_data0 && _M_data1;
! 	  }
! 	else
! 	  {
! 	    _M_data0._M_and_neighbors();
! 	    _M_data1._M_and_neighbors();
! 	  }
  	return *this;
        }
  
*************** namespace simd
*** 1528,1535 ****
        constexpr basic_mask&
        _M_or_neighbors()
        {
! 	_M_data0._M_or_neighbors();
! 	_M_data1._M_or_neighbors();
  	return *this;
        }
  
--- 1536,1551 ----
        constexpr basic_mask&
        _M_or_neighbors()
        {
! 	if constexpr (_S_size == 2)
! 	  {
! 	    static_assert(_S_is_scalar);
! 	    _M_data0 = _M_data1 = _M_data0 || _M_data1;
! 	  }
! 	else
! 	  {
! 	    _M_data0._M_or_neighbors();
! 	    _M_data1._M_or_neighbors();
! 	  }
  	return *this;
        }
  
*************** namespace simd
*** 1650,1656 ****
  	else if constexpr (_M_data1._S_has_bool_member)
  	  // in some cases the last element can be 'bool' instead of bit-/vector-mask;
  	  // e.g. mask<short, 17> is {mask<short, 16>, mask<short, 1>}, where the latter uses
! 	  // _ScalarAbi<1>, which is stored as 'bool'
  	  return __i < _N0 ? _M_data0[__i] : _M_data1[__i - _N0];
  	else if constexpr (abi_type::_S_is_bitmask)
  	  {
--- 1666,1672 ----
  	else if constexpr (_M_data1._S_has_bool_member)
  	  // in some cases the last element can be 'bool' instead of bit-/vector-mask;
  	  // e.g. mask<short, 17> is {mask<short, 16>, mask<short, 1>}, where the latter uses
! 	  // _Abi<1, 1>, which is stored as 'bool'
  	  return __i < _N0 ? _M_data0[__i] : _M_data1[__i - _N0];
  	else if constexpr (abi_type::_S_is_bitmask)
  	  {
*************** namespace simd
*** 1929,1938 ****
  	  {
  	    const auto __bits = _M_to_uint();
  	    __glibcxx_simd_precondition(__bits, "An empty mask does not have a min_index.");
! 	    if constexpr (_S_size == 1)
! 	      return 0;
! 	    else
! 	      return __countr_zero(_M_to_uint());
  	  }
  	else if (_M_data0._M_none_of())
  	  return _M_data1._M_reduce_min_index() + _N0;
--- 1945,1951 ----
  	  {
  	    const auto __bits = _M_to_uint();
  	    __glibcxx_simd_precondition(__bits, "An empty mask does not have a min_index.");
! 	    return __countr_zero(_M_to_uint());
  	  }
  	else if (_M_data0._M_none_of())
  	  return _M_data1._M_reduce_min_index() + _N0;
*************** namespace simd
*** 1948,1957 ****
  	  {
  	    const auto __bits = _M_to_uint();
  	    __glibcxx_simd_precondition(__bits, "An empty mask does not have a max_index.");
! 	    if constexpr (_S_size == 1)
! 	      return 0;
! 	    else
! 	      return __highest_bit(_M_to_uint());
  	  }
  	else if (_M_data1._M_none_of())
  	  return _M_data0._M_reduce_max_index();
--- 1961,1967 ----
  	  {
  	    const auto __bits = _M_to_uint();
  	    __glibcxx_simd_precondition(__bits, "An empty mask does not have a max_index.");
! 	    return __highest_bit(_M_to_uint());
  	  }
  	else if (_M_data1._M_none_of())
  	  return _M_data0._M_reduce_max_index();
diff -Nrcpad gcc-16-20260627/libstdc++-v3/include/bits/simd_vec.h gcc-16-20260704/libstdc++-v3/include/bits/simd_vec.h
*** gcc-16-20260627/libstdc++-v3/include/bits/simd_vec.h	Sat Jun 27 22:32:18 2026
--- gcc-16-20260704/libstdc++-v3/include/bits/simd_vec.h	Sat Jul  4 22:32:20 2026
*************** namespace simd
*** 1776,1782 ****
  
        _DataType1 _M_data1;
  
!       static constexpr bool _S_use_bitmask = _Ap::_S_is_bitmask;
  
        static constexpr bool _S_is_partial = _DataType1::_S_is_partial;
  
--- 1776,1782 ----
  
        _DataType1 _M_data1;
  
!       static constexpr bool _S_use_bitmask = _DataType0::_S_use_bitmask;
  
        static constexpr bool _S_is_partial = _DataType1::_S_is_partial;
  
diff -Nrcpad gcc-16-20260627/libstdc++-v3/src/c++11/debug.cc gcc-16-20260704/libstdc++-v3/src/c++11/debug.cc
*** gcc-16-20260627/libstdc++-v3/src/c++11/debug.cc	Sat Jun 27 22:32:19 2026
--- gcc-16-20260704/libstdc++-v3/src/c++11/debug.cc	Sat Jul  4 22:32:20 2026
***************
*** 33,39 ****
  #include <debug/safe_local_iterator.h>
  #include <debug/vector>
  
- #include <cassert>
  #include <cstdio>	// for std::fprintf, stderr
  #include <cstdlib>	// for std::abort
  #include <cctype>	// for std::isspace.
--- 33,38 ----
*************** namespace
*** 888,894 ****
    void
    print_named_name(PrintContext& ctx, const _Parameter::_Named& named)
    {
!     assert(named._M_name);
      pretty_print(ctx, named._M_name, print_word);
    }
  
--- 887,893 ----
    void
    print_named_name(PrintContext& ctx, const _Parameter::_Named& named)
    {
!     __glibcxx_assert(named._M_name);
      pretty_print(ctx, named._M_name, print_word);
    }
  
*************** namespace
*** 985,991 ****
  	print_iterator_state(ctx, iterator);
        else if (__builtin_strcmp(fname, "sequence") == 0)
  	{
! 	  assert(iterator._M_sequence);
  	  print_address(ctx, iterator._M_sequence);
  	}
        else if (__builtin_strcmp(fname, "seq_type") == 0)
--- 984,990 ----
  	print_iterator_state(ctx, iterator);
        else if (__builtin_strcmp(fname, "sequence") == 0)
  	{
! 	  __glibcxx_assert(iterator._M_sequence);
  	  print_address(ctx, iterator._M_sequence);
  	}
        else if (__builtin_strcmp(fname, "seq_type") == 0)
*************** namespace
*** 999,1041 ****
    void
    print_field(PrintContext& ctx, const _Parameter& param, const char* fname)
    {
!     assert(param._M_kind != _Parameter::__unused_param);
  
      const auto& variant = param._M_variant;
      switch (param._M_kind)
      {
      case _Parameter::__iterator:
        if (!print_iterator_field(ctx, fname, variant._M_iterator))
! 	assert(false);
        break;
  
      case _Parameter::__sequence:
        if (!print_instance_field(ctx, fname, variant._M_sequence))
! 	assert(false);
        break;
  
      case _Parameter::__integer:
        if (!print_named_field(ctx, fname, variant._M_integer))
! 	assert(false);
        break;
  
      case _Parameter::__string:
        if (!print_named_field(ctx, fname, variant._M_string))
! 	assert(false);
        break;
  
      case _Parameter::__instance:
        if (!print_instance_field(ctx, fname, variant._M_instance))
! 	assert(false);
        break;
  
      case _Parameter::__iterator_value_type:
        if (!print_type_field(ctx, fname, variant._M_iterator_value_type))
! 	assert(false);
        break;
  
      default:
!       assert(false);
        break;
      }
    }
--- 998,1040 ----
    void
    print_field(PrintContext& ctx, const _Parameter& param, const char* fname)
    {
!     __glibcxx_assert(param._M_kind != _Parameter::__unused_param);
  
      const auto& variant = param._M_variant;
      switch (param._M_kind)
      {
      case _Parameter::__iterator:
        if (!print_iterator_field(ctx, fname, variant._M_iterator))
! 	__glibcxx_assert(false);
        break;
  
      case _Parameter::__sequence:
        if (!print_instance_field(ctx, fname, variant._M_sequence))
! 	__glibcxx_assert(false);
        break;
  
      case _Parameter::__integer:
        if (!print_named_field(ctx, fname, variant._M_integer))
! 	__glibcxx_assert(false);
        break;
  
      case _Parameter::__string:
        if (!print_named_field(ctx, fname, variant._M_string))
! 	__glibcxx_assert(false);
        break;
  
      case _Parameter::__instance:
        if (!print_instance_field(ctx, fname, variant._M_instance))
! 	__glibcxx_assert(false);
        break;
  
      case _Parameter::__iterator_value_type:
        if (!print_type_field(ctx, fname, variant._M_iterator_value_type))
! 	__glibcxx_assert(false);
        break;
  
      default:
!       __glibcxx_assert(false);
        break;
      }
    }
*************** namespace
*** 1198,1206 ****
  	  }
  
  	// Get the parameter number
! 	assert(*str >= '1' && *str <= '9');
  	size_t param_index = *str - '0' - 1;
! 	assert(param_index < num_parameters);
  	const auto& param = parameters[param_index];
  
  	// '.' separates the parameter number from the field
--- 1197,1205 ----
  	  }
  
  	// Get the parameter number
! 	__glibcxx_assert(*str >= '1' && *str <= '9');
  	size_t param_index = *str - '0' - 1;
! 	__glibcxx_assert(param_index < num_parameters);
  	const auto& param = parameters[param_index];
  
  	// '.' separates the parameter number from the field
*************** namespace
*** 1208,1214 ****
  	++str;
  	if (*str != '.')
  	  {
! 	    assert(*str == ';');
  	    ++str;
  	    if (param._M_kind == _Parameter::__integer)
  	      print_integer(ctx, param._M_variant._M_integer._M_value);
--- 1207,1213 ----
  	++str;
  	if (*str != '.')
  	  {
! 	    __glibcxx_assert(*str == ';');
  	    ++str;
  	    if (param._M_kind == _Parameter::__integer)
  	      print_integer(ctx, param._M_variant._M_integer._M_value);
*************** namespace
*** 1226,1233 ****
  	++str;
  	while (*str != ';')
  	  {
! 	    assert(*str);
! 	    assert(field_idx < max_field_len - 1);
  	    field[field_idx++] = *str++;
  	  }
  	++str;
--- 1225,1232 ----
  	++str;
  	while (*str != ';')
  	  {
! 	    __glibcxx_assert(*str);
! 	    __glibcxx_assert(field_idx < max_field_len - 1);
  	    field[field_idx++] = *str++;
  	  }
  	++str;
*************** namespace __gnu_debug
*** 1382,1388 ****
      print_literal(ctx, "Error: ");
  
      // Print the error message
!     assert(_M_text);
      print_string(ctx, _M_text, -1, _M_parameters, _M_num_parameters);
      print_literal(ctx, ".\n");
  
--- 1381,1387 ----
      print_literal(ctx, "Error: ");
  
      // Print the error message
!     __glibcxx_assert(_M_text);
      print_string(ctx, _M_text, -1, _M_parameters, _M_num_parameters);
      print_literal(ctx, ".\n");
  
diff -Nrcpad gcc-16-20260627/libstdc++-v3/src/c++11/random.cc gcc-16-20260704/libstdc++-v3/src/c++11/random.cc
*** gcc-16-20260627/libstdc++-v3/src/c++11/random.cc	Sat Jun 27 22:32:19 2026
--- gcc-16-20260704/libstdc++-v3/src/c++11/random.cc	Sat Jul  4 22:32:20 2026
*************** namespace std _GLIBCXX_VISIBILITY(defaul
*** 390,403 ****
      }
  #endif // _GLIBCXX_USE_CRT_RAND_S
  
  #ifdef USE_RDSEED
      if (which & rdseed)
      {
        unsigned int eax, ebx, ecx, edx;
        // Check availability of cpuid and, for now at least, also the
!       // CPU signature for Intel and AMD.
        if (__get_cpuid_max(0, &ebx) > 0
! 	  && (ebx == signature_INTEL_ebx || ebx == signature_AMD_ebx))
  	{
  	  // CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18]
  	  __cpuid_count(7, 0, eax, ebx, ecx, edx);
--- 390,424 ----
      }
  #endif // _GLIBCXX_USE_CRT_RAND_S
  
+ #ifdef USE_RDRAND
+     // For the default device on Hygon prefer RDRAND (faster than RDSEED for
+     // bulk generation); an explicit "rdseed" token still selects rdseed below.
+     if (which == any)
+     {
+       unsigned int eax, ebx, ecx, edx;
+       if (__get_cpuid_max(0, &ebx) > 0 && ebx == signature_HYGON_ebx)
+ 	{
+ 	  // CPUID.01H:ECX.RDRAND[bit 30]
+ 	  __cpuid(1, eax, ebx, ecx, edx);
+ 	  if (ecx & bit_RDRND)
+ 	    {
+ 	      _M_func = &__x86_rdrand;
+ 	      return;
+ 	    }
+ 	}
+     }
+ #endif // USE_RDRAND
+ 
  #ifdef USE_RDSEED
      if (which & rdseed)
      {
        unsigned int eax, ebx, ecx, edx;
        // Check availability of cpuid and, for now at least, also the
!       // CPU signature for Intel, AMD and Hygon.
        if (__get_cpuid_max(0, &ebx) > 0
! 	  && (ebx == signature_INTEL_ebx
! 	      || ebx == signature_AMD_ebx
! 	      || ebx == signature_HYGON_ebx))
  	{
  	  // CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18]
  	  __cpuid_count(7, 0, eax, ebx, ecx, edx);
*************** namespace std _GLIBCXX_VISIBILITY(defaul
*** 425,433 ****
      {
        unsigned int eax, ebx, ecx, edx;
        // Check availability of cpuid and, for now at least, also the
!       // CPU signature for Intel and AMD.
        if (__get_cpuid_max(0, &ebx) > 0
! 	  && (ebx == signature_INTEL_ebx || ebx == signature_AMD_ebx))
  	{
  	  // CPUID.01H:ECX.RDRAND[bit 30]
  	  __cpuid(1, eax, ebx, ecx, edx);
--- 446,456 ----
      {
        unsigned int eax, ebx, ecx, edx;
        // Check availability of cpuid and, for now at least, also the
!       // CPU signature for Intel, AMD and Hygon.
        if (__get_cpuid_max(0, &ebx) > 0
! 	  && (ebx == signature_INTEL_ebx
! 	      || ebx == signature_AMD_ebx
! 	      || ebx == signature_HYGON_ebx))
  	{
  	  // CPUID.01H:ECX.RDRAND[bit 30]
  	  __cpuid(1, eax, ebx, ecx, edx);
diff -Nrcpad gcc-16-20260627/libstdc++-v3/src/c++17/floating_to_chars.cc gcc-16-20260704/libstdc++-v3/src/c++17/floating_to_chars.cc
*** gcc-16-20260627/libstdc++-v3/src/c++17/floating_to_chars.cc	Sat Jun 27 22:32:19 2026
--- gcc-16-20260704/libstdc++-v3/src/c++17/floating_to_chars.cc	Sat Jul  4 22:32:20 2026
***************
*** 26,32 ****
  
  #include <bit>
  #include <cfenv>
- #include <cassert>
  #include <cmath>
  #include <cstdio>
  #include <cstring>
--- 26,31 ----
*************** namespace
*** 106,111 ****
--- 105,113 ----
  
    namespace ryu
    {
+ #pragma push_macro("assert")
+ #undef assert
+ #define assert __glibcxx_assert
  #include "ryu/common.h"
  #include "ryu/digit_table.h"
  #include "ryu/d2s_intrinsics.h"
*************** namespace
*** 123,128 ****
--- 125,131 ----
  # include "ryu/ryu_generic_128.h"
  # include "ryu/generic_128.c"
      } // namespace generic128
+ #pragma pop_macro("assert")
  
      using generic128::floating_decimal_128;
      using generic128::generic_binary_to_decimal;
diff -Nrcpad gcc-16-20260627/libstdc++-v3/src/c++20/format.cc gcc-16-20260704/libstdc++-v3/src/c++20/format.cc
*** gcc-16-20260627/libstdc++-v3/src/c++20/format.cc	Sat Jun 27 22:32:19 2026
--- gcc-16-20260704/libstdc++-v3/src/c++20/format.cc	Sat Jul  4 22:32:20 2026
*************** struct mutex
*** 58,63 ****
--- 58,72 ----
  };
  #endif
  
+ #ifdef _GLIBCXX_HAVE_ICONV
+ // Detect whether type T* can be used as the second argument to iconv.
+ // SUSv2 used 'const char**', but POSIX.1-2003 uses 'char**'.
+ template<typename T>
+   concept iconv_input = requires (::iconv_t cd, T in, size_t n, char** out) {
+     ::iconv(cd, &in, &n, out, &n);
+   };
+ #endif
+ 
  // A non-standard locale::facet that caches the locale's std::text_encoding
  // and an iconv descriptor for converting from that encoding to UTF-8.
  struct __encoding : locale::facet
*************** struct __encoding : locale::facet
*** 111,118 ****
      bool done = false;
  
      auto overwrite = [&](char* p, size_t n) {
        auto inbytes
! 	= const_cast<char*>(input.data()) + input.size() - inbytesleft;
        char* outbytes = p + written;
        size_t outbytesleft = n - written;
        size_t res = ::iconv(_M_cd, &inbytes, &inbytesleft,
--- 120,128 ----
      bool done = false;
  
      auto overwrite = [&](char* p, size_t n) {
+       using input_t = __conditional_t<iconv_input<char*>, char*, const char*>;
        auto inbytes
! 	= const_cast<input_t>(input.data()) + input.size() - inbytesleft;
        char* outbytes = p + written;
        size_t outbytesleft = n - written;
        size_t res = ::iconv(_M_cd, &inbytes, &inbytesleft,
diff -Nrcpad gcc-16-20260627/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/1.cc gcc-16-20260704/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/1.cc
*** gcc-16-20260627/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/1.cc	Sat Jun 27 22:32:19 2026
--- gcc-16-20260704/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/1.cc	Sat Jul  4 22:32:21 2026
***************
*** 1,5 ****
--- 1,6 ----
  // { dg-do run { target c++17 } }
  // { dg-require-filesystem-ts "" }
+ // { dg-require-target-fs-symlinks "" }
  
  #include <filesystem>
  #include <testsuite_hooks.h>
diff -Nrcpad gcc-16-20260627/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/2.cc gcc-16-20260704/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/2.cc
*** gcc-16-20260627/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/2.cc	Sat Jun 27 22:32:19 2026
--- gcc-16-20260704/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/2.cc	Sat Jul  4 22:32:21 2026
***************
*** 1,5 ****
--- 1,6 ----
  // { dg-do run { target c++17 } }
  // { dg-require-filesystem-ts "" }
+ // { dg-require-target-fs-symlinks "" }
  
  #include <filesystem>
  #include <testsuite_hooks.h>
diff -Nrcpad gcc-16-20260627/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/3.cc gcc-16-20260704/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/3.cc
*** gcc-16-20260627/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/3.cc	Sat Jun 27 22:32:19 2026
--- gcc-16-20260704/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/3.cc	Sat Jul  4 22:32:21 2026
***************
*** 1,5 ****
--- 1,6 ----
  // { dg-do run { target c++17 } }
  // { dg-require-filesystem-ts "" }
+ // { dg-require-target-fs-symlinks "" }
  
  #include <filesystem>
  #include <testsuite_hooks.h>
diff -Nrcpad gcc-16-20260627/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/4.cc gcc-16-20260704/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/4.cc
*** gcc-16-20260627/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/4.cc	Sat Jun 27 22:32:19 2026
--- gcc-16-20260704/libstdc++-v3/testsuite/27_io/filesystem/operations/copy_symlink/4.cc	Sat Jul  4 22:32:21 2026
***************
*** 1,5 ****
--- 1,6 ----
  // { dg-do run { target c++17 } }
  // { dg-require-filesystem-ts "" }
+ // { dg-require-target-fs-symlinks "" }
  
  #include <filesystem>
  #include <testsuite_hooks.h>
diff -Nrcpad gcc-16-20260627/libstdc++-v3/testsuite/27_io/filesystem/operations/pr118158.cc gcc-16-20260704/libstdc++-v3/testsuite/27_io/filesystem/operations/pr118158.cc
*** gcc-16-20260627/libstdc++-v3/testsuite/27_io/filesystem/operations/pr118158.cc	Sat Jun 27 22:32:19 2026
--- gcc-16-20260704/libstdc++-v3/testsuite/27_io/filesystem/operations/pr118158.cc	Sat Jul  4 22:32:21 2026
***************
*** 1,5 ****
--- 1,6 ----
  // { dg-do run { target c++17 } }
  // { dg-require-filesystem-ts "" }
+ // { dg-require-mkfifo "" }
  
  #include <filesystem>
  #include <testsuite_fs.h>
diff -Nrcpad gcc-16-20260627/libstdc++-v3/testsuite/std/simd/traits_impl.cc gcc-16-20260704/libstdc++-v3/testsuite/std/simd/traits_impl.cc
*** gcc-16-20260627/libstdc++-v3/testsuite/std/simd/traits_impl.cc	Sat Jun 27 22:32:19 2026
--- gcc-16-20260704/libstdc++-v3/testsuite/std/simd/traits_impl.cc	Sat Jul  4 22:32:21 2026
*************** void test()
*** 48,71 ****
    static_assert(sizeof(_Bitmask<3>) == 1);
    static_assert(sizeof(_Bitmask<30>) == 4);
  
!   static_assert(__scalar_abi_tag<_ScalarAbi<1>>);
!   static_assert(__scalar_abi_tag<_ScalarAbi<2>>);
!   static_assert(!__scalar_abi_tag<_Abi_t<1, 1>>);
! 
!   static_assert(__abi_tag<_ScalarAbi<1>>);
!   static_assert(__abi_tag<_ScalarAbi<2>>);
  
    using AN = decltype(__native_abi<float>());
    using A1 = decltype(__native_abi<float>()._S_resize<1>());
    static_assert(A1::_S_size == 1);
    static_assert(A1::_S_nreg == 1);
    static_assert(A1::_S_variant == AN::_S_variant);
-   static_assert(__scalar_abi_tag<A1> == __scalar_abi_tag<AN>);
    static_assert(std::is_same_v<decltype(__abi_rebind<float, AN::_S_size, A1>()), AN>);
    if constexpr (AN::_S_size >= 2) // the target has SIMD support for float
      {
        {
  	using A2 = decltype(__abi_rebind<float, 2, AN>());
  	static_assert(A2::_S_size == 2);
  	static_assert(A2::_S_nreg == 1);
  	static_assert(A2::_S_variant == AN::_S_variant);
--- 48,68 ----
    static_assert(sizeof(_Bitmask<3>) == 1);
    static_assert(sizeof(_Bitmask<30>) == 4);
  
!   static_assert(__scalar_abi_tag<_Abi_t<1, 1>>);
!   static_assert(__scalar_abi_tag<_Abi_t<2, 2>>);
!   static_assert(!__scalar_abi_tag<_Abi_t<2, 1>>);
  
    using AN = decltype(__native_abi<float>());
    using A1 = decltype(__native_abi<float>()._S_resize<1>());
    static_assert(A1::_S_size == 1);
    static_assert(A1::_S_nreg == 1);
    static_assert(A1::_S_variant == AN::_S_variant);
    static_assert(std::is_same_v<decltype(__abi_rebind<float, AN::_S_size, A1>()), AN>);
    if constexpr (AN::_S_size >= 2) // the target has SIMD support for float
      {
        {
  	using A2 = decltype(__abi_rebind<float, 2, AN>());
+ 	static_assert(__scalar_abi_tag<A2> == __scalar_abi_tag<AN>);
  	static_assert(A2::_S_size == 2);
  	static_assert(A2::_S_nreg == 1);
  	static_assert(A2::_S_variant == AN::_S_variant);
