diff -Nrcpad gcc-15-20260612/LAST_UPDATED gcc-15-20260619/LAST_UPDATED
*** gcc-15-20260612/LAST_UPDATED	Fri Jun 12 22:32:18 2026
--- gcc-15-20260619/LAST_UPDATED	Fri Jun 19 22:32:19 2026
***************
*** 1 ****
! Obtained from git: releases/gcc-15 revision 38bb3d6612ca67697ac46db5b7afccd3773d8bcc
--- 1 ----
! Obtained from git: releases/gcc-15 revision 79c373588fc260a0b127defb57bfaf935383b8a0
diff -Nrcpad gcc-15-20260612/MD5SUMS gcc-15-20260619/MD5SUMS
*** gcc-15-20260612/MD5SUMS	Fri Jun 12 22:32:23 2026
--- gcc-15-20260619/MD5SUMS	Fri Jun 19 22:32:24 2026
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-15-20260612.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-15-20260619.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** d32239bcb673463ab874e80d47fae504  COPYIN
*** 25,31 ****
  fd4ecdf5d672efe2b0e409aca9cf9446  ChangeLog.jit
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! 85eede0ab27b233e6a0eaf91f0faed0f  LAST_UPDATED
  9d2cf5b58292c2e8b0804d3eafc2d6f3  MAINTAINERS
  b714b83dd28679b75c5fd3e619d35956  Makefile.def
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--- 25,31 ----
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*************** c5258891437b4abaf168ed1b1a5b2189  gcc/BA
*** 514,520 ****
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--- 514,520 ----
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*************** fb3fadb88e1d2b3b640cfaaa5ff11780  gcc/Ch
*** 551,557 ****
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! 62dc9aba6855ceb0718c20f5e396921b  gcc/DATESTAMP
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--- 551,557 ----
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*************** e6e86df919407a02a2bcc6baffb28dd6  gcc/co
*** 3383,3391 ****
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! b1dd83319f8b145674747f2ffc4814a9  gcc/common/config/i386/i386-common.cc
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--- 3383,3391 ----
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*************** b5a916bb9dd788754ac9e4ad7174ee74  gcc/co
*** 3420,3426 ****
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--- 3420,3426 ----
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*************** ba4e797220b33827e769b09447623896  gcc/co
*** 3435,3441 ****
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! d0fd5d524d133cb5b494e3b2e01177f8  gcc/config/aarch64/aarch64-early-ra.cc
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  6e8efccd687b154a1a7fcc3e9672274f  gcc/config/aarch64/aarch64-errata.h
--- 3435,3441 ----
  9bac3eb906f180e69a0abe65ec229b05  gcc/config/aarch64/aarch64-cost-tables.h
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! ffd3f9c114be700f647960e0bba8f7b8  gcc/config/aarch64/aarch64-early-ra.cc
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*************** ee7daa62f72913328d9bbce6f6104525  gcc/co
*** 4126,4131 ****
--- 4126,4133 ----
  fd2e2448cdce070eb502784965147928  gcc/config/i386/bmmintrin.h
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  7c0695349cbdcec9d10abf16d9ed2d80  gcc/config/i386/btver2.md
+ 117dc6bff88f6f5dc1ced4feaad9d388  gcc/config/i386/c86-4g-m7.md
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*************** ed2254bdda3903cf7bffcad423af98ae  gcc/co
*** 4135,4141 ****
  5ad53873fee13ffe31a50e133663fd9e  gcc/config/i386/cmpccxaddintrin.h
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! 3880d2a102ee1c35b73e26dea425f8ed  gcc/config/i386/cpuid.h
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--- 4137,4143 ----
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*************** a2bf0873375fc2ab681bcd55a2b23e26  gcc/co
*** 4153,4159 ****
  a5346c37d189bcadf27fd946fe2c2566  gcc/config/i386/djgpp.opt
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! fd6cfaf4d5b29d0d64b44aeea5759534  gcc/config/i386/driver-i386.cc
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  def0edea16aac07cf3e0e7d2daf27455  gcc/config/i386/enqcmdintrin.h
--- 4155,4161 ----
  a5346c37d189bcadf27fd946fe2c2566  gcc/config/i386/djgpp.opt
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! 82fab2f552dc623680c0b2ca0671a723  gcc/config/i386/driver-i386.cc
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*************** c527fd639b424e1e0a95494e13e8cad2  gcc/co
*** 4185,4191 ****
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--- 4187,4193 ----
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! c9b93fa3cbcff84e37b470c61a4c7f65  gcc/config/i386/i386-c.cc
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*************** ba79dc9cffbca47e10d361aeb3d716f3  gcc/co
*** 4194,4200 ****
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--- 4196,4202 ----
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! b2bbbaabe175be303181965daf230053  gcc/config/i386/i386-options.cc
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*************** ba79dc9cffbca47e10d361aeb3d716f3  gcc/co
*** 4202,4210 ****
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! 984423facca351215a6d7f335c0d40bb  gcc/config/i386/i386.cc
! 0150b759a527c67bf0c83ed700545456  gcc/config/i386/i386.h
! 8a8569f9ec65419470ab249f54ecd60a  gcc/config/i386/i386.md
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--- 4204,4212 ----
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! 7e925dbd61d7fe476ab7f718826d5ce0  gcc/config/i386/i386.cc
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*************** a0eef2ed8deb81df9cde53071094d3ff  gcc/co
*** 4230,4236 ****
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! 0bfe63899c97e6d0701a66b4e810d3d8  gcc/config/i386/mmx.md
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  0a902dd4d4e82e9bf2831a3848a102ed  gcc/config/i386/mwaitintrin.h
--- 4232,4238 ----
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! ddce445e18fdfa5ebcb27e7b7b46a18b  gcc/config/i386/mmx.md
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*************** de4e89bc042c6bc7eb093bda5d33a266  gcc/co
*** 4267,4273 ****
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! c8ea31976d63d485f96c63286b3c29a0  gcc/config/i386/sse.md
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--- 4269,4275 ----
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! 778821a1e3b401c74c6e531cad288029  gcc/config/i386/sse.md
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*************** b4cde95b709fc93c90bf4d6b3edc7fd0  gcc/co
*** 4315,4326 ****
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  458dd4e367214623fc01b5e796d65485  gcc/config/i386/x86-64.h
! d4774d1c1bf66446a29da4693ee53d1e  gcc/config/i386/x86-tune-costs.h
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--- 4317,4328 ----
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*************** beaf066ed06870bef361adf40e122f78  gcc/co
*** 4626,4632 ****
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--- 4628,4634 ----
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*************** b467d35485b39b25863e918609a322d0  gcc/co
*** 4939,4945 ****
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--- 4941,4947 ----
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*************** dce39de8bb20b88ffeb8b2073101dcfe  gcc/co
*** 5123,5129 ****
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--- 5125,5131 ----
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*************** a9c3cddee4e237141062720b72fe38cd  gcc/co
*** 5501,5507 ****
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--- 5503,5509 ----
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*************** aaf76a9b03fd0532d2904aef004fd66a  gcc/cp
*** 5586,5592 ****
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--- 5588,5594 ----
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*************** acdfc663791e4321372e79932070d05d  gcc/do
*** 5929,5935 ****
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--- 5931,5937 ----
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*************** ee4c7654f733cefcb73d4fd24f3e1b82  gcc/do
*** 5953,5959 ****
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--- 5955,5961 ----
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*************** e67bf1a2587fc7f7361e841145ff4cfb  gcc/es
*** 6040,6046 ****
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--- 6042,6048 ----
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*************** a798cdca802a57ffa3473ab610b37c86  gcc/fo
*** 6061,6067 ****
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--- 6063,6069 ----
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*************** eceaf6fecb6df7f838b427bf4f70eade  gcc/gi
*** 6278,6284 ****
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--- 6280,6286 ----
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*************** e1e331896b86db8a2281657bbb21ac72  gcc/ip
*** 6480,6486 ****
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--- 6482,6488 ----
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*************** d6625bf8e7676e7c0d45da5ca515ab06  gcc/re
*** 7812,7818 ****
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--- 7814,7820 ----
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*************** cf0f1ba732134068141dc67a09cd47ce  gcc/sh
*** 8394,8400 ****
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--- 8396,8402 ----
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*************** b3a965e425e6cf7888319667faf58da9  gcc/sy
*** 8448,8454 ****
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--- 8450,8456 ----
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*************** ccba3040ed86b5ffae7d72b18f556d1c  gcc/te
*** 18956,18961 ****
--- 18958,18964 ----
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*** 37522,37527 ****
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*** 53752,53757 ****
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*** 53782,53787 ****
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*** 53792,53797 ****
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*************** b0891b1dddf226da47f4f976abdd7cb0  gcc/te
*** 56107,56112 ****
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*************** ec79fa3be7327c757d4abcecfe6afb40  gcc/te
*** 62165,62170 ****
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*************** fc2eb8ac52faed5fba0a017b858d4ae4  gcc/te
*** 68822,68827 ****
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*************** eb024e3b157728adf6d4f14b1bd4c69d  gcc/te
*** 78771,78777 ****
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*** 79097,79103 ****
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*************** dada9b5540f865ba0c0df21dc2b72904  gcc/te
*** 86349,86354 ****
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*************** e990c042b373d09f16b69f4b30f0ac20  gcc/te
*** 89973,89978 ****
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*************** a8b69d6e4817f06059591ac07092f715  gcc/te
*** 90487,90497 ****
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--- 90504,90509 ----
*************** fd4dd1219acc650a4f7855faa0097964  gcc/tr
*** 118376,118382 ****
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*************** cca706bca4e77342da318cc597425137  gcc/tr
*** 118390,118396 ****
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*************** ada2da4e4f03dd37043a0cc6daa67681  gcc/tr
*** 118416,118422 ****
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--- 118428,118434 ----
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*************** a3eb5dee2788fe0a6c42502ba658eddd  libffi
*** 119322,119328 ****
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*************** b38cbc5c54988720ae33d36a2ff78fd3  libgcc
*** 119468,119474 ****
  5ab16e6eec7523296afc7c8bfee38565  libgcc/config/avr/lib1funcs.S
  622f81485f02d0eac2caaafa7d3a2fd1  libgcc/config/avr/lib2-object.mk
  e6604d88f15777c25f5d887ca1f9148c  libgcc/config/avr/lib2funcs.c
! fc2f55c27c607b074a531705055f065d  libgcc/config/avr/libf7/ChangeLog
  dd74908d3b47db38a7aaa2e9f130f20f  libgcc/config/avr/libf7/asm-defs.h
  7f7d24ba47e5a6cfeaf669beb81a0cc2  libgcc/config/avr/libf7/f7-renames.h
  fa695d06eee1fb3d5f9c3d904977f010  libgcc/config/avr/libf7/f7-wraps.h
--- 119480,119486 ----
  5ab16e6eec7523296afc7c8bfee38565  libgcc/config/avr/lib1funcs.S
  622f81485f02d0eac2caaafa7d3a2fd1  libgcc/config/avr/lib2-object.mk
  e6604d88f15777c25f5d887ca1f9148c  libgcc/config/avr/lib2funcs.c
! fa19ada31a2c94750aeb8a0572dad06b  libgcc/config/avr/libf7/ChangeLog
  dd74908d3b47db38a7aaa2e9f130f20f  libgcc/config/avr/libf7/asm-defs.h
  7f7d24ba47e5a6cfeaf669beb81a0cc2  libgcc/config/avr/libf7/f7-renames.h
  fa695d06eee1fb3d5f9c3d904977f010  libgcc/config/avr/libf7/f7-wraps.h
diff -Nrcpad gcc-15-20260612/gcc/ChangeLog gcc-15-20260619/gcc/ChangeLog
*** gcc-15-20260612/gcc/ChangeLog	Fri Jun 12 22:32:04 2026
--- gcc-15-20260619/gcc/ChangeLog	Fri Jun 19 22:32:05 2026
***************
*** 1,3 ****
--- 1,733 ----
+ 2026-06-18  Kewen Lin  <linkewen@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-05-28  Kewen Lin  <linkewen@hygon.cn>
+ 		    Xin Liu  <liulxx@hygon.cn>
+ 
+ 	* config/i386/c86-4g-m7.md (c86_4g_m7_fpu): Remove automaton.
+ 	(c86_4g_m7_fpu02): New automaton.
+ 	(c86_4g_m7_fpu13): Ditto.
+ 	(c86-4g-m7-fpu0): Move to c86_4g_m7_fpu02 automaton.
+ 	(c86-4g-m7-fpu1): Move to c86_4g_m7_fpu13 automaton.
+ 	(c86-4g-m7-fpu2): Move to c86_4g_m7_fpu02 automaton.
+ 	(c86-4g-m7-fpu3): Move to c86_4g_m7_fpu13 automaton.
+ 	(c86-4g-m7-fdiv): Remove cpu unit.
+ 	(c86-4g-m7-fdiv1): New cpu unit.
+ 	(c86-4g-m7-fdiv3): Ditto.
+ 	(c86-4g-m7-fpu_0_3): New reservation.
+ 	(c86-4g-m7-fpu_1_3x2): Ditto.
+ 	(c86-4g-m7-fpu_1_3x3): Ditto.
+ 	(c86-4g-m7-fpu_1_3x6): Ditto.
+ 	(c86-4g-m7-fpux2): Ditto.
+ 	(c86-4g-m7-fpux4): Ditto.
+ 	(c86-4g-m7-fpux6): Ditto.
+ 	(c86-4g-m7-fpux8): Ditto.
+ 	(c86-4g-m7-fpux16): Ditto.
+ 	(c86-4g-m7-fp1fdiv1x4): Ditto.
+ 	(c86-4g-m7-fp3fdiv3x4): Ditto.
+ 	(c86-4g-m7-fdiv13): Ditto.
+ 	(c86-4g-m7-fp13div13): Ditto.
+ 	(c86-4g-m7-fp13div13x4): Ditto.
+ 	(c86-4g-m7-fp1div1_fp3div3_x4x8): Ditto.
+ 	(c86-4g-m7-fp1div1_fp3div3_x4x9): Ditto.
+ 	(c86-4g-m7-fp1div1_fp3div3_x4x11): Ditto.
+ 	(c86-4g-m7-fp1div1_fp3div3_x4x15): Ditto.
+ 	(c86-4g-m7-fp1div1_fp3div3_x4x18): Ditto.
+ 	(c86_4g_m7_idiv): New reservation.
+ 	(c86_4g_m7_idiv_QI): Adjust reservation latency and unit occupancy.
+ 	(c86_4g_m7_idiv_load): New reservation.
+ 	(c86_4g_m7_idiv_QI_load): Adjust reservation latency and unit
+ 	occupancy.
+ 	(c86_4g_m7_idiv_DI): Remove reservation.
+ 	(c86_4g_m7_idiv_SI): Ditto.
+ 	(c86_4g_m7_idiv_HI): Ditto.
+ 	(c86_4g_m7_idiv_DI_load): Ditto.
+ 	(c86_4g_m7_idiv_SI_load): Ditto.
+ 	(c86_4g_m7_idiv_HI_load): Ditto.
+ 	(c86_4g_m7_sse_insertimm): Adjust reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_sse_insert): Ditto.
+ 	(c86_4g_m7_fp_sqrt): Adjust reservation.
+ 	(c86_4g_m7_fp_div): Ditto.
+ 	(c86_4g_m7_fp_div_load): Ditto.
+ 	(c86_4g_m7_fp_idiv_load): Ditto.
+ 	(c86_4g_m7_sse_pinsr_reg): Adjust reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_sse_pinsr_reg_load): Ditto.
+ 	(c86_4g_m7_avx_vpinsr_reg): Ditto.
+ 	(c86_4g_m7_avx_vpinsr_reg_load): Ditto.
+ 	(c86_4g_m7_avx512_perm_xmm): Delete the prefix condition.
+ 	(c86_4g_m7_avx512_perm_xmm_opload): Ditto.
+ 	(c86_4g_m7_avx512_permi2_ymm): Adjust reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_avx512_permi2_zmm): Ditto.
+ 	(c86_4g_m7_avx512_permi2_ymm_load): Ditto.
+ 	(c86_4g_m7_avx512_permi2_zmm_load): Ditto.
+ 	(c86_4g_m7_avx512_perm_zmm_imm): Ditto.
+ 	(c86_4g_m7_avx512_perm_zmm_imm_load): Ditto.
+ 	(c86_4g_m7_avx512_perm_zmm_noimm): Ditto.
+ 	(c86_4g_m7_sse_perm_zmm_noimm_load): Ditto.
+ 	(c86_4g_m7_avx_perm_ymm): Remove.
+ 	(c86_4g_m7_avx_perm_ymem): Ditto.
+ 	(c86_4g_m7_avx512_shuf_zmm): Adjust reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_avx512_shuf_zmem): Ditto.
+ 	(c86_4g_m7_avx512_cmpestr): Ditto.
+ 	(c86_4g_m7_avx512_cmpestr_load): Ditto.
+ 	(c86_4g_m7_avx512_vdbpsadbw_zmm): Ditto.
+ 	(c86_4g_m7_avx512_vdbpsadbw_zmem): Ditto.
+ 	(c86_4g_m7_avx_ssecomi_comi): Ditto.
+ 	(c86_4g_m7_avx_ssecomi_comi_load): Ditto.
+ 	(c86_4g_m7_avx512_expand): Ditto.
+ 	(c86_4g_m7_avx512_expand_load): Ditto.
+ 	(c86_4g_m7_avx512_expand_z): Ditto.
+ 	(c86_4g_m7_avx512_expand_z_load): Ditto.
+ 	(c86_4g_m7_sse_movnt_xy): Rename to c86_4g_m7_sse_movnt.
+ 	(c86_4g_m7_avx512_sseadd_xy): Adjust reservation units.
+ 	(c86_4g_m7_avx512_sseadd_xy_load): Ditto.
+ 	(c86_4g_m7_sse_sseiadd_hplus): Adjust reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_sse_sseiadd_hplus_load): Ditto.
+ 	(c86_4g_m7_avx512_ssemul): Adjust reservation units.
+ 	(c86_4g_m7_avx512_ssemul_load): Ditto.
+ 	(c86_4g_m7_avx512_ssediv): Remove.
+ 	(c86_4g_m7_avx512_ssediv_mem): Remove.
+ 	(c86_4g_m7_avx512_ssediv_x): New.
+ 	(c86_4g_m7_avx512_ssediv_xmem): New.
+ 	(c86_4g_m7_avx512_ssediv_y): New.
+ 	(c86_4g_m7_avx512_ssediv_ymem): New.
+ 	(c86_4g_m7_avx512_ssediv_z): Adjust reservation units.
+ 	(c86_4g_m7_avx512_ssediv_zmem): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_z): Add reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_avx512_ssecmp_z_load): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_vp_z): New reservation.
+ 	(c86_4g_m7_avx512_ssecmp_vp_z_load): Ditto.
+ 	(c86_4g_m7_avx512_ssecmp_test_z): Remove reservation.
+ 	(c86_4g_m7_avx512_ssecmp_test_z_load): Ditto.
+ 	(c86_4g_m7_avx512_muladd): Broaden matching condition.
+ 	(c86_4g_m7_avx512_muladd_load): Ditto.
+ 	(c86_4g_m7_fma_muladd): Remove reservation.
+ 	(c86_4g_m7_fma_muladd_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_x): Add reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_avx512_sse_conflict_x_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_y): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_y_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_z): Ditto.
+ 	(c86_4g_m7_avx512_sse_conflict_z_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_class_z): Add reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_avx512_sse_class_z_load): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt): Remove.
+ 	(c86_4g_m7_avx512_sse_sqrt_load): Remove.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_x): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_xload): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_y): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_yload): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_z): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_sf_zload): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_x): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_xload): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_y): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_yload): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_z): New.
+ 	(c86_4g_m7_avx512_sse_sqrt_df_zload): New.
+ 	(c86_4g_m7_avx512_msklog_vector): Add reservation units and unit
+ 	occupancy.
+ 	(c86_4g_m7_avx512_mskmov_z_k): Ditto.
+ 	(c86_4g_m7_avx512_mskmov_k_reg): Ditto.
+ 	* config/i386/c86-4g.md (c86_4g_fp): Remove automaton.
+ 	(c86_4g_fp024): New automaton.
+ 	(c86_4g_fp1): Ditto.
+ 	(c86-4g-fp0): Move to c86_4g_fp024 automaton.
+ 	(c86-4g-fp1): Move to c86_4g_fp1 automaton.
+ 	(c86-4g-fp2): Move to c86_4g_fp024 automaton.
+ 	(c86-4g-fp3): Ditto.
+ 	(c86-4g-fp1fdivx4): New reservation.
+ 	(c86_4g_fp_sqrt): Adjust reservation.
+ 	(c86_4g_sse_sqrt_sf): Ditto.
+ 	(c86_4g_sse_sqrt_sf_mem): Ditto.
+ 	(c86_4g_sse_sqrt_df): Ditto.
+ 	(c86_4g_sse_sqrt_df_mem): Ditto.
+ 	(c86_4g_fp_op_div): Ditto.
+ 	(c86_4g_fp_op_div_load): Ditto.
+ 	(c86_4g_fp_op_idiv_load): Adjust reservation latency.
+ 	(c86_4g_ssediv_ss_ps): Adjust reservation.
+ 	(c86_4g_ssediv_ss_ps_load): Ditto.
+ 	(c86_4g_ssediv_sd_pd): Ditto.
+ 	(c86_4g_ssediv_sd_pd_load): Ditto.
+ 	(c86_4g_ssediv_avx256_ps): Ditto.
+ 	(c86_4g_ssediv_avx256_ps_load): Ditto.
+ 	(c86_4g_ssediv_avx256_pd): Ditto.
+ 	(c86_4g_ssediv_avx256_pd_load): Ditto.
+ 
+ 2026-06-18  Kewen Lin  <linkewen@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-05-01  Kewen Lin  <linkewen@hygon.cn>
+ 
+ 	* config/i386/c86-4g-m7.md (c86_4g_m7_idiv): New automaton.
+ 	(c86_4g_m7_fdiv): Ditto.
+ 	(c86-4g-m7-idiv): New unit.
+ 	(c86-4g-m7-fdiv): Ditto.
+ 	(c86_4g_m7_idiv_DI): Adjust unit in the reservation.
+ 	(c86_4g_m7_idiv_SI): Ditto.
+ 	(c86_4g_m7_idiv_HI): Ditto.
+ 	(c86_4g_m7_idiv_QI): Ditto.
+ 	(c86_4g_m7_idiv_DI_load): Ditto.
+ 	(c86_4g_m7_idiv_SI_load): Ditto.
+ 	(c86_4g_m7_idiv_HI_load): Ditto.
+ 	(c86_4g_m7_idiv_QI_load): Ditto.
+ 	(c86_4g_m7_fp_div): Ditto.
+ 	(c86_4g_m7_fp_div_load): Ditto.
+ 	(c86_4g_m7_fp_idiv_load): Ditto.
+ 	(c86_4g_m7_avx512_ssediv): Ditto.
+ 	(c86_4g_m7_avx512_ssediv_mem): Ditto.
+ 	(c86_4g_m7_avx512_ssediv_z): Ditto.
+ 	(c86_4g_m7_avx512_ssediv_zmem): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt): Ditto.
+ 	(c86_4g_m7_avx512_sse_sqrt_load): Ditto.
+ 	(c86_4g_m7_fp_sqrt): Ditto.  Rename from ...
+ 	(c86_4g_m7fp_sqrt): ... here.
+ 	* config/i386/c86-4g.md (c86_4g_idiv): New automaton.
+ 	(c86_4g_fdiv): Ditto.
+ 	(c86-4g-idiv): New unit.
+ 	(c86-4g-fdiv): Ditto.
+ 	(c86_4g_idiv_DI): Ditto.
+ 	(c86_4g_idiv_SI): Ditto.
+ 	(c86_4g_idiv_HI): Ditto.
+ 	(c86_4g_idiv_QI): Ditto.
+ 	(c86_4g_idiv_mem_DI): Ditto.
+ 	(c86_4g_idiv_mem_SI): Ditto.
+ 	(c86_4g_idiv_mem_HI): Ditto.
+ 	(c86_4g_idiv_mem_QI): Ditto.
+ 	(c86_4g_fp_sqrt): Ditto.
+ 	(c86_4g_sse_sqrt_sf): Ditto.
+ 	(c86_4g_sse_sqrt_sf_mem): Ditto.
+ 	(c86_4g_sse_sqrt_df): Ditto.
+ 	(c86_4g_sse_sqrt_df_mem): Ditto.
+ 	(c86_4g_fp_op_div): Ditto.
+ 	(c86_4g_fp_op_div_load): Ditto.
+ 	(c86_4g_fp_op_idiv_load): Ditto.
+ 	(c86_4g_ssediv_ss_ps): Ditto.
+ 	(c86_4g_ssediv_ss_ps_load): Ditto.
+ 	(c86_4g_ssediv_ss_pd): Ditto.
+ 	(c86_4g_ssediv_ss_pd_load): Ditto.
+ 	(c86_4g_ssediv_avx256_ps): Ditto.
+ 	(c86_4g_ssediv_avx256_ps_load): Ditto.
+ 	(c86_4g_ssediv_avx256_pd): Ditto.
+ 	(c86_4g_ssediv_avx256_pd_load): Ditto.
+ 
+ 2026-06-18  Xin Liu  <liulxx@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-04-29  Xin Liu  <liulxx@hygon.cn>
+ 		    Zhaoling Bao  <baozhaoling@hygon.cn>
+ 
+ 	* common/config/i386/cpuinfo.h (get_hygon_cpu): Detect the specific
+ 	type of HYGON CPU and return HYGON CPU name.
+ 	(cpu_indicator_init): Handle HYGON CPU.
+ 	* common/config/i386/i386-common.cc (processor_names): Add HYGON
+ 	C86-4G processors c86-4g-m{4,6,7}.
+ 	(processor_alias_table): Add hygon, hygonfam18h and c86-4g-m{4,6,7}
+ 	entries.
+ 	(ARRAY_SIZE): Update as new entries added.
+ 	* common/config/i386/i386-cpuinfo.h (enum processor_vendor): Add
+ 	VENDOR_HYGON.
+ 	(enum processor_types): Add HYGONFAM18H.
+ 	(enum processor_subtypes): Add HYGONFAM18H_C86_4G_M{4,6,7}.
+ 	* config.gcc: Add support for c86_4g_m{4,6,7}.
+ 	* config/i386/cpuid.h (signature_HYGON_ebx):  Add signature for HYGON.
+ 	(signature_HYGON_ecx): Ditto.
+ 	(signature_HYGON_edx): Ditto.
+ 	* config/i386/driver-i386.cc (host_detect_local_cpu): Support HYGON
+ 	c86-4g-m4{4,6,7} processors.
+ 	* config/i386/i386-c.cc (ix86_target_macros_internal): Ditto.
+ 	* config/i386/i386-options.cc (m_C86_4G_M4): New definition.
+ 	(m_C86_4G_M6): Ditto.
+ 	(m_C86_4G_M7): Ditto.
+ 	(m_C86_4G): Ditto.
+ 	(processor_cost_table): Add cost entries for c86-4g-m4{4,6,7}.
+ 	* config/i386/i386.cc (ix86_reassociation_width): Add handlings for
+ 	PROCESSOR_C86_4G_M{4,6,7}.
+ 	* config/i386/i386.h (enum processor_type): Define
+ 	PROCESSOR_C86_4G_M{4,6,7}.
+ 	(PTA_C86_4G_M4): New define.
+ 	(PTA_C86_4G_M6): Ditto.
+ 	(PTA_C86_4G_M7): Ditto.
+ 	* config/i386/x86-tune-costs.h (c86_4g_m4_memcpy): New stringop_algs.
+ 	(c86_4g_m4_cost): New processor_costs.
+ 	(c86_4g_m6_cost): Ditto.
+ 	(c86_4g_m7_cost): Ditto.
+ 	* config/i386/x86-tune-sched.cc (ix86_issue_rate): Handle
+ 	PROCESSOR_C86_4G_M{4,6,7}.
+ 	(ix86_adjust_cost): Ditto.
+ 	* config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Handle m_C86_4G.
+ 	(X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto.
+ 	(X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto.
+ 	(X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto.
+ 	(X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto.
+ 	(X86_TUNE_MEMORY_MISMATCH_STALL): Ditto.
+ 	(X86_TUNE_FUSE_CMP_AND_BRANCH_32): Ditto.
+ 	(X86_TUNE_FUSE_CMP_AND_BRANCH_64): Ditto.
+ 	(X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS): Ditto.
+ 	(X86_TUNE_USE_LEAVE): Ditto.
+ 	(X86_TUNE_PUSH_MEMORY): Ditto.
+ 	(X86_TUNE_INTEGER_DFMODE_MOVES): Ditto.
+ 	(X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto.
+ 	(X86_TUNE_USE_SAHF): Ditto.
+ 	(X86_TUNE_USE_BT): Ditto.
+ 	(X86_TUNE_AVOID_MFENCE): Ditto.
+ 	(X86_TUNE_USE_FFREEP): Ditto.
+ 	(X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto.
+ 	(X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL): Ditto.
+ 	(X86_TUNE_SSE_TYPELESS_STORES): Ditto.
+ 	(X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto.
+ 	(X86_TUNE_USE_GATHER_2PARTS): Ditto.
+ 	(X86_TUNE_USE_GATHER_4PARTS): Ditto.
+ 	(X86_TUNE_USE_GATHER_8PARTS): Ditto.
+ 	(X86_TUNE_AVOID_128FMA_CHAINS): Ditto.
+ 	(X86_TUNE_AVOID_256FMA_CHAINS): Ditto.
+ 	(X86_TUNE_USE_RCR): Ditto.
+ 	(X86_TUNE_AVX256_MOVE_BY_PIECES): Handle m_C86_4G_M{4,6}.
+ 	(X86_TUNE_USE_SCATTER_2PARTS): Handle m_C86_4G_M7.
+ 	(X86_TUNE_USE_SCATTER_4PARTS): Ditto.
+ 	(X86_TUNE_USE_SCATTER_8PARTS): Ditto.
+ 	(X86_TUNE_AVX512_SPLIT_REGS): Ditto.
+ 	(X86_TUNE_AVX256_MOVE_BY_PIECES): Ditto.
+ 	(X86_TUNE_AVX256_STORE_BY_PIECES): Ditto.
+ 	(X86_TUNE_AVX512_MOVE_BY_PIECES): Ditto.
+ 	(X86_TUNE_AVX512_STORE_BY_PIECES): Ditto.
+ 	* doc/extend.texi: Document about hygonfam18h and c86-4g-m{4,6,7}.
+ 	* doc/invoke.texi: Document about c86-4g-m{4,6,7}.
+ 	* config/i386/c86-4g-m7.md: New file for c86-4g-m7 scheduling model
+ 	information.
+ 	* config/i386/c86-4g.md: New file for c86-4g-m{4,6} scheduling model
+ 	information.
+ 	* config/i386/i386.md (cpu attr): Add c86_4g_m{4,6,7}.
+ 	(c86-4g.md): New include.
+ 	(c86-4g-m7.md): Ditto.
+ 	(*cmpi<unord>xf_i387): Set attr c86_decode.
+ 	(*cmpi<unord><MODEF:mode>): Ditto.
+ 	(swap<mode>): Ditto.
+ 	(*swap<mode>): Ditto.
+ 	(extendhisi2): Ditto.
+ 	(floathi<mode>2): Ditto.
+ 	(float<SWI48x:mode>xf2): Ditto.
+ 	(*float<SWI48:mode><MODEF:mode>2): Ditto.
+ 	(*floatdi<MODEF:mode>2_i387): Ditto.
+ 	(*anddi_1_bt): Ditto.
+ 	(*iordi_1_bts): Ditto.
+ 	(*xordi_1_btc): Ditto.
+ 	(*<btsc><mode>): Ditto.
+ 	(*btr<mode>): Ditto.
+ 	(*btsq_imm): Ditto.
+ 	(*btrq_imm): Ditto.
+ 	(*btcq_imm): Ditto.
+ 	(*tzcnt<mode>_1): Ditto.
+ 	(*tzcnt<mode>_1_falsedep): Ditto.
+ 	(*bsf<mode>_1): Ditto.
+ 	(*ctz<mode>2_falsedep): Ditto.
+ 	(*ctzsi2_zext): Ditto.
+ 	(*ctzsi2_zext_falsedep): Ditto.
+ 	(bsr_rex64): Ditto.
+ 	(bsr_rex64_1): Ditto.
+ 	(bsr_rex64_1_zext): Ditto.
+ 	(bsr): Ditto.
+ 	(bsr_1): Ditto.
+ 	(bsr_zext_1): Ditto.
+ 	(*bswaphi2_movbe): Ditto.
+ 	(*bswaphi2): Ditto.
+ 	(bswaphisi2_lowpart): Ditto.
+ 	(fpremxf4_i387): Ditto.
+ 	(fprem1xf4_i387): Ditto.
+ 	(<sincos>xf2): Ditto.
+ 	(sincosxf3): Ditto.
+ 	(fptanxf4_i387): Ditto.
+ 	(atan2xf3): Ditto.
+ 	(fyl2xxf3_i387): Ditto.
+ 	(fyl2xp1xf3_i387): Ditto.
+ 	(fxtractxf3_i387): Ditto.
+ 	(*f2xm1xf2_i387): Ditto.
+ 	(fscalexf4_i387): Ditto.
+ 	(rintxf2): Ditto.
+ 	(*movxi_internal_avx512f): Set attr c86_attr.
+ 	(*movoi_internal_avx): Ditto.
+ 	(*movti_internal): Ditto.
+ 	(*movdi_internal): Ditto.
+ 	(*movsi_internal): Ditto.
+ 	(*movhi_internal): Ditto.
+ 	(*movtf_internal): Ditto.
+ 	(*movdf_internal): Ditto.
+ 	(*movsf_internal): Ditto.
+ 	(*zero_extendsidi2): Ditto.
+ 	(sqrtxf2): Ditto.
+ 	(<smaxmin:code><mode>3): Ditto.
+ 	(*ieee_s<ieee_maxmin><mode>3): Ditto.
+ 	* config/i386/mmx.md (*mmx_maskmovq): Set attr c86_decode.
+ 	(*mmx_maskmovq): Ditto.
+ 	(sse_movntq): Set attr c86_attr.
+ 	(*mmx_blendps): Ditto.
+ 	(mmx_blendvps): Ditto.
+ 	(*mmx_pmaddwd): Ditto.
+ 	(mmx_pblendvb_v8qi): Ditto.
+ 	(mmx_pblendvb_<mode>): Ditto.
+ 	(sse4_1_<code>v4qiv4hi2): Ditto.
+ 	(sse4_1_<code>v2hiv2si2): Ditto.
+ 	(sse4_1_<code>v2qiv2si2): Ditto.
+ 	(sse4_1_<code>v2qiv2hi2): Ditto.
+ 	(*mmx_pinsrd): Ditto.
+ 	(*mmx_pinsrw): Ditto.
+ 	(*mmx_pinsrb): Ditto.
+ 	(*mmx_pextrw): Ditto.
+ 	(*mmx_pextrw<mode>): Ditto.
+ 	(*mmx_pextrw_zext): Ditto.
+ 	(*mmx_pextrb): Ditto.
+ 	(*mmx_pextrb_zext): Ditto.
+ 	(*mmx_pblendw64): Ditto.
+ 	(*mmx_pblendw32): Ditto.
+ 	(*vec_extractv2si_1): Ditto.
+ 	(*vec_extractv2si_1_zext): Ditto.
+ 	(*pinsrw): Ditto.
+ 	(*pinsrb): Ditto.
+ 	(*pextrw): Ditto.
+ 	(*pextrw<mode>): Ditto.
+ 	(*pextrw_zext): Ditto.
+ 	(*pextrb): Ditto.
+ 	(*pextrb_zext): Ditto.
+ 	(*mmx_psadbw): Ditto.
+ 	* config/i386/sse.md (ktest<mode>): Set attr c86_decode.
+ 	(*kortest<mode>): Ditto.
+ 	(sse_cvtsi2ss<rex64namesuffix><round_name>): Ditto.
+ 	(sse2_cvtsi2sd): Ditto.
+ 	(sse2_maskmovdqu): Ditto.
+ 	(*<sse>_dp<ssemodesuffix><avxsizesuffix>): Ditto.
+ 	(*<sse4_1_avx2>_mpsadbw): Ditto.
+ 	(pclmulqdq): Ditto.
+ 	(<mask_codefor>conflict<mode><mask_name>): Ditto.
+ 	(<avx512>_blendm<mode>): Set attr c86_attr.
+ 	(sse2_movnti<mode>): Ditto.
+ 	(<sse>_movnt<mode>): Ditto.
+ 	(<sse2>_movnt<mode>): Ditto.
+ 	(<sse>_rcp<mode>2): Ditto.
+ 	(sse_vmrcpv4sf2): Ditto.
+ 	(<mask_codefor>rcp14<mode><mask_name>): Ditto.
+ 	(srcp14<mode>): Ditto.
+ 	(srcp14<mode>_mask): Ditto.
+ 	(<sse>_sqrt<mode>2<mask_name><round_name>): Ditto.
+ 	(<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>): Ditto.
+ 	(*<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>): Ditto.
+ 	(<mask_codefor>rsqrt14<mode><mask_name>): Ditto.
+ 	(rsqrt14<mode>): Ditto.
+ 	(rsqrt14_<mode>_mask"): Ditto.
+ 	(*<code><mode>3<mask_name><round_saeonly_name>): Ditto.
+ 	(ieee_<ieee_maxmin><mode>3<mask_name><round_saeonly_name>): Ditto.
+ 	(*<sse>_vm<code><mode>3<mask_scalar_name><round_saeonly_scalar_name>):
+ 	Ditto.
+ 	(<sse>_ieee_vm<ieee_maxmin><mode>3<mask_scalar_name>
+ 	<round_saeonly_scalar_name>): Ditto.
+ 	(*ieee_<ieee_maxmin><mode>3): Ditto.
+ 	(avx_h<insn>v4df3): Ditto.
+ 	(*sse3_haddv2df3): Ditto.
+ 	(sse3_hsubv2df3): Ditto.
+ 	(*sse3_haddv2df3_low): Ditto.
+ 	(*sse3_hsubv2df3_low): Ditto.
+ 	(avx_h<insn>v8sf3): Ditto.
+ 	(sse3_h<insn>v4sf3): Ditto.
+ 	(*<mask_codefor>reducep<mode><mask_name><round_saeonly_name>): Ditto.
+ 	(reduces<mode><mask_scalar_name><round_saeonly_scalar_name>): Ditto.
+ 	(*<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Ditto.
+ 	(<sse>_andnot<mode>3<mask_name>): Ditto.
+ 	(*<code><mode>3<mask_name>): Ditto.
+ 	(*andnot<mode>3): Ditto.
+ 	(<code><mode>3): Ditto.
+ 	(*<code>tf3): Ditto.
+ 	(vec_set<mode>_0): Ditto.
+ 	(@vec_set<mode>_0): Ditto.
+ 	(*sse4_1_extractps): Ditto.
+ 	(vec_extract<mode>): Ditto.
+ 	(<mask_codefor><avx512>_align<mode><mask_name>): Ditto.
+ 	(avx512bw_pmaddwd512<mode><mask_name>): Ditto.
+ 	(*avx2_pmaddw): Ditto.
+ 	(*sse2_pmaddwd): Ditto.
+ 	(*avx2_<code><mode>3): Ditto.
+ 	(*avx512f_<code><mode>3<mask_name>): Ditto.
+ 	(*avx512bw_<code><mode>3<mask_name>): Ditto.
+ 	(*sse4_1_<code><mode>3<mask_name>): Ditto.
+ 	(*<code>v8hi3): Ditto.
+ 	(*<code>v16qi3): Ditto.
+ 	(*andnot<mode>3_mask): Ditto.
+ 	(*<code><mode>3): Ditto.
+ 	(<code>v1ti3): Ditto.
+ 	(<sse2p4_1>_pinsr<ssemodesuffix>): Ditto.
+ 	(*<extract_type>_vinsert<shuffletype><extract_suf>_0): Ditto.
+ 	(<mask_codefor><extract_type>_vinsert<shuffletype><extract_suf>
+ 	_1<mask_name>): Ditto.
+ 	(vec_set_lo_<mode><mask_name>): Ditto.
+ 	(vec_set_hi_<mode><mask_name>): Ditto.
+ 	(<mask_codefor>avx512dq_shuf_<shuffletype>64x2_1<mask_name>): Ditto.
+ 	(avx512f_shuf_<shuffletype>64x2_1<mask_name>): Ditto.
+ 	(*avx512f_shuf_<shuffletype>64x2_1<mask_name>_1): Ditto.
+ 	(avx512vl_shuf_<shuffletype>32x4_1<mask_name>): Ditto.
+ 	(avx512f_shuf_<shuffletype>32x4_1<mask_name>): Ditto.
+ 	(*avx512f_shuf_<shuffletype>32x4_1<mask_name>_1): Ditto.
+ 	(*vec_extract<mode>): Ditto.
+ 	(*vec_extract<PEXTR_MODE12:mode>_zext): Ditto.
+ 	(*vec_extractv16qi_zext): Ditto.
+ 	(*vec_extractv4si): Ditto.
+ 	(*vec_extractv4si_zext): Ditto.
+ 	(*vec_extractv2di_1): Ditto.
+ 	(*vec_concatv2si_sse4_1): Ditto.
+ 	(vec_concatv2di): Ditto.
+ 	(*<sse2_avx2>_uavg<mode>3<mask_name>): Ditto.
+ 	(*<sse2_avx2>_psadbw): Ditto.
+ 	(<sse>_movmsk<ssemodesuffix><avxsizesuffix>): Ditto.
+ 	(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): Ditto.
+ 	(<sse2_avx2>_pmovmskb): Ditto.
+ 	(*<sse2_avx2>_pmovmskb_zext): Ditto.
+ 	(*sse2_maskmovdqu): Ditto.
+ 	(avx2_ph<plusminus_mnemonic>wv16hi3): Ditto.
+ 	(ssse3_ph<plusminus_mnemonic>wv8hi3): Ditto.
+ 	(ssse3_ph<plusminus_mnemonic>dv4si3): Ditto.
+ 	(avx2_ph<plusminus_mnemonic>dv8si3): Ditto.
+ 	(avx2_pmaddubsw256): Ditto.
+ 	(avx512bw_pmaddubsw512<mode><mask_name>): Ditto.
+ 	(ssse3_pmaddubsw128): Ditto.
+ 	(<ssse3_avx2>_psign<mode>3): Ditto.
+ 	(ssse3_psign<mode>3): Ditto.
+ 	(*abs<mode>2): Ditto.
+ 	(abs<mode>2_mask): Ditto.
+ 	(abs<mode>2_mask): Ditto.
+ 	(sse4a_movnt<mode>): Ditto.
+ 	(sse4a_vmmovnt<mode>): Ditto.
+ 	(<sse4_1>_blend<ssemodesuffix><avxsizesuffix>): Ditto.
+ 	(<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>): Ditto.
+ 	(sse4_1_blendv<ssemodesuffix>): Ditto.
+ 	(<vi8_sse4_1_avx2_avx512>_movntdqa): Ditto.
+ 	(<sse4_1_avx2>_pblendvb): Ditto.
+ 	(sse4_1_pblend<ssemodesuffix>): Ditto.
+ 	(*avx2_pblend<ssemodesuffix>): Ditto.
+ 	(avx2_pblendd<mode>): Ditto.
+ 	(avx2_<code>v16qiv16hi2<mask_name>): Ditto.
+ 	(avx512bw_<code>v32qiv32hi2<mask_name>): Ditto.
+ 	(sse4_1_<code>v8qiv8hi2<mask_name>): Ditto.
+ 	(*sse4_1_<code>v8qiv8hi2<mask_name>_1): Ditto.
+ 	(<mask_codefor>avx512f_<code>v16qiv16si2<mask_name>): Ditto.
+ 	(avx2_<code>v8qiv8si2<mask_name>): Ditto.
+ 	(*avx2_<code>v8qiv8si2<mask_name>_1): Ditto.
+ 	(sse4_1_<code>v4qiv4si2<mask_name>): Ditto.
+ 	(*sse4_1_<code>v4qiv4si2<mask_name>_1): Ditto.
+ 	(avx512f_<code>v16hiv16si2<mask_name>): Ditto.
+ 	(avx2_<code>v8hiv8si2<mask_name>): Ditto.
+ 	(sse4_1_<code>v4hiv4si2<mask_name>): Ditto.
+ 	(*sse4_1_<code>v4hiv4si2<mask_name>_1): Ditto.
+ 	(avx512f_<code>v8qiv8di2<mask_name>): Ditto.
+ 	(*avx512f_<code>v8qiv8di2<mask_name>_1): Ditto.
+ 	(avx2_<code>v4qiv4di2<mask_name>): Ditto.
+ 	(*avx2_<code>v4qiv4di2<mask_name>_1): Ditto.
+ 	(sse4_1_<code>v2qiv2di2<mask_name>): Ditto.
+ 	(*sse4_1_<code>v2qiv2di2<mask_name>_1): Ditto.
+ 	(avx512f_<code>v8hiv8di2<mask_name>): Ditto.
+ 	(avx2_<code>v4hiv4di2<mask_name>): Ditto.
+ 	(*avx2_<code>v4hiv4di2<mask_name>_1): Ditto.
+ 	(sse4_1_<code>v2hiv2di2<mask_name>): Ditto.
+ 	(*sse4_1_<code>v2hiv2di2<mask_name>_1): Ditto.
+ 	(avx512f_<code>v8siv8di2<mask_name>): Ditto.
+ 	(avx2_<code>v4siv4di2<mask_name>): Ditto.
+ 	(sse4_1_<code>v2siv2di2<mask_name>): Ditto.
+ 	(*sse4_1_<code>v2siv2di2<mask_name>_1): Ditto.
+ 	(sse4_1_round<ssescalarmodesuffix>): Ditto.
+ 	(*sse4_1_round<ssescalarmodesuffix>"): Ditto.
+ 	(sse4_2_pcmpestri): Ditto.
+ 	(sse4_2_pcmpestrm): Ditto.
+ 	(sse4_2_pcmpestr_cconly): Ditto.
+ 	(sse4_2_pcmpistri): Ditto.
+ 	(sse4_2_pcmpistrm): Ditto.
+ 	(sse4_2_pcmpistr_cconly): Ditto.
+ 	(xop_phadd<u>bw): Ditto.
+ 	(xop_phadd<u>bd): Ditto.
+ 	(xop_phadd<u>bq): Ditto.
+ 	(xop_phadd<u>wd): Ditto.
+ 	(xop_phadd<u>wq): Ditto.
+ 	(xop_phadd<u>dq): Ditto.
+ 	(xop_phsubbw): Ditto.
+ 	(xop_phsubwd): Ditto.
+ 	(xop_phsubdq): Ditto.
+ 	(aesenc): Ditto.
+ 	(aesenclast): Ditto.
+ 	(aesdec): Ditto.
+ 	(aesdeclast): Ditto.
+ 	(aesimc): Ditto.
+ 	(aeskeygenassist): Ditto.
+ 	(<avx2_avx512>_permvar<mode><mask_name>): Ditto.
+ 	(avx2_perm<mode>_1<mask_name>): Ditto.
+ 	(<avx512>_permvar<mode><mask_name>): Ditto.
+ 	(avx512f_perm<mode>_1<mask_name>): Ditto.
+ 	(<mask_codefor>avx512f_broadcast<mode><mask_name>): Ditto.
+ 	(avx_vbroadcastf128_<mode>): Ditto.
+ 	(<mask_codefor>avx512vl_broadcast<mode><mask_name>_1): Ditto.
+ 	(<mask_codefor>avx512dq_broadcast<mode><mask_name>_1): Ditto.
+ 	(*<avx512>_vpermi2var<mode>3_mask): Ditto.
+ 	(<avx512>_vpermt2var<mode>3<sd_maskz_name>): Ditto.
+ 	(<avx512>_vpermt2var<mode>3_mask): Ditto.
+ 	(*avx_vperm2f128<mode>_nozero): Ditto.
+ 	(vec_set_lo_<mode><mask_name>): Ditto.
+ 	(vec_set_hi_<mode><mask_name>): Ditto.
+ 	(vec_set_lo_<mode>): Ditto.
+ 	(vec_set_hi_<mode>): Ditto.
+ 	(vec_set_lo_v32qi): Ditto.
+ 	(<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>): Ditto.
+ 	(<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>): Ditto.
+ 	(avx_vec_concat<mode>): Ditto.
+ 	(<avx512>_compress<mode>_mask): Ditto.
+ 	(compress<mode>_mask): Ditto.
+ 	(<avx512>_compressstore<mode>_mask): Ditto.
+ 	(compressstore<mode>_mask): Ditto.
+ 	(expand<mode>_mask): Ditto.
+ 	(<mask_codefor>avx512bw_dbpsadbw<mode><mask_name>): Ditto.
+ 	(clz<mode>2<mask_name>): Ditto.
+ 	(vpmadd52<vpmadd52type>v8di): Ditto.
+ 	(vpmadd52<vpmadd52type><mode>): Ditto.
+ 	(vpmadd52<vpmadd52type><mode>_maskz_1): Ditto.
+ 	(vpmadd52<vpmadd52type><mode>_mask): Ditto.
+ 	(vaesdec_<mode>): Ditto.
+ 	(vaesdeclast_<mode>): Ditto.
+ 	(vaesenc_<mode>): Ditto.
+ 	(vaesenclast_<mode>): Ditto.
+ 
+ 2026-06-17  Zhongyao Chen  <chen.zhongyao@zte.com.cn>
+ 
+ 	PR target/125215
+ 	* config/riscv/riscv-v.cc (expand_const_vector_interleaved_stepped_npatterns):
+ 	Remove hi/lo optimization and always use the merge fallback.
+ 
+ 2026-06-17  Alex Coplan  <alex.coplan@arm.com>
+ 
+ 	Backported from master:
+ 	2026-06-09  Alex Coplan  <alex.coplan@arm.com>
+ 
+ 	PR middle-end/125621
+ 	* expmed.cc (make_tree): Fix CONST_POLY_INT case to pass type
+ 	instead of t, move it to its own switch case.
+ 
+ 2026-06-17  Kishan Parmar  <kishan@linux.ibm.com>
+ 
+ 	Backported from master:
+ 	2026-05-22  Steve Markgraf  <steve@steve-m.de>
+ 
+ 	* config/rs6000/rs6000.h (TARGET_NO_LWSYNC): Add PROCESSOR_MPCCORE.
+ 
+ 2026-06-17  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	Backported from master:
+ 	2026-06-15  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	PR target/125795
+ 	* config/aarch64/aarch64-early-ra.cc (early_ra::allocate_colors):
+ 	Compute the allocated-FPR mask as
+ 	((1ULL << color->group->size) - 1) << best.
+ 
+ 2026-06-17  Carter Rennick  <carter.rennick@gmail.com>
+ 
+ 	Backported from master:
+ 	2026-04-24  Carter Rennick  <carter.rennick@gmail.com>
+ 
+ 	PR target/120144
+ 	* config/mips/mips.h (MAX_FIXED_MODE_SIZE): Remove.
+ 
+ 2026-06-17  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-06-10  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR ipa/125699
+ 	* ipa-param-manipulation.cc (ipa_param_body_adjustments::prepare_debug_expressions): Fix
+ 	lifetime issue with m_dead_ssa_debug_equiv usage.
+ 
+ 2026-06-17  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-06-13  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/125776
+ 	* tree-ssa-phiopt.cc (is_factor_profitable): An
+ 	usage in a debug stmt should be ignored.
+ 
+ 2026-06-17  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-06-14  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/125774
+ 	* gimple-range-fold.cc (fold_using_range::relation_fold_and_or): Use
+ 	relation_swap rather than relation_negate when the operands are exchanged.
+ 
+ 2026-06-17  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-03-12  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR rtl-optimization/123822
+ 	* simplify-rtx.cc (simplify_context::simplify_subreg): Check the
+ 	mode of the part to be non-VOIDmode before calling gen_rtx_SUBREG.
+ 
+ 2026-06-17  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-03-13  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR rtl-optimization/124454
+ 	* regcprop.cc (pass_cprop_hardreg::execute): If something
+ 	changed and non-call exceptions is on, call purge_all_dead_edges
+ 	and cleanup_cfg.
+ 
+ 2026-06-17  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-02-18  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR rtl-optimization/116053
+ 	* regcprop.cc (copyprop_hardreg_forward_1): Use delete_insn_and_edges
+ 	instead of delete_insn.
+ 
+ 2026-06-17  Andrew MacLeod  <amacleod@redhat.com>
+ 
+ 	PR tree-optimization/125501
+ 	* tree-ssa-dom.cc (set_global_ranges_from_unreachable_edges): Abort
+ 	if there are 2 SSA_NAMES on the branch condition.
+ 
+ 2026-06-16  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	Backported from master:
+ 	2026-05-12  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	PR tree-optimization/124151
+ 	* tree-sra.cc (build_user_friendly_ref_for_offset): Added parameters
+ 	CUR_SIZE and EXP_SIZE.  Added code passing the correct CUR_SIZE and
+ 	checking it against EXP_SIZE.  Removed unused code for the case when
+ 	EXP_TYPE was NULL_TREE.
+ 	(create_artificial_child_access): Adjusted the call to
+ 	build_user_friendly_ref_for_offset.
+ 	(propagate_subaccesses_from_rhs): Likewise.
+ 	(propagate_subaccesses_from_rhs): Removed a check that the size of
+ 	lchild is a multiple of BITS_PER_UNIT.
+ 	(propagate_subaccesses_from_lhs): Likewise.
+ 
+ 2026-06-12  Ramin Moussavi  <lordrasmus@gmail.com>
+ 
+ 	* config/microblaze/microblaze.h (DWARF_ALT_FRAME_RETURN_COLUMN):
+ 	Define.
+ 
+ 2026-06-12  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2026-06-11  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/125751
+ 	* config/avr/avr.cc (avr_out_fract): Fix too small sequence
+ 	lengths in avr_asm_len calls.
+ 
  2026-06-12  Release Manager
  
  	* GCC 15.3.0 released.
diff -Nrcpad gcc-15-20260612/gcc/DATESTAMP gcc-15-20260619/gcc/DATESTAMP
*** gcc-15-20260612/gcc/DATESTAMP	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/DATESTAMP	Fri Jun 19 22:32:05 2026
***************
*** 1 ****
! 20260612
--- 1 ----
! 20260619
diff -Nrcpad gcc-15-20260612/gcc/common/config/i386/cpuinfo.h gcc-15-20260619/gcc/common/config/i386/cpuinfo.h
*** gcc-15-20260612/gcc/common/config/i386/cpuinfo.h	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/common/config/i386/cpuinfo.h	Fri Jun 19 22:32:06 2026
*************** get_amd_cpu (struct __processor_model *c
*** 333,338 ****
--- 333,380 ----
    return cpu;
  }
  
+ /* Get the specific type of HYGON CPU and return HYGON CPU name.  Return
+    NULL for unknown HYGON CPU.  */
+ 
+ static inline const char *
+ get_hygon_cpu (struct __processor_model *cpu_model,
+ 	       struct __processor_model2 *cpu_model2,
+ 	       unsigned int *cpu_features2 __attribute__((unused)))
+ {
+   const char *cpu = NULL;
+   unsigned int family = cpu_model2->__cpu_family;
+   unsigned int model = cpu_model2->__cpu_model;
+ 
+   switch (family)
+     {
+     case 0x18:
+       cpu_model->__cpu_type = HYGONFAM18H;
+       if (model == 0x4)
+ 	{
+ 	  cpu = "c86-4g-m4";
+ 	  CHECK___builtin_cpu_is ("c86-4g-m4");
+ 	  cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M4;
+ 	}
+       else if (model == 0x6)
+ 	{
+ 	  cpu = "c86-4g-m6";
+ 	  CHECK___builtin_cpu_is ("c86-4g-m6");
+ 	  cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M6;
+ 	}
+       else if (model == 0x7)
+ 	{
+ 	  cpu = "c86-4g-m7";
+ 	  CHECK___builtin_cpu_is ("c86-4g-m7");
+ 	  cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M7;
+ 	}
+       break;
+     default:
+       break;
+     }
+ 
+   return cpu;
+ }
+ 
  /* Get the specific type of Intel CPU and return Intel CPU name.  Return
     NULL for unknown Intel CPU.  */
  
*************** cpu_indicator_init (struct __processor_m
*** 1210,1215 ****
--- 1252,1272 ----
      cpu_model->__cpu_vendor = VENDOR_CYRIX;
    else if (vendor == signature_NSC_ebx)
      cpu_model->__cpu_vendor = VENDOR_NSC;
+   else if (vendor == signature_HYGON_ebx)
+     {
+       /* Adjust model and family for HYGON CPUS.  */
+       if (family == 0x0f)
+ 	{
+ 	  family += extended_family;
+ 	  model += extended_model;
+ 	}
+       cpu_model2->__cpu_family = family;
+       cpu_model2->__cpu_model = model;
+ 
+       /* Get CPU type.  */
+       get_hygon_cpu (cpu_model, cpu_model2, cpu_features2);
+       cpu_model->__cpu_vendor = VENDOR_HYGON;
+     }
    else
      cpu_model->__cpu_vendor = VENDOR_OTHER;
  
diff -Nrcpad gcc-15-20260612/gcc/common/config/i386/i386-common.cc gcc-15-20260619/gcc/common/config/i386/i386-common.cc
*** gcc-15-20260612/gcc/common/config/i386/i386-common.cc	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/common/config/i386/i386-common.cc	Fri Jun 19 22:32:06 2026
*************** const char *const processor_names[] =
*** 2206,2212 ****
    "znver2",
    "znver3",
    "znver4",
!   "znver5"
  };
  
  /* Guarantee that the array is aligned with enum processor_type.  */
--- 2206,2215 ----
    "znver2",
    "znver3",
    "znver4",
!   "znver5",
!   "c86-4g-m4",
!   "c86-4g-m6",
!   "c86-4g-m7"
  };
  
  /* Guarantee that the array is aligned with enum processor_type.  */
*************** const pta processor_alias_table[] =
*** 2467,2472 ****
--- 2470,2484 ----
    {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
      PTA_BTVER2,
      M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},
+   {"c86-4g-m4", PROCESSOR_C86_4G_M4, CPU_C86_4G_M4,
+     PTA_C86_4G_M4,
+     M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M4), P_PROC_AVX2},
+   {"c86-4g-m6", PROCESSOR_C86_4G_M6, CPU_C86_4G_M6,
+     PTA_C86_4G_M6,
+     M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M6), P_PROC_AVX2},
+   {"c86-4g-m7", PROCESSOR_C86_4G_M7, CPU_C86_4G_M7,
+     PTA_C86_4G_M7,
+     M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M7), P_PROC_AVX512F},
  
    {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
      PTA_64BIT
*************** const pta processor_alias_table[] =
*** 2487,2496 ****
      M_CPU_SUBTYPE (AMDFAM10H_SHANGHAI), P_NONE},
    {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
      M_CPU_SUBTYPE (AMDFAM10H_ISTANBUL), P_NONE},
  };
  
  /* NB: processor_alias_table stops at the "generic" entry.  */
! unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 7;
  unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
  
  /* Provide valid option values for -march and -mtune options.  */
--- 2499,2512 ----
      M_CPU_SUBTYPE (AMDFAM10H_SHANGHAI), P_NONE},
    {"istanbul", PROCESSOR_GENERIC, CPU_GENERIC, 0,
      M_CPU_SUBTYPE (AMDFAM10H_ISTANBUL), P_NONE},
+   {"hygon", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+     M_VENDOR (VENDOR_HYGON), P_NONE},
+   {"hygonfam18h", PROCESSOR_GENERIC, CPU_GENERIC, 0,
+     M_CPU_TYPE (HYGONFAM18H), P_NONE},
  };
  
  /* NB: processor_alias_table stops at the "generic" entry.  */
! unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 9;
  unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);
  
  /* Provide valid option values for -march and -mtune options.  */
diff -Nrcpad gcc-15-20260612/gcc/common/config/i386/i386-cpuinfo.h gcc-15-20260619/gcc/common/config/i386/i386-cpuinfo.h
*** gcc-15-20260612/gcc/common/config/i386/i386-cpuinfo.h	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/common/config/i386/i386-cpuinfo.h	Fri Jun 19 22:32:06 2026
*************** enum processor_vendor
*** 30,35 ****
--- 30,36 ----
    VENDOR_INTEL = 1,
    VENDOR_AMD,
    VENDOR_ZHAOXIN,
+   VENDOR_HYGON,
    VENDOR_OTHER,
    VENDOR_CENTAUR,
    VENDOR_CYRIX,
*************** enum processor_types
*** 62,67 ****
--- 63,69 ----
    INTEL_GRANDRIDGE,
    INTEL_CLEARWATERFOREST,
    AMDFAM1AH,
+   HYGONFAM18H,
    CPU_TYPE_MAX,
    BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX
  };
*************** enum processor_subtypes
*** 106,111 ****
--- 108,116 ----
    AMDFAM1AH_ZNVER5,
    ZHAOXIN_FAM7H_SHIJIDADAO,
    INTEL_COREI7_DIAMONDRAPIDS,
+   HYGONFAM18H_C86_4G_M4,
+   HYGONFAM18H_C86_4G_M6,
+   HYGONFAM18H_C86_4G_M7,
    CPU_SUBTYPE_MAX
  };
  
diff -Nrcpad gcc-15-20260612/gcc/config/aarch64/aarch64-early-ra.cc gcc-15-20260619/gcc/config/aarch64/aarch64-early-ra.cc
*** gcc-15-20260612/gcc/config/aarch64/aarch64-early-ra.cc	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/aarch64/aarch64-early-ra.cc	Fri Jun 19 22:32:06 2026
*************** early_ra::allocate_colors ()
*** 3038,3044 ****
        if (dump_file && (dump_flags & TDF_DETAILS))
  	fprintf (dump_file, "  Allocating [v%d:v%d] to color %d\n",
  		 best, best + color->group->size - 1, color->id);
!       m_allocated_fprs |= ((1U << color->group->size) - 1) << best;
      }
  }
  
--- 3038,3050 ----
        if (dump_file && (dump_flags & TDF_DETAILS))
  	fprintf (dump_file, "  Allocating [v%d:v%d] to color %d\n",
  		 best, best + color->group->size - 1, color->id);
!       // Mark the COLOR's FPRs as allocated.  A full-width color can have
!       // size == 32, so shift a wide enough value: "1U << 32" is undefined,
!       // as is "1UL << 32" on hosts with 32-bit long.  unsigned long long is
!       // at least 64 bits everywhere.  best + size <= 32 (from the candidate
!       // search) keeps the result within the 32-bit mask.
!       gcc_assert (best + color->group->size <= 32);
!       m_allocated_fprs |= ((1ULL << color->group->size) - 1) << best;
      }
  }
  
diff -Nrcpad gcc-15-20260612/gcc/config/i386/c86-4g-m7.md gcc-15-20260619/gcc/config/i386/c86-4g-m7.md
*** gcc-15-20260612/gcc/config/i386/c86-4g-m7.md	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/config/i386/c86-4g-m7.md	Fri Jun 19 22:32:06 2026
***************
*** 0 ****
--- 1,2063 ----
+ ;; Copyright (C) 2026 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+ ;;
+ ;; GCC is free software; you can redistribute it and/or modify
+ ;; it under the terms of the GNU General Public License as published by
+ ;; the Free Software Foundation; either version 3, or (at your option)
+ ;; any later version.
+ ;;
+ ;; GCC is distributed in the hope that it will be useful,
+ ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+ ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ ;; GNU General Public License for more details.
+ ;;
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING3.  If not see
+ ;; <http://www.gnu.org/licenses/>.
+ ;;
+ 
+ ;; HYGON c86-4g-m7 Scheduling
+ ;; Modeling automatons for decoders, integer execution pipes,
+ ;; AGU pipes, branch, floating point execution, fp store units,
+ ;; integer and floating point dividers.  Split fpu1 and fpu3
+ ;; into their own automata to keep these units independent
+ ;; without increasing the main c86_4g_m7_fpu state space.
+ (define_automaton "c86_4g_m7, c86_4g_m7_ieu, c86_4g_m7_agu, c86_4g_m7_fpu02, c86_4g_m7_fpu13, c86_4g_m7_idiv, c86_4g_m7_fdiv")
+ 
+ ;; Decoders unit has 4 decoders and all of them can decode fast path
+ ;; and vector type instructions.
+ (define_cpu_unit "c86-4g-m7-decode0" "c86_4g_m7")
+ (define_cpu_unit "c86-4g-m7-decode1" "c86_4g_m7")
+ (define_cpu_unit "c86-4g-m7-decode2" "c86_4g_m7")
+ (define_cpu_unit "c86-4g-m7-decode3" "c86_4g_m7")
+ 
+ ;; Currently blocking all decoders for vector path instructions as
+ ;; they are dispatched separetely as microcode sequence.
+ (define_reservation "c86-4g-m7-vector" "c86-4g-m7-decode0+c86-4g-m7-decode1+c86-4g-m7-decode2+c86-4g-m7-decode3")
+ 
+ ;; Direct instructions can be issued to any of the four decoders.
+ (define_reservation "c86-4g-m7-direct" "c86-4g-m7-decode0|c86-4g-m7-decode1|c86-4g-m7-decode2|c86-4g-m7-decode3")
+ 
+ ;; Fix me: Need to revisit this later to simulate fast path double behavior.
+ (define_reservation "c86-4g-m7-double" "c86-4g-m7-direct")
+ 
+ ;; Integer unit 4 ALU pipes.
+ (define_cpu_unit "c86-4g-m7-ieu0" "c86_4g_m7_ieu")
+ (define_cpu_unit "c86-4g-m7-ieu1" "c86_4g_m7_ieu")
+ (define_cpu_unit "c86-4g-m7-ieu2" "c86_4g_m7_ieu")
+ (define_cpu_unit "c86-4g-m7-ieu3" "c86_4g_m7_ieu")
+ 
+ ;; One separated integer divider.
+ (define_cpu_unit "c86-4g-m7-idiv" "c86_4g_m7_idiv")
+ 
+ ;; c86-4g-m7 has an additional branch unit.
+ (define_cpu_unit "c86-4g-m7-bru0" "c86_4g_m7_ieu")
+ (define_reservation "c86-4g-m7-ieu" "c86-4g-m7-ieu0|c86-4g-m7-ieu1|c86-4g-m7-ieu2|c86-4g-m7-ieu3")
+ 
+ ;; 3 AGU pipes in c86-4g-m7
+ (define_cpu_unit "c86-4g-m7-agu0" "c86_4g_m7_agu")
+ (define_cpu_unit "c86-4g-m7-agu1" "c86_4g_m7_agu")
+ (define_cpu_unit "c86-4g-m7-agu2" "c86_4g_m7_agu")
+ (define_reservation "c86-4g-m7-agu-reserve" "c86-4g-m7-agu0|c86-4g-m7-agu1|c86-4g-m7-agu2")
+ 
+ ;; Load is 4 cycles.  We do not model reservation of load unit.
+ (define_reservation "c86-4g-m7-load" "c86-4g-m7-agu-reserve")
+ (define_reservation "c86-4g-m7-store" "c86-4g-m7-agu-reserve")
+ 
+ ;; vectorpath (microcoded) instructions are single issue instructions.
+ ;; So, they occupy all the integer units.
+ (define_reservation "c86-4g-m7-ivector" "c86-4g-m7-ieu0+c86-4g-m7-ieu1
+ 					 +c86-4g-m7-ieu2+c86-4g-m7-ieu3+c86-4g-m7-bru0
+ 					 +c86-4g-m7-agu0+c86-4g-m7-agu1+c86-4g-m7-agu2")
+ 
+ ;; Floating point unit 4 FP pipes.
+ (define_cpu_unit "c86-4g-m7-fpu0" "c86_4g_m7_fpu02")
+ (define_cpu_unit "c86-4g-m7-fpu1" "c86_4g_m7_fpu13")
+ (define_cpu_unit "c86-4g-m7-fpu2" "c86_4g_m7_fpu02")
+ (define_cpu_unit "c86-4g-m7-fpu3" "c86_4g_m7_fpu13")
+ 
+ (define_reservation "c86-4g-m7-fpu" "c86-4g-m7-fpu0|c86-4g-m7-fpu1|c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ (define_reservation "c86-4g-m7-fpu_0_1" "c86-4g-m7-fpu0|c86-4g-m7-fpu1")
+ (define_reservation "c86-4g-m7-fpu_0_2" "c86-4g-m7-fpu0|c86-4g-m7-fpu2")
+ (define_reservation "c86-4g-m7-fpu_0_2x2" "c86-4g-m7-fpu0*2|c86-4g-m7-fpu2*2")
+ (define_reservation "c86-4g-m7-fpu_0_2x4" "c86-4g-m7-fpu0*4|c86-4g-m7-fpu2*4")
+ (define_reservation "c86-4g-m7-fpu_0_3" "c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ (define_reservation "c86-4g-m7-fpu_1_3" "c86-4g-m7-fpu1|c86-4g-m7-fpu3")
+ (define_reservation "c86-4g-m7-fpu_1_3x2" "c86-4g-m7-fpu1*2|c86-4g-m7-fpu3*2")
+ (define_reservation "c86-4g-m7-fpu_1_3x3" "c86-4g-m7-fpu1*3|c86-4g-m7-fpu3*3")
+ (define_reservation "c86-4g-m7-fpu_1_3x6" "c86-4g-m7-fpu1*6|c86-4g-m7-fpu3*6")
+ (define_reservation "c86-4g-m7-fpux2" "c86-4g-m7-fpu0*2|c86-4g-m7-fpu1*2|c86-4g-m7-fpu2*2|c86-4g-m7-fpu3*2")
+ (define_reservation "c86-4g-m7-fpux4" "c86-4g-m7-fpu0*4|c86-4g-m7-fpu1*4|c86-4g-m7-fpu2*4|c86-4g-m7-fpu3*4")
+ (define_reservation "c86-4g-m7-fpux8" "c86-4g-m7-fpu0*8|c86-4g-m7-fpu1*8|c86-4g-m7-fpu2*8|c86-4g-m7-fpu3*8")
+ (define_reservation "c86-4g-m7-fpux6" "c86-4g-m7-fpu0*6|c86-4g-m7-fpu1*6|c86-4g-m7-fpu2*6|c86-4g-m7-fpu3*6")
+ (define_reservation "c86-4g-m7-fpux16" "c86-4g-m7-fpu0*16|c86-4g-m7-fpu1*16|c86-4g-m7-fpu2*16|c86-4g-m7-fpu3*16")
+ (define_reservation "c86-4g-m7-fvector" "c86-4g-m7-fpu0+c86-4g-m7-fpu1
+ 					 +c86-4g-m7-fpu2+c86-4g-m7-fpu3
+ 					 +c86-4g-m7-agu0+c86-4g-m7-agu1+c86-4g-m7-agu2")
+ 
+ ;; Two FP dividers.
+ (define_cpu_unit "c86-4g-m7-fdiv1" "c86_4g_m7_fdiv")
+ (define_cpu_unit "c86-4g-m7-fdiv3" "c86_4g_m7_fdiv")
+ 
+ (define_reservation "c86-4g-m7-fp1fdiv1x4" "(c86-4g-m7-fpu1+c86-4g-m7-fdiv1)*4")
+ (define_reservation "c86-4g-m7-fp3fdiv3x4" "(c86-4g-m7-fpu3+c86-4g-m7-fdiv3)*4")
+ (define_reservation "c86-4g-m7-fdiv13" "(c86-4g-m7-fdiv1+c86-4g-m7-fdiv3)")
+ (define_reservation "c86-4g-m7-fp13div13" "(c86-4g-m7-fpu1+c86-4g-m7-fpu3+c86-4g-m7-fdiv1+c86-4g-m7-fdiv3)")
+ (define_reservation "c86-4g-m7-fp13div13x4" "c86-4g-m7-fp13div13*4")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x8" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*8)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*8)")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x9" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*9)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*9)")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x11" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*11)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*11)")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x15" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*15)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*15)")
+ (define_reservation "c86-4g-m7-fp1div1_fp3div3_x4x18" "(c86-4g-m7-fp1fdiv1x4,c86-4g-m7-fdiv1*18)|(c86-4g-m7-fp3fdiv3x4,c86-4g-m7-fdiv3*18)")
+ 
+ ;; IMOV/IMOVX
+ (define_insn_reservation "c86_4g_m7_imov_xchg" 1
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imov")
+ 				  (and (eq_attr "c86_decode" "vector")
+ 				       (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct")
+ 
+ (define_insn_reservation "c86_4g_m7_imov_xchg_load" 5
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imov")
+ 				  (and (eq_attr "c86_decode" "vector")
+ 				       (eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load")
+ 
+ (define_insn_reservation "c86_4g_m7_imovx_cwde" 2
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imovx")
+ 				  (and (eq_attr "c86_decode" "double")
+ 				       (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_imov" 1
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imov,imovx")
+ 				  (and (eq_attr "c86_decode" "direct")
+ 				       (eq_attr "memory" "none"))))
+ 	     "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_imov_load" 5
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imov,imovx")
+ 				  (and (eq_attr "c86_decode" "!vector")
+ 				       (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_imov_store" 1
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imov,imovx")
+ 				  (and (eq_attr "c86_decode" "!vector")
+ 				       (eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu")
+ 
+ ;; PUSH
+ (define_insn_reservation "c86_4g_m7_push" 1
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "push,sse")
+ 				  (eq_attr "memory" "store")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_push_mem" 5
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 				 (and (eq_attr "type" "push")
+ 				  (eq_attr "memory" "both")))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store")
+ 
+ ;; POP
+ (define_insn_reservation "c86_4g_m7_pop" 4
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "pop")
+ 				  (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load")
+ 
+ (define_insn_reservation "c86_4g_m7_pop_mem" 5
+ 	    (and (eq_attr "cpu" "c86_4g_m7")
+ 		 (and (eq_attr "type" "pop")
+ 		  (eq_attr "memory" "both")))
+ 	     "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store")
+ 
+ ;; IMUL/IMULX
+ (define_insn_reservation "c86_4g_m7_imul" 3
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imul,imulx")
+ 				  (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu1")
+ 
+ (define_insn_reservation "c86_4g_m7_imul_load" 7
+ 			(and (eq_attr "cpu" "c86_4g_m7")
+ 			     (and (eq_attr "type" "imul")
+ 				  (eq_attr "memory" "!none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu1")
+ 
+ ;; IDIV
+ (define_insn_reservation "c86_4g_m7_idiv" 7
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "!QI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*7")
+ 
+ (define_insn_reservation "c86_4g_m7_idiv_QI" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "QI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu3,c86-4g-m7-idiv*6")
+ 
+ (define_insn_reservation "c86_4g_m7_idiv_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "!QI")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*7")
+ 
+ (define_insn_reservation "c86_4g_m7_idiv_QI_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "QI")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3,c86-4g-m7-idiv*6")
+ 
+ ;; Integer/genaral Instructions
+ (define_insn_reservation "c86_4g_m7_insn" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu,negnot,rotate1,ishift1,test,incdec,icmp,
+ 						    rotate,rotatex,ishift,ishiftx,icmov")
+ 				   (eq_attr "memory" "none,unknown")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_insn_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu,incdec,icmp,test,ishift,
+ 						    ishiftx,icmov,rotate,rotatex")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_insn_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ishift1,rotate1,rotate,incdec,
+ 						    alu,icmov,ishift,negnot,alu1")
+ 				   (eq_attr "memory" "store")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_insn2_store" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "icmp")
+ 				   (eq_attr "memory" "store")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_insn_both" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu,negnot,rotate1,ishift1,incdec,rotate,
+ 						    rotatex,ishift,ishiftx,icmov")
+ 				   (eq_attr "memory" "both")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_setcc" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "setcc")
+ 				   (eq_attr "memory" "none,unknown")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
+ 
+ (define_insn_reservation "c86_4g_m7_setcc_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "setcc")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
+ 
+ (define_insn_reservation "c86_4g_m7_setcc_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "setcc")
+ 				   (eq_attr "memory" "store")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu0|c86-4g-m7-ieu3")
+ 
+ ;; ALU1
+ (define_insn_reservation "c86_4g_m7_alu1_double" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "double")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_double_load" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "double")
+ 					(eq_attr "memory" "both"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_vector" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-ivector*3")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_vector_load" 7
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 					(eq_attr "memory" "both"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ivector*3")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_direct" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "direct")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ (define_insn_reservation "c86_4g_m7_alu1_direct_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "alu1")
+ 				   (and (eq_attr "c86_decode" "direct")
+ 					(eq_attr "memory" "both"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu")
+ 
+ ;; CALL/CALLV
+ (define_insn_reservation "c86_4g_m7_call" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (eq_attr "type" "call,callv"))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu0|c86-4g-m7-bru0,c86-4g-m7-store")
+ 
+ ;; IBR
+ (define_insn_reservation "c86_4g_m7_branch" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ibr")
+ 				   (eq_attr "memory" "none")))
+ 			  "c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-bru0")
+ 
+ (define_insn_reservation "c86_4g_m7_branch_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ibr")
+ 				   (eq_attr "memory" "load")))
+ 			  "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-bru0")
+ 
+ ;; LEA
+ (define_insn_reservation "c86_4g_m7_lea" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (eq_attr "type" "lea"))
+ 			 "c86-4g-m7-direct,c86-4g-m7-ieu")
+ 
+ ;; LEAVE
+ (define_insn_reservation "c86_4g_m7_leave" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (eq_attr "type" "leave"))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu,c86-4g-m7-store")
+ 
+ ;; STR
+ (define_insn_reservation "c86_4g_m7_str" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "str")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-vector,c86-4g-m7-ivector*3")
+ 
+ (define_insn_reservation "c86_4g_m7_str_load" 7
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "str")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*3")
+ 
+ 
+ (define_insn_reservation "c86_4g_m7_ieu_vector" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "other,multi")
+ 				   (and (eq_attr "unit" "!i387")
+ 				       (eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-ivector*5")
+ 
+ (define_insn_reservation "c86_4g_m7_ieu_vector_load" 9
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "other,multi")
+ 				   (and (eq_attr "unit" "!i387")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*5")
+ 
+ ;; SSEINS
+ (define_insn_reservation "c86_4g_m7_sse_insertimm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseins")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "length_immediate" "2"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_3,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_insert" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseins")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "length_immediate" "!2"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1*2")
+ 
+ ;; FCMOV
+ (define_insn_reservation "c86_4g_m7_fp_cmov" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (eq_attr "type" "fcmov"))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fvector*3")
+ 
+ ;; FLD
+ (define_insn_reservation "c86_4g_m7_fp_mov_direct_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ ;; FST
+ (define_insn_reservation "c86_4g_m7_fp_mov_direct_store" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1,c86-4g-m7-store")
+ 
+ ;; FILD
+ (define_insn_reservation "c86_4g_m7_fp_mov_double_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ ;; FIST
+ (define_insn_reservation "c86_4g_m7_fp_mov_double_store" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-store")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_mov_direct" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
+ 
+ ;; FSQRT
+ (define_insn_reservation "c86_4g_m7_fp_sqrt" 22
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fpspc")
+ 				   (eq_attr "c86_attr" "sqrt")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x18")
+ 
+ ;; FPSPC
+ (define_insn_reservation "c86_4g_m7_fp_spc_direct" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fpspc")
+ 				   (and (eq_attr "c86_decode" "direct")
+ 				    (and (eq_attr "c86_attr" "other")
+ 					 (eq_attr "memory" "store")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_spc" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fpspc")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fvector*6")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_op_mul" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fop,fmul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_op_mul_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fop,fmul")
+ 				   (and (eq_attr "fp_int_src" "false")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_op_imul_load" 16
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fmul")
+ 				   (and (eq_attr "fp_int_src" "true")
+ 					(eq_attr "memory" "!none"))))
+ 			"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu_0_2")
+ 
+ ;; FDIV
+ (define_insn_reservation "c86_4g_m7_fp_div" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x11")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_div_load" 22
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (and (eq_attr "fp_int_src" "false")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x11")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_idiv_load" 26
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (and (eq_attr "fp_int_src" "true")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1*4,c86-4g-m7-fp1div1_fp3div3_x4x11")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_fsgn" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (eq_attr "type" "fsgn"))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ ;; FCMP
+ (define_insn_reservation "c86_4g_m7_fp_fcmp" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fcmp")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu0,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_fp_fcmp_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "fcmp")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu1")
+ 
+ ;; MMX
+ (define_insn_reservation "c86_4g_m7_fp_mmx" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (eq_attr "type" "mmx"))
+ 			 "c86-4g-m7-direct")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_add_cmp" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxadd,mmxcmp")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_add_cmp_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxadd,mmxcmp")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_cvt" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxcvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_cvt_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxcvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift_avg" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "avg")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift_avg_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "avg")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ ;; SADBW
+ (define_insn_reservation "c86_4g_m7_mmx_shift_sadbw" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_shift_sadbw_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mov" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxmov")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mov_store" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxmov")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mov_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxmov")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxmul")
+ 				   (eq_attr "memory" "none")))
+ 			  "c86-4g-m7-direct,c86-4g-m7-fpu0")
+ 
+ (define_insn_reservation "c86_4g_m7_mmx_mul_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mmxmul")
+ 				   (eq_attr "memory" "load")))
+ 			  "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
+ 
+ ;; PINSR
+ (define_insn_reservation "c86_4g_m7_sse_pinsr_reg" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,mmxcvt")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-ieu2,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_pinsr_reg_load" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,mmxcvt")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_vpinsr_reg" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 				     (and (eq_attr "prefix" "!orig")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_vpinsr_reg_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 				     (and (eq_attr "prefix" "!orig")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ ;; PERM
+ (define_insn_reservation "c86_4g_m7_avx512_perm_xmm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (ior (and (eq_attr "c86_attr" "perm2")
+ 						  (eq_attr "mode" "V4SF,V2DF,TI"))
+ 					     (and (eq_attr "c86_attr" "perm")
+ 						  (eq_attr "mode" "V8SF,V4DF,TI,OI")))
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_perm_xmm_opload" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (ior (and (eq_attr "c86_attr" "perm2")
+ 						  (eq_attr "mode" "V4SF,V2DF,TI"))
+ 					     (and (eq_attr "c86_attr" "perm")
+ 						  (eq_attr "mode" "V8SF,V4DF,TI,OI")))
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_permi2_ymm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm2")
+ 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_permi2_zmm" 16
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm2")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux16")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_permi2_ymm_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm2")
+ 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_permi2_zmm_load" 23
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm2")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux16")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (match_operand 2 "immediate_operand")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpux4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_imm_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (match_operand 2 "immediate_operand")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpux4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_perm_zmm_noimm" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (match_operand 2 "nonimmediate_operand")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux8")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_perm_zmm_noimm_load" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "perm")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (match_operand 2 "nonimmediate_operand")
+ 					 (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux8")
+ 
+ ;; VINSERT
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_ymm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 				     (and (eq_attr "prefix" "evex")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_ymem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 				     (and (eq_attr "prefix" "evex")
+ 					  (eq_attr "memory" "load,both"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmm" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==16")
+ 					 (match_operand 2 "register_operand"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2x4,c86-4g-m7-fpu_0_2x4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_zxmem" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==16")
+ 					  (match_operand 2 "memory_operand"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4,c86-4g-m7-fpu_0_2x4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_zymm" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==32")
+ 					  (match_operand 2 "register_operand"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_insertx_zymem" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				    (and (match_test "GET_MODE_SIZE (GET_MODE (operands[2]))==32")
+ 					  (match_operand 2 "memory_operand"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_insertx_ymm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				     (and (eq_attr "prefix" "!evex")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0*2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_insertx_ymem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "insertx")
+ 				     (and (eq_attr "prefix" "!evex")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0*2")
+ 
+ ;; SHUF/MULTISHIFTQB
+ (define_insn_reservation "c86_4g_m7_avx512_shuf_xymm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "shufx")
+ 				     (and (not (eq_attr "mode" "V8DF,V16SF,XI"))
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_shuf_zmm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "shufx")
+ 				     (and (eq_attr "mode" "V8DF,V16SF,XI")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2x4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_shuf_xymem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "shufx")
+ 				     (and (not (eq_attr "mode" "V8DF,V16SF,XI"))
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_shuf_zmem" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "shufx")
+ 				     (and (eq_attr "mode" "V8DF,V16SF,XI")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4")
+ 
+ ;; SSELOGIC
+ (define_insn_reservation "c86_4g_m7_sselogic_xymm" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "sselogic")
+ 					 (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_sselogic_xymm_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1")
+ 				   (and (eq_attr "c86_attr" "sselogic")
+ 					 (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ ;; CMPESTR
+ (define_insn_reservation "c86_4g_m7_avx512_cmpestr" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "cmpestr")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux6")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_cmpestr_load" 13
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "cmpestr")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux6")
+ 
+ ;; SSELOG
+ (define_insn_reservation "c86_4g_m7_avx512_log" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_log_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog,sselog1,sseshuf,sseshuf1")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					 (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ ;; SSELOG1
+ ;; VDBPSADBW
+ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "mode" "OI,TI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_xymem" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "mode" "OI,TI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmm" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "mode" "XI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vdbpsadbw_zmem" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "mode" "XI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")
+ 
+ ;; ABS
+ (define_insn_reservation "c86_4g_m7_avx512_abs" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1,sse")
+ 				   (and (eq_attr "c86_attr" "abs")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_abs_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1,sse")
+ 				   (and (eq_attr "c86_attr" "abs")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "load,both")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ ;; SIGN
+ (define_insn_reservation "c86_4g_m7_avx_sign" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sign")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sign_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sign")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ 
+ ;; BLEND/ABS/AES
+ (define_insn_reservation "c86_4g_m7_avx_blend" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "abs,blend,aes")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_blend_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "abs,blend,aes")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_aes" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1,ssecvt,sse")
+ 				   (and (eq_attr "c86_attr" "aes")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_aes_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1,ssecvt,sse")
+ 				   (and (eq_attr "c86_attr" "aes")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_aes" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "aes")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_aes_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "aes")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu1")
+ 
+ ;; EXTR
+ (define_insn_reservation "c86_4g_m7_extr" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1,sselog,mmxcvt")
+ 				   (and (eq_attr "c86_attr" "extr")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_extr_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sselog1,sselog,mmxcvt")
+ 				   (and (eq_attr "c86_attr" "extr")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-store,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+ 
+ ;; SSECOMI
+ (define_insn_reservation "c86_4g_m7_avx_ssecomi_comi" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecomi")
+ 				   (and (eq_attr "prefix_extra" "0")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecomi_comi_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecomi")
+ 				   (and (eq_attr "prefix_extra" "0")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecomi_test" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecomi")
+ 				   (and (eq_attr "prefix_extra" "1")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecomi_test_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecomi")
+ 				   (and (eq_attr "prefix_extra" "1")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+ 
+ ;; SSEIMUL
+ (define_insn_reservation "c86_4g_m7_avx512_imul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (and (eq_attr "prefix" "evex")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_imul_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (and (eq_attr "prefix" "evex")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_imul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (and (eq_attr "prefix" "!evex")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_imul_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (and (eq_attr "prefix" "!evex")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ 
+ ;; SSEMOV
+ (define_insn_reservation "c86_4g_m7_avx512_mov_vmov" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov,sseiadd")
+ 				    (and (eq_attr "c86_attr" "other,blend,maxmin")
+ 					 (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mov_vmov_store" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					 (eq_attr "memory" "store"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mov_vmov_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov,sseiadd")
+ 				   (and (eq_attr "c86_attr" "other,blend,maxmin")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "OI,V8SF,V4DF")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_y_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov,sselog1")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "OI,V8SF,V4DF")
+ 					  (eq_attr "memory" "load,both"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				     (and (eq_attr "mode" "XI")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2x4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_z_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				     (and (eq_attr "mode" "XI")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_x" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "TI,SI")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_vpmovx_x_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "TI,SI")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_vpmovx_xx_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "vpmovx")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load,both")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2")
+ 
+ ;; EXPAND
+ (define_insn_reservation "c86_4g_m7_avx512_expand" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "expand,compress")
+ 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_expand_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "expand,compress")
+ 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_expand_z" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "expand,compress")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_expand_z_load" 17
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "expand,compress")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu3,c86-4g-m7-fpu_0_3")
+ 
+ ;; MOVNT
+ (define_insn_reservation "c86_4g_m7_avx512_movnt_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "movnt")
+ 				   (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					(eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_movnt_store" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "movnt")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "store")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1*2")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_movnt_store" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov,mmxmov")
+ 				   (and (eq_attr "c86_attr" "movnt")
+ 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ 					 (eq_attr "memory" "!none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_movnt" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "movnt")
+ 				    (and (not (eq_attr "mode" "XI,V16SF,V8DF"))
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ ;; BLENDV
+ (define_insn_reservation "c86_4g_m7_avx512_blendv" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "blendv")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_blendv_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov")
+ 				   (and (eq_attr "c86_attr" "blendv")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ ;; SSEMOV2
+ (define_insn_reservation "c86_4g_m7_sse_mov2" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov2")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_mov2_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemov2")
+ 				   (eq_attr "memory" "!none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ ;; SSEISHFT
+ (define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (and (eq_attr "prefix_extra" "1")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseishft_aligr_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (and (eq_attr "prefix_extra" "1")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (and (eq_attr "prefix_extra" "!1")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseishft_vshift_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (and (eq_attr "prefix_extra" "!1")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ 
+ ;; SSEADD
+ (define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_xy" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "evex")
+ 				      (and (eq_attr "memory" "none")
+ 					   (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseadd_maxmin_xy_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "evex")
+ 				      (ior (eq_attr "memory" "load")
+ 					   (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "vex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseadd_maxmin_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "vex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseadd_maxmin_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sse")
+ 				   (and (eq_attr "c86_attr" "maxmin")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ 
+ ;; SUB/ADD
+ (define_insn_reservation "c86_4g_m7_avx512_sseadd_xy" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseadd_xy_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					 (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ ;; HADD/HSUB
+ (define_insn_reservation "c86_4g_m7_avx_sseadd_hplus" 7
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sseadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-vector")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseadd_hplus_load" 14
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseadd,sseadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load")
+ 
+ ;; SSEIADD
+ (define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw,madd")
+ 					(and (ior (eq_attr "prefix" "evex")
+ 						  (eq_attr "mode" "XI"))
+ 					     (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseiadd_madd_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw,madd")
+ 					(and (ior (eq_attr "prefix" "evex")
+ 						  (eq_attr "mode" "XI"))
+ 					     (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "prefix" "vex,maybe_evex")
+ 				     (and (eq_attr "mode" "TI,OI")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseiadd_sadbw_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "prefix" "vex,maybe_evex")
+ 				     (and (eq_attr "mode" "TI,OI")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_sadbw_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "madd")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu0")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_madd_mem" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "madd")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0")
+ 
+ ;; AVG
+ (define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "avg")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sseiadd_avg_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "avg")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd,sseiadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 				    (and (eq_attr "prefix" "vex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sseiadd_hplus_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd,sseiadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 				    (and (eq_attr "prefix" "vex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd,sseiadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 				    (and (eq_attr "prefix" "orig")
+ 				     (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpux2")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_sseiadd_hplus_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sseiadd,sseiadd1")
+ 				   (and (eq_attr "c86_attr" "hplus")
+ 				    (and (eq_attr "prefix" "orig")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpux2")
+ 
+ ;; SSEMUL
+ (define_insn_reservation "c86_4g_m7_avx512_ssemul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssemul_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ ;; SSEDIV
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_x" 13
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x8")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_xmem" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x8")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_y" 13
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "V8SF,V4DF")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*8")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_ymem" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "V8SF,V4DF")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*8")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_z" 24
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "V16SF,V8DF")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*20")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssediv_zmem" 31
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (and (eq_attr "mode" "V16SF,V8DF")
+ 					 (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*20")
+ 
+ ;; SSECMP
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "V2DF,V4DF,V8SF,V4SF,SF,DF")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_z" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_z_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				    (and (eq_attr "mode" "V16SF,V8DF,XI")
+ 				     (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "TI,OI")
+ 				     (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "TI,OI")
+ 				     (and (eq_attr "c86_attr" "other")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "XI")
+ 				     (and (eq_attr "c86_attr" "other,ptest")
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_vp_z_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "mode" "XI")
+ 				     (and (eq_attr "c86_attr" "other,ptest")
+ 					  (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecmp_vp" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "!evex")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecmp_vp_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (and (eq_attr "prefix" "!evex")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu")
+ 
+ ;; VPTEST
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				    (and (eq_attr "mode" "TI,OI")
+ 				     (and (eq_attr "c86_attr" "ptest")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecmp_test_load" 13
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecmp")
+ 				    (and (eq_attr "mode" "TI,OI")
+ 				     (and (eq_attr "c86_attr" "ptest")
+ 					  (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fpu_1_3")
+ 
+ ;; SSECVT
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 				    (and (eq_attr "prefix" "evex")
+ 				     (and (eq_attr "mode" "TI,V4SF,V2DF,OI,V8SF,V4DF")
+ 				      (and (not (ior (match_operand:V8DI 1 "register_operand")
+ 						     (match_operand:V8DF 1 "register_operand")))
+ 					   (eq_attr "memory" "none")))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_xy_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "prefix" "evex")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "mode" "TI,V4SF,V2DF,OI,V8SF,V4DF")
+ 				      (and (not (ior (match_operand:V8DI 1 "register_operand")
+ 						     (match_operand:V8DF 1 "register_operand")))
+ 					   (eq_attr "memory" "!none")))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "mode" "OI,V8SF,V4DF")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (ior (match_operand:V8DI 1 "register_operand")
+ 					       (match_operand:V8DF 1 "register_operand"))
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_y_z_load" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "mode" "OI,V8SF,V4DF")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (ior (match_operand:V8DI 1 "memory_operand")
+ 					       (match_operand:V8DF 1 "memory_operand"))
+ 					  (eq_attr "memory" "!none"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_z" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_ssecvt_z_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 				    (and (eq_attr "mode" "XI,V16SF,V8DF")
+ 					 (eq_attr "memory" "!none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecvt" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "prefix" "!evex")
+ 				     (and (eq_attr "mmx_isa" "base")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_ssecvt_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "prefix" "!evex")
+ 				    (and (eq_attr "mmx_isa" "base")
+ 					 (eq_attr "memory" "!none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3")
+ 
+ ;; CVTPI
+ (define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "mode" "SF,DI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_ssecvt_pspi_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "mode" "SF,DI")
+ 					 (eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_ssecvt_pi" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				    (and (not (eq_attr "mode" "SF,DI"))
+ 				     (and (eq_attr "mmx_isa" "native")
+ 					  (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_sse_ssecvt_pi_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (not (eq_attr "mode" "SF,DI"))
+ 				    (and (eq_attr "mmx_isa" "native")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1")
+ 
+ ;; SSEMULADD
+ (define_insn_reservation "c86_4g_m7_avx512_muladd" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemuladd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_muladd_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemuladd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_muladd_madd" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemuladd,sse")
+ 				   (and (eq_attr "c86_attr" "madd,rcp")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_muladd_madd_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "ssemuladd,sse")
+ 				   (and (eq_attr "c86_attr" "madd,rcp")
+ 				    (and (eq_attr "prefix" "evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ ;; SSE
+ (define_insn_reservation "c86_4g_m7_avx512_sse_range" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "!1")
+ 				      (and (eq_attr "prefix" "evex")
+ 				       (and (eq_attr "c86_decode" "direct")
+ 					   (eq_attr "memory" "none")))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_range_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "!1")
+ 				      (and (eq_attr "c86_decode" "direct")
+ 				       (and (eq_attr "prefix" "evex")
+ 					    (eq_attr "memory" "load")))))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "TI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_x_load" 9
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "TI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x2")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "OI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_y_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "OI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "XI")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3x6")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_conflict_z_load" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_decode" "vector")
+ 				    (and (eq_attr "mode" "XI")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3x6")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_class" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_attr" "other")
+ 				    (and (eq_attr "length_immediate" "1")
+ 				     (and (not (eq_attr "mode" "V32HF,V16SF,V8DF"))
+ 					  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_class_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "1")
+ 				      (and (not (eq_attr "mode" "V32HF,V16SF,V8DF"))
+ 					   (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_class_z" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "1")
+ 				      (and (eq_attr "mode" "V32HF,V16SF,V8DF")
+ 					   (eq_attr "memory" "none"))))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_class_z_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				    (and (eq_attr "c86_attr" "other")
+ 				     (and (eq_attr "length_immediate" "1")
+ 				      (and (eq_attr "mode" "V32HF,V16SF,V8DF")
+ 					   (eq_attr "memory" "load"))))))
+ 			 "c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sse" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_attr" "rcp,other")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_0_1")
+ 
+ (define_insn_reservation "c86_4g_m7_avx_sse_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "c86_attr" "rcp,other")
+ 				    (and (eq_attr "prefix" "!evex")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1")
+ 
+ ;; SSE SQRT
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_x" 14
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "SF,V4SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x9")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_xload" 21
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "SF,V4SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x9")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_y" 14
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V8SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*9")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_yload" 21
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V8SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*9")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_z" 26
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V16SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*22")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_sf_zload" 33
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V16SF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*22")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_x" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "DF,V2DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp1div1_fp3div3_x4x15")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_xload" 27
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "DF,V2DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp1div1_fp3div3_x4x15")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_y" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V4DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*15")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_yload" 27
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V4DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*15")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_z" 38
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V8DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "none")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*34")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_sse_sqrt_df_zload" 45
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "mode" "V8DF")
+ 				    (and (eq_attr "c86_attr" "sqrt")
+ 					 (eq_attr "memory" "load")))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fp13div13x4,c86-4g-m7-fdiv13*34")
+ 
+ ;; MSKLOG/MSKMOV
+ (define_insn_reservation "c86_4g_m7_avx512_msklog" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "msklog")
+ 				   (eq_attr "c86_decode" "direct")))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_msklog_vector" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "msklog")
+ 				   (eq_attr "c86_decode" "vector")))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_reg_k" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mskmov")
+ 				  (and (match_operand 0 "register_operand" "r")
+ 				       (eq_attr "memory" "none"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_xy_k" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mskmov")
+ 				   (ior (match_operand:V2DI 0 "register_operand" "v")
+ 					(match_operand:V4DI 0 "register_operand" "v"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_z_k" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mskmov")
+ 				   (match_operand:V8DI 0 "register_operand" "v")))
+ 			 "c86-4g-m7-vector,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_k" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mskmov")
+ 				  (and (match_operand 0 "register_operand" "k")
+ 				       (match_operand 1 "register_operand" "k"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_reg" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mskmov")
+ 				  (and (match_operand 0 "register_operand" "k")
+ 				       (match_operand 1 "register_operand" "r"))))
+ 			 "c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_1_3")
+ 
+ (define_insn_reservation "c86_4g_m7_avx512_mskmov_k_m" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m7")
+ 			      (and (eq_attr "type" "mskmov")
+ 				  (and (match_operand 0 "register_operand" "k")
+ 				       (match_operand 1 "memory_operand"))))
+ 			 "c86-4g-m7-direct,c86-4g-m7-load")
diff -Nrcpad gcc-15-20260612/gcc/config/i386/c86-4g.md gcc-15-20260619/gcc/config/i386/c86-4g.md
*** gcc-15-20260612/gcc/config/i386/c86-4g.md	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/config/i386/c86-4g.md	Fri Jun 19 22:32:06 2026
***************
*** 0 ****
--- 1,1214 ----
+ ;; Copyright (C) 2026 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+ ;;
+ ;; GCC is free software; you can redistribute it and/or modify
+ ;; it under the terms of the GNU General Public License as published by
+ ;; the Free Software Foundation; either version 3, or (at your option)
+ ;; any later version.
+ ;;
+ ;; GCC is distributed in the hope that it will be useful,
+ ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+ ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ ;; GNU General Public License for more details.
+ ;;
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING3.  If not see
+ ;; <http://www.gnu.org/licenses/>.
+ ;;
+ 
+ 
+ (define_attr "c86_decode" "direct,vector,double"
+   (const_string "direct"))
+ 
+ (define_attr "c86_attr" "other,abs,sqrt,maxmin,blend,blendv,rcp,movnt,avg,
+ 			       sign,sadbw,insr,perm2,perm,insertx,shufx,madd,
+ 			       compress,sselogic,cmpestr,extr,vpmovx,expand,aes,
+ 			       hplus,ptest"
+   (const_string "other"))
+ 
+ ;; HYGON Scheduling
+ ;; Modeling automatons for decoders, integer execution pipes,
+ ;; AGU pipes, floating point execution units, integer and
+ ;; floating point dividers.  Split fp1 into its own automaton
+ ;; to keep this unit independent without increasing the main
+ ;; c86_4g_fp state space.
+ (define_automaton "c86_4g, c86_4g_ieu, c86_4g_fp024, c86_4g_fp1, c86_4g_agu, c86_4g_idiv, c86_4g_fdiv")
+ 
+ ;; Decoders unit has 4 decoders and all of them can decode fast path
+ ;; and vector type instructions.
+ (define_cpu_unit "c86-4g-decode0" "c86_4g")
+ (define_cpu_unit "c86-4g-decode1" "c86_4g")
+ (define_cpu_unit "c86-4g-decode2" "c86_4g")
+ (define_cpu_unit "c86-4g-decode3" "c86_4g")
+ 
+ ;; Currently blocking all decoders for vector path instructions as
+ ;; they are dispatched separetely as microcode sequence.
+ ;; Fix me: Need to revisit this.
+ (define_reservation "c86-4g-vector" "c86-4g-decode0+c86-4g-decode1+c86-4g-decode2+c86-4g-decode3")
+ 
+ ;; Direct instructions can be issued to any of the four decoders.
+ (define_reservation "c86-4g-direct" "c86-4g-decode0|c86-4g-decode1|c86-4g-decode2|c86-4g-decode3")
+ 
+ ;; Fix me: Need to revisit this later to simulate fast path double behavior.
+ (define_reservation "c86-4g-double" "c86-4g-direct")
+ 
+ ;; Integer unit 4 ALU pipes.
+ (define_cpu_unit "c86-4g-ieu0" "c86_4g_ieu")
+ (define_cpu_unit "c86-4g-ieu1" "c86_4g_ieu")
+ (define_cpu_unit "c86-4g-ieu2" "c86_4g_ieu")
+ (define_cpu_unit "c86-4g-ieu3" "c86_4g_ieu")
+ (define_reservation "c86-4g-ieu" "c86-4g-ieu0|c86-4g-ieu1|c86-4g-ieu2|c86-4g-ieu3")
+ 
+ ;; One separated integer divider.
+ (define_cpu_unit "c86-4g-idiv" "c86_4g_idiv")
+ 
+ ;; 2 AGU pipes in c86_4g
+ ;; According to CPU diagram last AGU unit is used only for stores.
+ (define_cpu_unit "c86-4g-agu0" "c86_4g_agu")
+ (define_cpu_unit "c86-4g-agu1" "c86_4g_agu")
+ (define_reservation "c86-4g-agu-reserve" "c86-4g-agu0|c86-4g-agu1")
+ 
+ ;; Load is 4 cycles.  We do not model reservation of load unit.
+ ;;(define_reservation "c86-4g-load" "c86-4g-agu-reserve, nothing, nothing, nothing")
+ (define_reservation "c86-4g-load" "c86-4g-agu-reserve")
+ (define_reservation "c86-4g-store" "c86-4g-agu-reserve")
+ 
+ ;; vectorpath (microcoded) instructions are single issue instructions.
+ ;; So, they occupy all the integer units.
+ (define_reservation "c86-4g-ivector" "c86-4g-ieu0+c86-4g-ieu1
+ 				      +c86-4g-ieu2+c86-4g-ieu3
+ 				      +c86-4g-agu0+c86-4g-agu1")
+ 
+ ;; Floating point unit 4 FP pipes.
+ (define_cpu_unit "c86-4g-fp0" "c86_4g_fp024")
+ (define_cpu_unit "c86-4g-fp1" "c86_4g_fp1")
+ (define_cpu_unit "c86-4g-fp2" "c86_4g_fp024")
+ (define_cpu_unit "c86-4g-fp3" "c86_4g_fp024")
+ 
+ (define_reservation "c86-4g-fpu" "c86-4g-fp0|c86-4g-fp1|c86-4g-fp2|c86-4g-fp3")
+ 
+ (define_reservation "c86-4g-fvector" "c86-4g-fp0+c86-4g-fp1
+ 				      +c86-4g-fp2+c86-4g-fp3
+ 				      +c86-4g-agu0+c86-4g-agu1")
+ 
+ ;; One separated FP divider.
+ (define_cpu_unit "c86-4g-fdiv" "c86_4g_fdiv")
+ 
+ (define_reservation "c86-4g-fp1fdivx4" "(c86-4g-fp1+c86-4g-fdiv)*4")
+ 
+ ;; Call instruction
+ (define_insn_reservation "c86_4g_call" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (eq_attr "type" "call,callv"))
+ 			 "c86-4g-double,c86-4g-store,c86-4g-ieu0+c86-4g-ieu3")
+ 
+ ;; General instructions
+ (define_insn_reservation "c86_4g_push" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "push")
+ 				   (eq_attr "memory" "store")))
+ 			 "c86-4g-direct,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_push_load" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "push")
+ 				   (eq_attr "memory" "both")))
+ 			 "c86-4g-direct,c86-4g-load+c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_pop" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "pop")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load")
+ 
+ (define_insn_reservation "c86_4g_pop_mem" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "pop")
+ 				   (eq_attr "memory" "both")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-store")
+ 
+ ;; Leave
+ (define_insn_reservation "c86_4g_leave" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (eq_attr "type" "leave"))
+ 			 "c86-4g-double,c86-4g-ieu+c86-4g-store")
+ 
+ ;; Integer Instructions or General instructions
+ ;; Multiplications
+ ;; Reg operands
+ (define_insn_reservation "c86_4g_imul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "imul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-ieu1")
+ 
+ (define_insn_reservation "c86_4g_imul_mem" 7
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "imul")
+ 				   (eq_attr "memory" "!none")))
+ 			 "c86-4g-direct,c86-4g-load, c86-4g-ieu1")
+ 
+ ;; Divisions
+ ;; Reg operands
+ (define_insn_reservation "c86_4g_idiv_DI" 41
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "DI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-ieu2,c86-4g-idiv*41")
+ 
+ (define_insn_reservation "c86_4g_idiv_SI" 25
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "SI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-ieu2,c86-4g-idiv*25")
+ 
+ (define_insn_reservation "c86_4g_idiv_HI" 17
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "HI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-ieu2,c86-4g-idiv*17")
+ 
+ (define_insn_reservation "c86_4g_idiv_QI" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "QI")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-ieu2,c86-4g-idiv*15")
+ 
+ ;; Mem operands
+ (define_insn_reservation "c86_4g_idiv_mem_DI" 45
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "DI")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*41")
+ 
+ (define_insn_reservation "c86_4g_idiv_mem_SI" 29
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "SI")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*25")
+ 
+ (define_insn_reservation "c86_4g_idiv_mem_HI" 21
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "HI")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*17")
+ 
+ (define_insn_reservation "c86_4g_idiv_mem_QI" 19
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "idiv")
+ 				   (and (eq_attr "mode" "QI")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-ieu2,c86-4g-idiv*15")
+ 
+ ;; STR ISHIFT which are micro coded.
+ ;; Fix me: Latency need to be rechecked.
+ (define_insn_reservation "c86_4g_str_ishift" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "str,ishift")
+ 				   (eq_attr "memory" "both,store")))
+ 			 "c86-4g-vector,c86-4g-ivector")
+ 
+ ;; MOV - integer moves
+ (define_insn_reservation "c86_4g_load_imov_double" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "imovx")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-ieu")
+ 
+ (define_insn_reservation "c86_4g_load_imov_direct" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "!double")
+ 				   (and (eq_attr "type" "imov,imovx")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-ieu")
+ 
+ (define_insn_reservation "c86_4g_load_imov_double_store" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "imovx")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-double,c86-4g-ieu,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_load_imov_direct_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "!double")
+ 				   (and (eq_attr "type" "imov,imovx")
+ 					(eq_attr "memory" "store"))))
+ 				   "c86-4g-direct,c86-4g-ieu,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_load_imov_double_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "imovx")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-ieu")
+ 
+ (define_insn_reservation "c86_4g_load_imov_direct_load" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "!double")
+ 				   (and (eq_attr "type" "imov,imovx")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load")
+ 
+ ;; INTEGER/GENERAL instructions
+ ;; register/imm operands only: ALU, ICMP, NEG, NOT, ROTATE, ISHIFT, TEST
+ (define_insn_reservation "c86_4g_insn" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov")
+ 				   (eq_attr "memory" "none,unknown")))
+ 			 "c86-4g-direct,c86-4g-ieu")
+ 
+ (define_insn_reservation "c86_4g_insn_load" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-ieu")
+ 
+ ;; FIXME: The instructions matched here has only two operands, which means memory type can only be none, load or both.
+ ;; Store memory type handling should never take effect here?
+ (define_insn_reservation "c86_4g_insn_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
+ 				   (eq_attr "memory" "store")))
+ 			 "c86-4g-direct,c86-4g-ieu,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_insn_both" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec")
+ 				   (eq_attr "memory" "both")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-ieu,c86-4g-store")
+ 
+ ;; Special latency for multi type.
+ (define_insn_reservation "c86_4g_fp_fcomp" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "memory" "none")
+ 				   (and (eq_attr "unit" "i387")
+ 					(eq_attr "type" "multi"))))
+ 			 "c86-4g-double,c86-4g-fp0|c86-4g-fp2")
+ 
+ ;; Fix me: Other vector type insns keeping latency 6 as of now.
+ (define_insn_reservation "c86_4g_ieu_vector" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "memory" "none")
+ 				   (and (eq_attr "unit" "!i387")
+ 					(eq_attr "type" "other,str,multi"))))
+ 			 "c86-4g-vector,c86-4g-ivector")
+ 
+ ;; ALU1 register operands.
+ (define_insn_reservation "c86_4g_alu1_vector" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "vector")
+ 				   (and (eq_attr "type" "alu1")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-vector,c86-4g-ivector")
+ 
+ (define_insn_reservation "c86_4g_alu1_double" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "alu1")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-double,c86-4g-ieu")
+ 
+ (define_insn_reservation "c86_4g_alu1_direct" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "alu1")
+ 					(eq_attr "memory" "none,unknown"))))
+ 			 "c86-4g-direct,c86-4g-ieu")
+ 
+ ;; Branches : Fix me need to model conditional branches.
+ (define_insn_reservation "c86_4g_branch" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "ibr")
+ 					(eq_attr "memory" "none")))
+ 			  "c86-4g-direct")
+ 
+ ;; Indirect branches check latencies.
+ (define_insn_reservation "c86_4g_indirect_branch_mem" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "ibr")
+ 					(eq_attr "memory" "load")))
+ 			 "c86-4g-vector,c86-4g-ivector")
+ 
+ ;; LEA executes in ALU units with 1 cycle latency.
+ (define_insn_reservation "c86_4g_lea" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (eq_attr "type" "lea"))
+ 			 "c86-4g-direct,c86-4g-ieu")
+ 
+ ;;  Floating point
+ (define_insn_reservation "c86_4g_fp_cmov" 6
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (eq_attr "type" "fcmov"))
+ 			 "c86-4g-vector,c86-4g-fvector")
+ 
+ 
+ (define_insn_reservation "c86_4g_fp_mov_direct_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_fp_mov_direct_store" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-direct,c86-4g-fp2|c86-4g-fp3,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_fp_mov_double" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_fp_mov_double_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "double")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_fp_mov_direct" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fmov")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp1")
+ 
+ ;; SQRT
+ (define_insn_reservation "c86_4g_fp_sqrt" 22
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "fpspc")
+ 				   (eq_attr "c86_attr" "sqrt")))
+ 			 "c86-4g-direct,c86-4g-fp1fdivx4,c86-4g-fdiv*18")
+ 
+ (define_insn_reservation "c86_4g_sse_sqrt_sf" 14
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SF,V4SF,V8SF")
+ 				   (and (eq_attr "memory" "none,unknown")
+ 					(and (eq_attr "c86_attr" "sqrt")
+ 					     (eq_attr "type" "sse")))))
+ 			 "c86-4g-direct,c86-4g-fp1fdivx4,c86-4g-fdiv*10")
+ 
+ (define_insn_reservation "c86_4g_sse_sqrt_sf_mem" 21
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SF,V4SF,V8SF")
+ 				   (and (eq_attr "memory" "load")
+ 					(and (eq_attr "c86_attr" "sqrt")
+ 					     (eq_attr "type" "sse")))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1fdivx4,c86-4g-fdiv*10")
+ 
+ (define_insn_reservation "c86_4g_sse_sqrt_df" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "DF,V2DF,V4DF")
+ 				   (and (eq_attr "memory" "none,unknown")
+ 					(and (eq_attr "c86_attr" "sqrt")
+ 					     (eq_attr "type" "sse")))))
+ 			 "c86-4g-direct,c86-4g-fp1fdivx4,c86-4g-fdiv*16")
+ 
+ (define_insn_reservation "c86_4g_sse_sqrt_df_mem" 27
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "DF,V2DF,V4DF")
+ 				   (and (eq_attr "memory" "load")
+ 					(and (eq_attr "c86_attr" "sqrt")
+ 					     (eq_attr "type" "sse")))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1fdivx4,c86-4g-fdiv*16")
+ 
+ ;; RCP
+ (define_insn_reservation "c86_4g_sse_rcp" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V4SF,V8SF,SF")
+ 				   (and (eq_attr "memory" "none")
+ 					(and (eq_attr "c86_attr" "rcp")
+ 					     (eq_attr "type" "sse")))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_rcp_mem" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V4SF,V8SF,SF")
+ 				   (and (eq_attr "memory" "load")
+ 					(and (eq_attr "c86_attr" "rcp")
+ 					     (eq_attr "type" "sse")))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ ;; TODO: AGU?
+ (define_insn_reservation "c86_4g_fp_spc_direct" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_decode" "direct")
+ 				   (and (eq_attr "type" "fpspc")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-direct,c86-4g-fp3")
+ 
+ ;; FABS
+ (define_insn_reservation "c86_4g_fp_absneg" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (eq_attr "type" "fsgn"))
+ 			 "c86-4g-direct,c86-4g-fp1|c86-4g-fp3")
+ 
+ ;; FCMP
+ (define_insn_reservation "c86_4g_fp_fcmp" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				  (and (eq_attr "memory" "none")
+ 				  (and (eq_attr "c86_decode" "double")
+ 				       (eq_attr "type" "fcmp"))))
+ 			 "c86-4g-double,c86-4g-fp0,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_fp_fcmp_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "memory" "load")
+ 				   (and (eq_attr "c86_decode" "double")
+ 					(eq_attr "type" "fcmp"))))
+ 			 "c86-4g-double,c86-4g-load, c86-4g-fp0,c86-4g-fp1")
+ 
+ ;;FADD FSUB FMUL
+ (define_insn_reservation "c86_4g_fp_op_mul" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "fop,fmul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_fp_op_mul_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "fop,fmul")
+ 				   (and (eq_attr "fp_int_src" "false")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_fp_op_imul_load" 16
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "fop,fmul")
+ 				   (and (eq_attr "fp_int_src" "true")
+ 					(eq_attr "memory" "load"))))
+ 			"c86-4g-double,c86-4g-load,c86-4g-fp0,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_fp_op_div" 15
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp1fdivx4,c86-4g-fdiv*11")
+ 
+ (define_insn_reservation "c86_4g_fp_op_div_load" 22
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1fdivx4,c86-4g-fdiv*11")
+ 
+ (define_insn_reservation "c86_4g_fp_op_idiv_load" 26
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "fdiv")
+ 				   (and (eq_attr "fp_int_src" "true")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp1*4,c86-4g-fp1fdivx4,c86-4g-fdiv*11")
+ 
+ ;; MMX, SSE, SSEn.n, AVX, AVX2 instructions
+ (define_insn_reservation "c86_4g_fp_insn" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (eq_attr "type" "mmx"))
+ 			 "c86-4g-direct,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_mmx_add" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxadd")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1|c86-4g-fp3")
+ 
+ (define_insn_reservation "c86_4g_mmx_add_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxadd")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1|c86-4g-fp3")
+ 
+ (define_insn_reservation "c86_4g_mmx_hadd" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseadd1")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_mmx_hadd_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseadd1")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_mmx_cmp" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxcmp")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp3")
+ 
+ (define_insn_reservation "c86_4g_mmx_cmp_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxcmp")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp3")
+ 
+ (define_insn_reservation "c86_4g_mmx_cvt_pck_shuf" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_mmx_cvt_pck_shuf_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxcvt,sseshuf,sseshuf1")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_mmx_shift" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_mmx_move" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxmov")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_mmx_shift_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_mmx_move_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxshft")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_mmx_move_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxshft,mmxmov")
+ 				   (eq_attr "memory" "store,both")))
+ 			  "c86-4g-direct,c86-4g-fp2,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_mmx_mul" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxmul")
+ 				   (eq_attr "memory" "none")))
+ 			  "c86-4g-direct,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_mmx_mul_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "mmxmul")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+ 
+ ;; sseabs
+ (define_insn_reservation "c86_4g_sse_abs" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_attr" "abs")
+ 				   (and (eq_attr "type" "sselog1")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_sse_pinsr_reg" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 					(and (match_operand 2 "register_operand")
+ 					     (eq_attr "memory" "none")))))
+ 			 "c86-4g-direct,c86-4g-ieu2,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_pinsr" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "insr")
+ 					(and (not (match_operand 2 "register_operand"))
+ 					     (eq_attr "memory" "none")))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_log" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_log_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_sign" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sign")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_sse_sign_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "sign")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+ 
+ 
+ (define_insn_reservation "c86_4g_sse_log1" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_log1_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sselog1")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "!none"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_extrq" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "prefix_data16" "1"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_movsdup" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sse")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "prefix" "vex"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_alignr" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "prefix_extra" "1"))
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_ishift" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "prefix_extra" "!1"))
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_ishift_load" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "prefix_extra" "!1"))
+ 			      (and (eq_attr "type" "sseishft")
+ 				   (eq_attr "memory" "!none")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_insertimm" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseins")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "length_immediate" "2"))))
+ 			 "c86-4g-direct,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sse_insert" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseins")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "length_immediate" "!2"))))
+ 			 "c86-4g-direct,c86-4g-fpu,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sse_comi" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SF,DF,V4SF,V2DF")
+ 				   (and (eq_attr "prefix" "!vex")
+ 					(and (eq_attr "prefix_extra" "0")
+ 					     (and (eq_attr "type" "ssecomi")
+ 						  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_comi_load" 12
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "SF,DF,V4SF,V2DF"))
+ 			      (and (eq_attr "prefix_extra" "0")
+ 				   (and (eq_attr "type" "ssecomi")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_comi_double" 2
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "V4SF,V2DF,TI"))
+ 			      (and (eq_attr "prefix" "vex")
+ 				   (and (eq_attr "prefix_extra" "0")
+ 					(and (eq_attr "type" "ssecomi")
+ 					     (eq_attr "memory" "none")))))
+ 			 "c86-4g-double,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_comi_double_load" 10
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "V4SF,V2DF,TI"))
+ 			      (and (eq_attr "prefix" "vex")
+ 				   (and (eq_attr "prefix_extra" "0")
+ 					(and (eq_attr "type" "ssecomi")
+ 					     (eq_attr "memory" "load")))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp0|c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_test" 4
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
+ 			      (and (eq_attr "prefix_extra" "1")
+ 				   (and (eq_attr "type" "ssecomi")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_test_load" 11
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
+ 			      (and (eq_attr "prefix_extra" "1")
+ 				   (and (eq_attr "type" "ssecomi")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_avx256_test" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "V8SF,V4DF,OI"))
+ 			      (and (eq_attr "prefix_extra" "1")
+ 				   (and (eq_attr "type" "ssecomi")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_avx256_test_load" 15
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "V8SF,V4DF,OI"))
+ 			      (and (eq_attr "prefix_extra" "1")
+ 				   (and (eq_attr "type" "ssecomi")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1")
+ 
+ ;; SSE moves
+ ;; Fix me:  Need to revist this again some of the moves may be restricted
+ ;; to some fpu pipes.
+ 
+ ;; movnt doesn't touch cache, so latency modeling has little impact.
+ (define_insn_reservation "c86_4g_sse_movnt_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_attr" "movnt")
+ 				   (and (eq_attr "type" "ssemov,mmxmov,ssecvt")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load")
+ 
+ (define_insn_reservation "c86_4g_sse_movnt_store" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "c86_attr" "movnt")
+ 				   (and (eq_attr "type" "ssemov,mmxmov,ssecvt")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-direct,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_sse_mov" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SI")
+ 				   (and (eq_attr "isa" "avx")
+ 					(and (eq_attr "type" "ssemov")
+ 					     (eq_attr "memory" "none")))))
+ 			 "c86-4g-direct,c86-4g-ieu0")
+ 
+ (define_insn_reservation "c86_4g_avx_mov" 2
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "TI")
+ 				   (and (eq_attr "isa" "avx")
+ 					(and (eq_attr "type" "ssemov")
+ 					     (and (match_operand:SI 1 "register_operand")
+ 						  (eq_attr "memory" "none"))))))
+ 			 "c86-4g-direct,c86-4g-ieu2")
+ 
+ (define_insn_reservation "c86_4g_sseavx_mov" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
+ 			      (and (eq_attr "prefix_extra" "0")
+ 				   (and (eq_attr "type" "ssemov")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_sseavx_blend" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "SF,DF,V4SF,V2DF"))
+ 			      (and (eq_attr "type" "ssemov,sselog1")
+ 				   (and (eq_attr "c86_attr" "blend,blendv")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sseavx_mov_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SF,DF,V4SF,V2DF,TI")
+ 				   (and (eq_attr "type" "ssemov")
+ 					(eq_attr "memory" "store"))))
+ 			"c86-4g-direct,c86-4g-fpu,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_sseavx_mov_load" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "SF,DF,V4SF,V2DF,TI"))
+ 			       (and (eq_attr "type" "ssemov")
+ 				    (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_avx256_mov" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 				   (and (eq_attr "type" "ssemov")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_avx256_mov_store" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 				   (and (eq_attr "type" "ssemov")
+ 					(eq_attr "memory" "store"))))
+ 			 "c86-4g-double,c86-4g-fpu,c86-4g-store")
+ 
+ (define_insn_reservation "c86_4g_avx256_mov_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V8SF,V4DF,OI")
+ 				   (and (eq_attr "type" "ssemov")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fpu")
+ 
+ ;; SSE max & min
+ (define_insn_reservation "c86_4g_sse_maxmin" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "SF,DF,V4SF,V8SF,V2DF,V4DF,TI"))
+ 			      (and (eq_attr "type" "sseadd")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "c86_attr" "maxmin"))))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_maxmin_load" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "SF,DF,V4SF,V8SF,V2DF,V4DF,TI"))
+ 			      (and (eq_attr "type" "sseadd")
+ 				   (and (eq_attr "memory" "load")
+ 					(eq_attr "c86_attr" "maxmin"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_pmaxmin" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "TI,OI"))
+ 			      (and (eq_attr "type" "mmxadd,sseiadd")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "c86_attr" "maxmin"))))
+ 			 "c86-4g-direct,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_sse_pmaxmin_load" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "TI,OI"))
+ 			      (and (eq_attr "type" "mmxadd,sseiadd")
+ 				   (and (eq_attr "memory" "load")
+ 					(eq_attr "c86_attr" "maxmin"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+ 
+ ;; SSE avg
+ (define_insn_reservation "c86_4g_sse_avg" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "c86_attr" "avg"))
+ 			      (and (eq_attr "type" "sseiadd,mmxshft")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_sse_avg_load" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "c86_attr" "avg"))
+ 			      (and (eq_attr "type" "sseiadd,mmxshft")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp3")
+ 
+ ;;MMX sadbw
+ (define_insn_reservation "c86_4g_sse_sadbw" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseiadd,mmxshft")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sse_sadbw_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseiadd,mmxshft")
+ 				   (and (eq_attr "c86_attr" "sadbw")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+ 
+ ;; SSE add
+ (define_insn_reservation "c86_4g_sse_add" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseadd")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "c86_attr" "other"))))
+ 			 "c86-4g-direct,c86-4g-fp1|c86-4g-fp3")
+ 
+ (define_insn_reservation "c86_4g_sse_add_load" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseadd")
+ 				   (and (eq_attr "memory" "load")
+ 					(eq_attr "c86_attr" "!maxmin"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1|c86-4g-fp3")
+ 
+ (define_insn_reservation "c86_4g_sse_fma" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "ssemuladd")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_fma_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "ssemuladd")
+ 				   (eq_attr "memory" "load")))
+ 			"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_iadd" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fpu")
+ 
+ (define_insn_reservation "c86_4g_sse_iadd_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "sseiadd")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+ 
+ ;; SSE conversions.
+ (define_insn_reservation "c86_4g_ssecvtsf_si_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SI")
+ 				   (and (eq_attr "type" "sseicvt")
+ 					(and (match_operand:SF 1 "memory_operand")
+ 					     (eq_attr "memory" "load")))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp3,c86-4g-ieu0")
+ 
+ (define_insn_reservation "c86_4g_ssecvtdf_si" 5
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SI")
+ 				   (and (match_operand:DF 1 "register_operand")
+ 					(and (eq_attr "type" "sseicvt")
+ 					     (eq_attr "memory" "none")))))
+ 			 "c86-4g-double,c86-4g-fp3,c86-4g-ieu0")
+ 
+ (define_insn_reservation "c86_4g_ssecvtdf_si_load" 12
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "SI")
+ 				   (and (eq_attr "type" "sseicvt")
+ 					(and (match_operand:DF 1 "memory_operand")
+ 					     (eq_attr "memory" "load")))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp3,c86-4g-ieu0")
+ 
+ ;; All other used ssecvt fp3 pipes
+ ;; Check: Need to revisit this again.
+ ;; Some SSE converts may use different pipe combinations.
+ (define_insn_reservation "c86_4g_ssecvt" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-direct,c86-4g-fp1")
+ 
+ (define_insn_reservation "c86_4g_ssecvt_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "type" "ssecvt")
+ 				   (and (eq_attr "c86_attr" "other")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1")
+ 
+ ;; SSE div
+ (define_insn_reservation "c86_4g_ssediv_ss_ps" 10
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "V4SF,SF"))
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp1fdivx4,c86-4g-fdiv*6")
+ 
+ (define_insn_reservation "c86_4g_ssediv_ss_ps_load" 17
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "V4SF,SF"))
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1fdivx4,c86-4g-fdiv*6")
+ 
+ (define_insn_reservation "c86_4g_ssediv_sd_pd" 13
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "V2DF,DF"))
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp1fdivx4,c86-4g-fdiv*9")
+ 
+ (define_insn_reservation "c86_4g_ssediv_sd_pd_load" 20
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					       (eq_attr "mode" "V2DF,DF"))
+ 			      (and (eq_attr "type" "ssediv")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp1fdivx4,c86-4g-fdiv*9")
+ 
+ 
+ (define_insn_reservation "c86_4g_ssediv_avx256_ps" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V8SF")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "type" "ssediv"))))
+ 			 "c86-4g-double,c86-4g-fp1fdivx4,c86-4g-fdiv*6")
+ 
+ (define_insn_reservation "c86_4g_ssediv_avx256_ps_load" 17
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V8SF")
+ 				   (and (eq_attr "type" "ssediv")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp1fdivx4,c86-4g-fdiv*6")
+ 
+ (define_insn_reservation "c86_4g_ssediv_avx256_pd" 13
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V4DF")
+ 				   (and (eq_attr "type" "ssediv")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-fp1fdivx4,c86-4g-fdiv*9")
+ 
+ (define_insn_reservation "c86_4g_ssediv_avx256_pd_load" 20
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V4DF")
+ 				   (and (eq_attr "type" "ssediv")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp1fdivx4,c86-4g-fdiv*9")
+ ;; SSE MUL
+ (define_insn_reservation "c86_4g_ssemul_ss_ps" 3
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "V8SF,V4SF,SF"))
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_ssemul_ss_ps_load" 10
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "V8SF,V4SF,SF"))
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_ssemul_sd_pd" 4
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "V4DF,V2DF,DF"))
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_ssemul_sd_pd_load" 11
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "V4DF,V2DF,DF"))
+ 			      (and (eq_attr "type" "ssemul")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ ;;SSE imul
+ (define_insn_reservation "c86_4g_sseimul" 3
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "TI"))
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sseimul_avx256" 4
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "OI")
+ 				   (and (eq_attr "type" "sseimul")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sseimul_load" 10
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "TI"))
+ 			      (and (eq_attr "type" "sseimul")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sseimul_avx256_load" 11
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "OI")
+ 				   (and (eq_attr "type" "sseimul")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sseimul_di" 3
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "DI")
+ 				   (and (eq_attr "memory" "none")
+ 					(eq_attr "type" "sseimul"))))
+ 			 "c86-4g-direct,c86-4g-fp0")
+ 
+ (define_insn_reservation "c86_4g_sseimul_load_di" 10
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "DI")
+ 				   (and (eq_attr "type" "sseimul")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0")
+ 
+ ;; SSE compares
+ (define_insn_reservation "c86_4g_sse_cmp" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					(eq_attr "mode" "SF,DF,V4SF,V2DF"))
+ 			       (and (eq_attr "type" "ssecmp")
+ 				    (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_cmp_load" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 					 (eq_attr "mode" "SF,DF,V4SF,V2DF"))
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ 
+ (define_insn_reservation "c86_4g_sse_cmp_avx256" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V8SF,V4DF")
+ 				   (and (eq_attr "type" "ssecmp")
+ 					(eq_attr "memory" "none"))))
+ 			"c86-4g-double,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_cmp_avx256_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "V8SF,V4DF")
+ 				   (and (eq_attr "type" "ssecmp")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fp0|c86-4g-fp2")
+ 
+ (define_insn_reservation "c86_4g_sse_icmp" 1
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "QI,HI,SI,DI,TI"))
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (eq_attr "memory" "none")))
+ 			 "c86-4g-direct,c86-4g-fpu")
+ 
+ 
+ (define_insn_reservation "c86_4g_sse_icmp_load" 8
+ 			 (and (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 				   (eq_attr "mode" "QI,HI,SI,DI,TI"))
+ 			      (and (eq_attr "type" "ssecmp")
+ 				   (eq_attr "memory" "load")))
+ 			 "c86-4g-direct,c86-4g-load,c86-4g-fpu")
+ 
+ 
+ (define_insn_reservation "c86_4g_sse_icmp_avx256" 1
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "OI")
+ 				   (and (eq_attr "type" "ssecmp")
+ 					(eq_attr "memory" "none"))))
+ 			 "c86-4g-double,c86-4g-fpu")
+ 
+ 
+ (define_insn_reservation "c86_4g_sse_icmp_avx256_load" 8
+ 			 (and (eq_attr "cpu" "c86_4g_m4,c86_4g_m6")
+ 			      (and (eq_attr "mode" "OI")
+ 				   (and (eq_attr "type" "ssecmp")
+ 					(eq_attr "memory" "load"))))
+ 			 "c86-4g-double,c86-4g-load,c86-4g-fpu")
diff -Nrcpad gcc-15-20260612/gcc/config/i386/cpuid.h gcc-15-20260619/gcc/config/i386/cpuid.h
*** gcc-15-20260612/gcc/config/i386/cpuid.h	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/i386/cpuid.h	Fri Jun 19 22:32:06 2026
***************
*** 229,234 ****
--- 229,238 ----
  #define signature_SHANGHAI_ecx	0x20206961
  #define signature_SHANGHAI_edx	0x68676e61
  
+ #define signature_HYGON_ebx	0x6f677948
+ #define signature_HYGON_ecx	0x656e6975
+ #define signature_HYGON_edx	0x6e65476e
+ 
  #ifndef __x86_64__
  /* At least one cpu (Winchip 2) does not set %ebx and %ecx
     for cpuid leaf 1. Forcibly zero the two registers before
diff -Nrcpad gcc-15-20260612/gcc/config/i386/driver-i386.cc gcc-15-20260619/gcc/config/i386/driver-i386.cc
*** gcc-15-20260612/gcc/config/i386/driver-i386.cc	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/i386/driver-i386.cc	Fri Jun 19 22:32:06 2026
*************** const char *host_detect_local_cpu (int a
*** 526,531 ****
--- 526,541 ----
        else
  	processor = PROCESSOR_PENTIUM;
      }
+   else if (vendor == VENDOR_HYGON)
+     {
+       processor = PROCESSOR_GENERIC;
+       if (model == 4)
+ 	processor = PROCESSOR_C86_4G_M4;
+       else if (model == 6)
+ 	processor = PROCESSOR_C86_4G_M6;
+       else if (model >= 7)
+ 	processor = PROCESSOR_C86_4G_M7;
+     }
    else if (vendor == VENDOR_CENTAUR)
      {
        processor = PROCESSOR_GENERIC;
*************** const char *host_detect_local_cpu (int a
*** 868,873 ****
--- 878,892 ----
      case PROCESSOR_SHIJIDADAO:
        cpu = "shijidadao";
        break;
+     case PROCESSOR_C86_4G_M4:
+       cpu = "c86-4g-m4";
+       break;
+     case PROCESSOR_C86_4G_M6:
+       cpu = "c86-4g-m6";
+       break;
+     case PROCESSOR_C86_4G_M7:
+       cpu = "c86-4g-m7";
+       break;
  
      default:
        /* Use something reasonable.  */
diff -Nrcpad gcc-15-20260612/gcc/config/i386/i386-c.cc gcc-15-20260619/gcc/config/i386/i386-c.cc
*** gcc-15-20260612/gcc/config/i386/i386-c.cc	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/i386/i386-c.cc	Fri Jun 19 22:32:06 2026
*************** ix86_target_macros_internal (HOST_WIDE_I
*** 295,301 ****
        def_or_undef (parse_in, "__diamondrapids");
        def_or_undef (parse_in, "__diamondrapids__");
        break;
! 
      /* use PROCESSOR_max to not set/unset the arch macro.  */
      case PROCESSOR_max:
        break;
--- 295,312 ----
        def_or_undef (parse_in, "__diamondrapids");
        def_or_undef (parse_in, "__diamondrapids__");
        break;
!     case PROCESSOR_C86_4G_M4:
!       def_or_undef (parse_in, "__c86_4g_m4");
!       def_or_undef (parse_in, "__c86_4g_m4__");
!       break;
!     case PROCESSOR_C86_4G_M6:
!       def_or_undef (parse_in, "__c86_4g_m6");
!       def_or_undef (parse_in, "__c86_4g_m6__");
!       break;
!     case PROCESSOR_C86_4G_M7:
!       def_or_undef (parse_in, "__c86_4g_m7");
!       def_or_undef (parse_in, "__c86_4g_m7__");
!       break;
      /* use PROCESSOR_max to not set/unset the arch macro.  */
      case PROCESSOR_max:
        break;
*************** ix86_target_macros_internal (HOST_WIDE_I
*** 498,503 ****
--- 509,523 ----
      case PROCESSOR_DIAMONDRAPIDS:
        def_or_undef (parse_in, "__tune_diamondrapids__");
        break;
+     case PROCESSOR_C86_4G_M4:
+       def_or_undef (parse_in, "__tune_c86_4g_m4__");
+       break;
+     case PROCESSOR_C86_4G_M6:
+       def_or_undef (parse_in, "__tune_c86_4g_m6__");
+       break;
+     case PROCESSOR_C86_4G_M7:
+       def_or_undef (parse_in, "__tune_c86_4g_m7__");
+       break;
      case PROCESSOR_INTEL:
      case PROCESSOR_GENERIC:
        break;
diff -Nrcpad gcc-15-20260612/gcc/config/i386/i386-options.cc gcc-15-20260619/gcc/config/i386/i386-options.cc
*** gcc-15-20260612/gcc/config/i386/i386-options.cc	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/i386/i386-options.cc	Fri Jun 19 22:32:06 2026
*************** along with GCC; see the file COPYING3.
*** 183,188 ****
--- 183,192 ----
  #define m_ZNVER (m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ZNVER5)
  #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER \
  			| m_ZNVER)
+ #define m_C86_4G_M4 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M4)
+ #define m_C86_4G_M6 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M6)
+ #define m_C86_4G_M7 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M7)
+ #define m_C86_4G (m_C86_4G_M4 | m_C86_4G_M6 | m_C86_4G_M7)
  
  #define m_GENERIC (HOST_WIDE_INT_1U<<PROCESSOR_GENERIC)
  
*************** static const struct processor_costs *pro
*** 820,826 ****
    &znver2_cost,
    &znver3_cost,
    &znver4_cost,
!   &znver5_cost
  };
  
  /* Guarantee that the array is aligned with enum processor_type.  */
--- 824,833 ----
    &znver2_cost,
    &znver3_cost,
    &znver4_cost,
!   &znver5_cost,
!   &c86_4g_m4_cost,	/* PROCESSOR_C86_4G_M4.		*/
!   &c86_4g_m6_cost,	/* PROCESSOR_C86_4G_M6.		*/
!   &c86_4g_m7_cost	/* PROCESSOR_C86_4G_M7.		*/
  };
  
  /* Guarantee that the array is aligned with enum processor_type.  */
diff -Nrcpad gcc-15-20260612/gcc/config/i386/i386.cc gcc-15-20260619/gcc/config/i386/i386.cc
*** gcc-15-20260612/gcc/config/i386/i386.cc	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/i386/i386.cc	Fri Jun 19 22:32:06 2026
*************** ix86_reassociation_width (unsigned int o
*** 24933,24939 ****
        /* Znver1-4 Integer vector instructions execute in FP unit
  	 and can execute 3 additions and one multiplication per cycle.  */
        if ((ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2
! 	   || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4)
     	  && INTEGRAL_MODE_P (mode) && op != PLUS && op != MINUS)
  	return 1;
        /* Znver5 can do 2 integer multiplications per cycle with latency
--- 24933,24942 ----
        /* Znver1-4 Integer vector instructions execute in FP unit
  	 and can execute 3 additions and one multiplication per cycle.  */
        if ((ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2
! 	   || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4
! 	   || ix86_tune == PROCESSOR_C86_4G_M4
! 	   || ix86_tune == PROCESSOR_C86_4G_M6
! 	   || ix86_tune == PROCESSOR_C86_4G_M7)
     	  && INTEGRAL_MODE_P (mode) && op != PLUS && op != MINUS)
  	return 1;
        /* Znver5 can do 2 integer multiplications per cycle with latency
diff -Nrcpad gcc-15-20260612/gcc/config/i386/i386.h gcc-15-20260619/gcc/config/i386/i386.h
*** gcc-15-20260612/gcc/config/i386/i386.h	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/i386/i386.h	Fri Jun 19 22:32:06 2026
*************** enum processor_type
*** 2341,2346 ****
--- 2341,2349 ----
    PROCESSOR_ZNVER3,
    PROCESSOR_ZNVER4,
    PROCESSOR_ZNVER5,
+   PROCESSOR_C86_4G_M4,
+   PROCESSOR_C86_4G_M6,
+   PROCESSOR_C86_4G_M7,
    PROCESSOR_max
  };
  
*************** constexpr wide_int_bitmask PTA_LUJIAZUI
*** 2502,2507 ****
--- 2505,2525 ----
  constexpr wide_int_bitmask PTA_YONGFENG = PTA_LUJIAZUI | PTA_AVX | PTA_AVX2
    | PTA_F16C | PTA_FMA | PTA_SHA | PTA_LZCNT;
  
+ constexpr wide_int_bitmask PTA_C86_4G_M4 = PTA_64BIT | PTA_MMX | PTA_SSE
+   | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3
+   | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
+   | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
+   | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX
+   | PTA_RDSEED | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
+   | PTA_SHA | PTA_LZCNT | PTA_POPCNT;
+ constexpr wide_int_bitmask PTA_C86_4G_M6 = PTA_C86_4G_M4;
+ constexpr wide_int_bitmask PTA_C86_4G_M7 = PTA_C86_4G_M4 | PTA_AVX512F
+   | PTA_AVX512DQ | PTA_AVX512IFMA | PTA_AVX512CD | PTA_AVX512BW | PTA_AVX512VL
+   | PTA_AVX512BF16 | PTA_AVX512VBMI | PTA_AVX512VBMI2 | PTA_GFNI
+   | PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ
+   | PTA_AVX512VP2INTERSECT | PTA_VAES | PTA_AVXVNNI | PTA_VPCLMULQDQ
+   | PTA_WBNOINVD | PTA_CLWB;
+ 
  #ifndef GENERATOR_FILE
  
  #include "insn-attr-common.h"
diff -Nrcpad gcc-15-20260612/gcc/config/i386/i386.md gcc-15-20260619/gcc/config/i386/i386.md
*** gcc-15-20260612/gcc/config/i386/i386.md	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/i386/i386.md	Fri Jun 19 22:32:06 2026
***************
*** 528,534 ****
  (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem,
  		    atom,slm,glm,haswell,generic,lujiazui,yongfeng,amdfam10,bdver1,
  		    bdver2,bdver3,bdver4,btver2,znver1,znver2,znver3,znver4,
! 		    znver5"
    (const (symbol_ref "ix86_schedule")))
  
  ;; A basic instruction type.  Refinements due to arguments to be
--- 528,534 ----
  (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem,
  		    atom,slm,glm,haswell,generic,lujiazui,yongfeng,amdfam10,bdver1,
  		    bdver2,bdver3,bdver4,btver2,znver1,znver2,znver3,znver4,
! 		    znver5,c86_4g_m4,c86_4g_m6,c86_4g_m7"
    (const (symbol_ref "ix86_schedule")))
  
  ;; A basic instruction type.  Refinements due to arguments to be
***************
*** 1426,1431 ****
--- 1426,1433 ----
  (include "haswell.md")
  (include "lujiazui.md")
  (include "yongfeng.md")
+ (include "c86-4g.md")
+ (include "c86-4g-m7.md")
  
  
  ;; Operand and operator predicates and constraints
***************
*** 2033,2038 ****
--- 2035,2041 ----
     (set_attr "athlon_decode" "vector")
     (set_attr "amdfam10_decode" "direct")
     (set_attr "bdver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "znver1_decode" "double")])
  
  (define_insn "*cmpx<unord><MODEF:mode>"
***************
*** 2086,2091 ****
--- 2089,2095 ----
     (set_attr "amdfam10_decode" "direct")
     (set_attr "bdver1_decode" "double")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set (attr "enabled")
       (if_then_else
         (match_test ("SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH"))
***************
*** 2477,2482 ****
--- 2481,2487 ----
      }
  }
    [(set_attr "type" "sselog1,sselog1,ssemov,ssemov")
+    (set_attr "c86_attr" "sselogic,sselogic,*,*")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 2501,2506 ****
--- 2506,2512 ----
  }
    [(set_attr "isa" "*,avx2,*,*")
     (set_attr "type" "sselog1,sselog1,ssemov,ssemov")
+    (set_attr "c86_attr" "sselogic,sselogic,*,*")
     (set_attr "prefix" "vex")
     (set_attr "mode" "OI")])
  
***************
*** 2543,2548 ****
--- 2549,2558 ----
  	      (const_string "sselog1")
  	   ]
  	   (const_string "ssemov")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "2,3")
+        (const_string "sselogic")
+        (const_string "*")))
     (set (attr "prefix")
       (if_then_else (eq_attr "type" "sselog1,ssemov")
         (const_string "maybe_vex")
***************
*** 2686,2691 ****
--- 2696,2705 ----
  	      (const_string "lea")
  	   ]
  	   (const_string "imov")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "12")
+        (const_string "sselogic")
+        (const_string "*")))
     (set (attr "modrm")
       (if_then_else
         (and (eq_attr "alternative" "4") (eq_attr "type" "imov"))
***************
*** 2906,2911 ****
--- 2920,2929 ----
  	      (const_string "lea")
  	   ]
  	   (const_string "imov")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "8")
+        (const_string "sselogic")
+        (const_string "*")))
     (set (attr "prefix")
       (if_then_else (eq_attr "type" "sselog1,ssemov")
         (const_string "maybe_vex")
***************
*** 3080,3085 ****
--- 3098,3107 ----
  	      (const_string "imovx")
  	   ]
  	   (const_string "imov")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "11")
+        (const_string "sselogic")
+        (const_string "*")))
     (set (attr "prefix")
  	(cond [(eq_attr "alternative" "4,5,6,7,8")
  		 (const_string "vex")
***************
*** 3361,3366 ****
--- 3383,3389 ----
     (set_attr "pent_pair" "np")
     (set_attr "athlon_decode" "vector")
     (set_attr "amdfam10_decode" "double")
+    (set_attr "c86_decode" "vector")
     (set_attr "bdver1_decode" "double")])
  
  (define_insn "*swap<mode>"
***************
*** 3386,3391 ****
--- 3409,3415 ----
     (set_attr "pent_pair" "np")
     (set_attr "athlon_decode" "vector")
     (set_attr "amdfam10_decode" "double")
+    (set_attr "c86_decode" "vector")
     (set_attr "bdver1_decode" "double")])
  
  (define_peephole2
***************
*** 4069,4074 ****
--- 4093,4099 ----
  }
    [(set_attr "isa" "*,*,*,x64,x64")
     (set_attr "type" "sselog1,ssemov,ssemov,multi,multi")
+    (set_attr "c86_attr" "sselogic,*,*,*,*")
     (set (attr "prefix")
       (if_then_else (eq_attr "type" "sselog1,ssemov")
         (const_string "maybe_vex")
***************
*** 4240,4245 ****
--- 4265,4274 ----
  		 (const_string "sselog1")
  	      ]
  	      (const_string "ssemov")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "12,16")
+        (const_string "sselogic")
+        (const_string "*")))
     (set (attr "modrm")
       (if_then_else (eq_attr "alternative" "11")
         (const_string "0")
***************
*** 4412,4417 ****
--- 4441,4450 ----
  		 (const_string "mmxmov")
  	      ]
  	      (const_string "ssemov")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "5")
+        (const_string "sselogic")
+        (const_string "*")))
     (set (attr "prefix")
       (if_then_else (eq_attr "type" "sselog1,ssemov")
         (const_string "maybe_vex")
***************
*** 4760,4765 ****
--- 4793,4802 ----
  	      (const_string "mskmov")
  	   ]
  	   (const_string "imovx")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "10,11")
+        (const_string "vpmovx")
+        (const_string "*")))
     (set (attr "prefix_extra")
       (if_then_else (eq_attr "alternative" "10,11")
         (const_string "1")
***************
*** 5169,5174 ****
--- 5206,5215 ----
       (if_then_else (eq_attr "prefix_0f" "0")
  	(const_string "double")
  	(const_string "direct")))
+    (set (attr "c86_decode")
+      (if_then_else (eq_attr "prefix_0f" "0")
+ 	(const_string "double")
+ 	(const_string "direct")))
     (set (attr "modrm")
       (if_then_else (eq_attr "prefix_0f" "0")
  	(const_string "0")
***************
*** 6078,6083 ****
--- 6119,6125 ----
    [(set_attr "type" "fmov")
     (set_attr "mode" "<MODE>")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "fp_int_src" "true")])
  
  (define_insn "float<SWI48x:mode>xf2"
***************
*** 6088,6093 ****
--- 6130,6136 ----
    [(set_attr "type" "fmov")
     (set_attr "mode" "XF")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "fp_int_src" "true")])
  
  (define_expand "float<SWI48x:mode><MODEF:mode>2"
***************
*** 6122,6127 ****
--- 6165,6171 ----
     (set_attr "amdfam10_decode" "*,vector,double")
     (set_attr "bdver1_decode" "*,double,direct")
     (set_attr "znver1_decode" "double,*,*")
+    (set_attr "c86_decode" "double,*,*")
     (set_attr "fp_int_src" "true")
     (set (attr "enabled")
       (if_then_else
***************
*** 6160,6165 ****
--- 6204,6210 ----
    [(set_attr "type" "fmov")
     (set_attr "mode" "<MODEF:MODE>")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "fp_int_src" "true")])
  
  ;; Try TARGET_USE_VECTOR_CONVERTS, but not so hard as to require extra memory
***************
*** 12601,12606 ****
--- 12646,12652 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "DI")])
  
  ;; Turn *anddi_1 into *andsi_1_zext if possible.
***************
*** 13658,13663 ****
--- 13704,13710 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "DI")])
  
  (define_insn_and_split "*xordi_1_btc"
***************
*** 13682,13687 ****
--- 13729,13735 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "DI")])
  
  ;; Optimize a ^ ((a ^ b) & mask) to (~mask & a) | (b & mask)
***************
*** 18839,18844 ****
--- 18887,18893 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "<MODE>")])
  
  ;; Avoid useless masking of count operand.
***************
*** 18907,18912 ****
--- 18956,18962 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "<MODE>")])
  
  ;; Avoid useless masking of count operand.
***************
*** 19048,19053 ****
--- 19098,19104 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "DI")])
  
  (define_insn "*btrq_imm"
***************
*** 19061,19066 ****
--- 19112,19118 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "DI")])
  
  (define_insn "*btcq_imm"
***************
*** 19074,19079 ****
--- 19126,19132 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "DI")])
  
  ;; Allow Nocona to avoid these instructions if a register is available.
***************
*** 21040,21045 ****
--- 21093,21099 ----
     (set_attr "prefix_0f" "1")
     (set_attr "prefix_rep" "1")
     (set_attr "btver2_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "<MODE>")])
  
  ; False dependency happens when destination is only updated by tzcnt,
***************
*** 21059,21064 ****
--- 21113,21119 ----
     (set_attr "prefix_0f" "1")
     (set_attr "prefix_rep" "1")
     (set_attr "btver2_decode" "double")
+    (set_attr "c86_decode" "double")
     (set_attr "mode" "<MODE>")])
  
  (define_insn "*bsf<mode>_1"
***************
*** 21073,21078 ****
--- 21128,21134 ----
     (set_attr "prefix_0f" "1")
     (set_attr "btver2_decode" "double")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "<MODE>")])
  
  (define_insn_and_split "ctz<mode>2"
***************
*** 21135,21140 ****
--- 21191,21197 ----
      gcc_unreachable ();
  }
    [(set_attr "type" "alu1")
+    (set_attr "c86_decode" "double")
     (set_attr "prefix_0f" "1")
     (set_attr "prefix_rep" "1")
     (set_attr "mode" "<MODE>")])
***************
*** 21160,21165 ****
--- 21217,21223 ----
       (clobber (reg:CC FLAGS_REG))])]
    "ix86_expand_clear (operands[0]);"
    [(set_attr "type" "alu1")
+    (set_attr "c86_decode" "double")
     (set_attr "prefix_0f" "1")
     (set_attr "prefix_rep" "1")
     (set_attr "mode" "SI")])
***************
*** 21180,21185 ****
--- 21238,21244 ----
    "TARGET_BMI && TARGET_64BIT"
    "tzcnt{l}\t{%1, %k0|%k0, %1}"
    [(set_attr "type" "alu1")
+    (set_attr "c86_decode" "double")
     (set_attr "prefix_0f" "1")
     (set_attr "prefix_rep" "1")
     (set_attr "mode" "SI")])
***************
*** 21257,21262 ****
--- 21316,21322 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "DI")])
  
  (define_insn "bsr_rex64_1"
***************
*** 21269,21274 ****
--- 21329,21335 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "DI")])
  
  (define_insn "bsr_rex64_1_zext"
***************
*** 21284,21289 ****
--- 21345,21351 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "DI")])
  
  (define_insn "bsr"
***************
*** 21298,21303 ****
--- 21360,21366 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "SI")])
  
  (define_insn "bsr_1"
***************
*** 21310,21315 ****
--- 21373,21379 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "SI")])
  
  (define_insn "bsr_zext_1"
***************
*** 21324,21329 ****
--- 21388,21394 ----
    [(set_attr "type" "alu1")
     (set_attr "prefix_0f" "1")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "SI")])
  
  ; As bsr is undefined behavior on zero and for other input
***************
*** 22640,22645 ****
--- 22705,22711 ----
     (set_attr "pent_pair" "np,*,*")
     (set_attr "athlon_decode" "vector,*,*")
     (set_attr "amdfam10_decode" "double,*,*")
+    (set_attr "c86_decode" "vector,*,*")
     (set_attr "bdver1_decode" "double,*,*")
     (set_attr "mode" "QI,HI,HI")])
  
***************
*** 22652,22657 ****
--- 22718,22724 ----
     (set_attr "pent_pair" "np")
     (set_attr "athlon_decode" "vector")
     (set_attr "amdfam10_decode" "double")
+    (set_attr "c86_decode" "vector")
     (set_attr "bdver1_decode" "double")
     (set_attr "mode" "QI")])
  
***************
*** 22676,22681 ****
--- 22743,22749 ----
     (set_attr "pent_pair" "np")
     (set_attr "athlon_decode" "vector")
     (set_attr "amdfam10_decode" "double")
+    (set_attr "c86_decode" "vector")
     (set_attr "bdver1_decode" "double")
     (set_attr "mode" "QI")])
  
***************
*** 23749,23754 ****
--- 23817,23823 ----
    [(set_attr "type" "fpspc")
     (set_attr "mode" "XF")
     (set_attr "athlon_decode" "direct")
+    (set_attr "c86_attr" "sqrt")
     (set_attr "amdfam10_decode" "direct")
     (set_attr "bdver1_decode" "direct")])
  
***************
*** 23917,23922 ****
--- 23986,23992 ----
    "fprem"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "fmodxf3"
***************
*** 23989,23994 ****
--- 24059,24065 ----
    "fprem1"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "remainderxf3"
***************
*** 24064,24069 ****
--- 24135,24141 ----
    "f<sincos>"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "<sincos><mode>2"
***************
*** 24095,24100 ****
--- 24167,24173 ----
    "fsincos"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "sincos<mode>3"
***************
*** 24128,24133 ****
--- 24201,24207 ----
    "fptan"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "tanxf2"
***************
*** 24170,24175 ****
--- 24244,24250 ----
    "fpatan"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "atan2<mode>3"
***************
*** 24473,24478 ****
--- 24548,24554 ----
    "fyl2x"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "logxf2"
***************
*** 24570,24575 ****
--- 24646,24652 ----
    "fyl2xp1"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "log1pxf2"
***************
*** 24610,24615 ****
--- 24687,24693 ----
    "fxtract"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "logbxf2"
***************
*** 24690,24695 ****
--- 24768,24774 ----
    "f2xm1"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_insn "fscalexf4_i387"
***************
*** 24705,24710 ****
--- 24784,24790 ----
    "fscale"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "expNcorexf3"
***************
*** 25023,25028 ****
--- 25103,25109 ----
    "frndint"
    [(set_attr "type" "fpspc")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "XF")])
  
  (define_expand "rinthf2"
***************
*** 26767,26772 ****
--- 26848,26854 ----
     v<maxmin_float><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "prefix" "orig,vex")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "type" "sseadd")
     (set_attr "mode" "<MODE>")])
  
***************
*** 26811,26816 ****
--- 26893,26899 ----
     v<ieee_maxmin><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "prefix" "orig,maybe_evex")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "type" "sseadd")
     (set_attr "mode" "<MODE>")])
  
diff -Nrcpad gcc-15-20260612/gcc/config/i386/mmx.md gcc-15-20260619/gcc/config/i386/mmx.md
*** gcc-15-20260612/gcc/config/i386/mmx.md	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/i386/mmx.md	Fri Jun 19 22:32:06 2026
***************
*** 641,646 ****
--- 641,647 ----
    [(set_attr "isa" "*,x64")
     (set_attr "mmx_isa" "native,*")
     (set_attr "type" "mmxmov,ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "mode" "DI")])
  
  (define_expand "movq_<mode>_to_sse"
***************
*** 1301,1306 ****
--- 1302,1308 ----
     vblendps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "length_immediate" "1")
     (set_attr "prefix_data16" "1,1,*")
     (set_attr "prefix_extra" "1")
***************
*** 1321,1326 ****
--- 1323,1329 ----
     vblendvps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blendv")
     (set_attr "length_immediate" "1")
     (set_attr "prefix_data16" "1,1,*")
     (set_attr "prefix_extra" "1")
***************
*** 3576,3581 ****
--- 3579,3585 ----
    [(set_attr "isa" "*,sse2_noavx,avx")
     (set_attr "mmx_isa" "native,*,*")
     (set_attr "type" "mmxmul,sseiadd,sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "mode" "DI,TI,TI")])
  
  (define_expand "mmx_pmulhrwv4hi3"
***************
*** 4323,4328 ****
--- 4327,4333 ----
     vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blendv")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,orig,vex")
***************
*** 4399,4404 ****
--- 4404,4410 ----
     vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blendv")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,orig,vex")
***************
*** 5017,5022 ****
--- 5023,5029 ----
    "%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 5049,5054 ****
--- 5056,5062 ----
    "%vpmov<extsuffix>wd\t{%1, %0|%0, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 5081,5086 ****
--- 5089,5095 ----
    "%vpmov<extsuffix>bd\t{%1, %0|%0, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 5107,5112 ****
--- 5116,5122 ----
    "%vpmov<extsuffix>bw\t{%1, %0|%0, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 5283,5288 ****
--- 5293,5299 ----
     (set_attr "addr" "gpr16,*")
     (set_attr "prefix_extra" "1")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insr")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "TI")])
***************
*** 5322,5327 ****
--- 5333,5339 ----
    [(set_attr "isa" "*,sse2_noavx,avx,sse4")
     (set_attr "mmx_isa" "native,*,*,*")
     (set_attr "type" "mmxcvt,sselog,sselog,sselog")
+    (set_attr "c86_attr" "insr")
     (set_attr "length_immediate" "1")
     (set_attr "mode" "DI,TI,TI,TI")])
  
***************
*** 5372,5377 ****
--- 5384,5390 ----
  }
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insr")
     (set_attr "addr" "gpr16,*")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 5394,5399 ****
--- 5407,5413 ----
     (set_attr "addr" "*,*,gpr16,*")
     (set_attr "mmx_isa" "native,*,*,*")
     (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,maybe_vex,maybe_vex,maybe_evex")
     (set_attr "mode" "DI,TI,TI,TI")])
***************
*** 5429,5434 ****
--- 5443,5449 ----
     (set_attr "addr" "*,*,gpr16,*,*,*")
     (set_attr "mmx_isa" "native,*,*,*,*,*")
     (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,sseishft1,sseishft1")
+    (set_attr "c86_attr" "extr,extr,extr,extr,*,*")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,maybe_vex,maybe_vex,maybe_evex,orig,maybe_evex")
     (set_attr "mode" "DI,TI,TI,TI,TI,TI")])
***************
*** 5447,5452 ****
--- 5462,5468 ----
    [(set_attr "isa" "*,sse2")
     (set_attr "mmx_isa" "native,*")
     (set_attr "type" "mmxcvt,sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,maybe_vex")
     (set_attr "mode" "DI,TI")])
***************
*** 5465,5470 ****
--- 5481,5487 ----
    [(set_attr "isa" "noavx,noavx,avx,avx")
     (set_attr "addr" "*,gpr16,*,*")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 5480,5485 ****
--- 5497,5503 ----
    "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 5606,5611 ****
--- 5624,5630 ----
     vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,orig,vex")
***************
*** 5624,5629 ****
--- 5643,5649 ----
     vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,orig,vex")
***************
*** 5806,5811 ****
--- 5826,5832 ----
  		      (const_string "*")))
     (set_attr "mmx_isa" "native,*,*,*,*,native,*,*")
     (set_attr "type" "mmxcvt,ssemov,ssemov,sseshuf1,sseshuf1,mmxmov,ssemov,imov")
+    (set_attr "c86_attr" "*,extr,extr,*,*,*,*,*")
     (set (attr "length_immediate")
       (if_then_else (eq_attr "alternative" "1,2,3,4")
  		   (const_string "1")
***************
*** 5833,5838 ****
--- 5854,5860 ----
    "%vpextrd\t{$1, %1, %k0|%k0, %1, 1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 5987,5992 ****
--- 6009,6015 ----
  }
    [(set_attr "isa" "noavx,avx,sse4")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insr")
     (set_attr "length_immediate" "1")
     (set_attr "mode" "TI")])
  
***************
*** 6039,6044 ****
--- 6062,6068 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,vex")
***************
*** 6057,6062 ****
--- 6081,6087 ----
    [(set_attr "isa" "*,sse4_noavx,avx")
     (set_attr "addr" "*,gpr16,*")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
     (set_attr "mode" "TI")])
***************
*** 6090,6095 ****
--- 6115,6121 ----
    [(set_attr "isa" "*,sse4_noavx,avx,noavx,avx")
     (set_attr "addr" "*,gpr16,*,*,*")
     (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1")
+    (set_attr "c86_attr" "extr,extr,extr,*,*")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex,orig,maybe_evex,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 6103,6108 ****
--- 6129,6135 ----
    "TARGET_SSE2"
    "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
     (set_attr "mode" "TI")])
***************
*** 6121,6126 ****
--- 6148,6154 ----
    [(set_attr "isa" "noavx,noavx,avx,avx")
     (set_attr "addr" "*,gpr16,*,*")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 6136,6141 ****
--- 6164,6170 ----
    "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 6488,6493 ****
--- 6517,6523 ----
    [(set_attr "isa" "*,sse2_noavx,avx")
     (set_attr "mmx_isa" "native,*,*")
     (set_attr "type" "mmxshft,sseiadd,sseiadd")
+    (set_attr "c86_attr" "sadbw")
     (set_attr "mode" "DI,TI,TI")])
  
  (define_expand "reduc_<code>_scal_<mode>"
***************
*** 6867,6872 ****
--- 6897,6903 ----
    "maskmovq\t{%2, %1|%1, %2}"
    [(set_attr "type" "mmxcvt")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "DI")])
  
  (define_int_iterator EMMS
diff -Nrcpad gcc-15-20260612/gcc/config/i386/sse.md gcc-15-20260619/gcc/config/i386/sse.md
*** gcc-15-20260612/gcc/config/i386/sse.md	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/i386/sse.md	Fri Jun 19 22:32:06 2026
***************
*** 1772,1777 ****
--- 1772,1782 ----
      }
  }
    [(set_attr "type" "ssemov")
+    (set (attr "c86_attr")
+      (if_then_else (and (match_test "REG_P (operands[1])")
+ 			(match_test "REGNO (operands[1]) != REGNO (operands[0])"))
+        (const_string "blend")
+        (const_string "*")))
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 1786,1791 ****
--- 1791,1797 ----
      vmovdqu<ssescalarsize>\t{%2, %0%{%3%}%N1|%0%{%3%}%N1, %2}
      vpblendm<sseintmodesuffix>\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "*,blend")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 2012,2017 ****
--- 2018,2024 ----
    "TARGET_SSE2"
    "movnti\t{%1, %0|%0, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "prefix_data16" "0")
     (set_attr "mode" "<MODE>")])
  
***************
*** 2023,2028 ****
--- 2030,2036 ----
    "TARGET_SSE"
    "%vmovnt<ssemodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "prefix" "maybe_vex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 2038,2043 ****
--- 2046,2052 ----
         (match_test "TARGET_AVX")
       (const_string "*")
       (const_string "1")))
+    (set_attr "c86_attr" "movnt")
     (set_attr "prefix" "maybe_vex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 2339,2344 ****
--- 2348,2354 ----
    "ktest<mskmodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "mode" "<MODE>")
     (set_attr "type" "msklog")
+    (set_attr "c86_decode" "vector")
     (set_attr "prefix" "vex")])
  
  (define_insn "*kortest<mode>"
***************
*** 2351,2356 ****
--- 2361,2367 ----
    "kortest<mskmodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "mode" "<MODE>")
     (set_attr "type" "msklog")
+    (set_attr "c86_decode" "vector")
     (set_attr "prefix" "vex")])
  
  (define_insn "kortest<mode>_ccc"
***************
*** 2919,2924 ****
--- 2930,2936 ----
     (set_attr "addr" "*,gpr16")
     (set_attr "atom_sse_attr" "rcp")
     (set_attr "btver2_sse_attr" "rcp")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "maybe_vex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 2938,2943 ****
--- 2950,2956 ----
     (set_attr "addr" "*,gpr16")
     (set_attr "atom_sse_attr" "rcp")
     (set_attr "btver2_sse_attr" "rcp")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "SF")])
  
***************
*** 2958,2963 ****
--- 2971,2977 ----
     (set_attr "addr" "*,gpr16")
     (set_attr "atom_sse_attr" "rcp")
     (set_attr "btver2_sse_attr" "rcp")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "SF")])
  
***************
*** 3007,3012 ****
--- 3021,3027 ----
    "TARGET_AVX512F"
    "vrcp14<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3021,3026 ****
--- 3036,3042 ----
    "TARGET_AVX512F"
    "vrcp14<ssescalarmodesuffix>\t{%1, %2, %0|%0, %2, %<iptr>1}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3038,3043 ****
--- 3054,3060 ----
    "TARGET_AVX512F"
    "vrcp14<ssescalarmodesuffix>\t{%1, %2, %0%{%4%}%N3|%0%{%4%}%N3, %2, %<iptr>1}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3073,3078 ****
--- 3090,3096 ----
     (set_attr "type" "sse")
     (set_attr "atom_sse_attr" "sqrt")
     (set_attr "btver2_sse_attr" "sqrt")
+    (set_attr "c86_attr" "sqrt")
     (set_attr "prefix" "maybe_vex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3092,3097 ****
--- 3110,3116 ----
     (set_attr "atom_sse_attr" "sqrt")
     (set_attr "prefix" "<round_scalar_prefix>")
     (set_attr "btver2_sse_attr" "sqrt")
+    (set_attr "c86_attr" "sqrt")
     (set_attr "mode" "<ssescalarmode>")])
  
  (define_insn "*<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>"
***************
*** 3111,3116 ****
--- 3130,3136 ----
     (set_attr "atom_sse_attr" "sqrt")
     (set_attr "prefix" "<round_scalar_prefix>")
     (set_attr "btver2_sse_attr" "sqrt")
+    (set_attr "c86_attr" "sqrt")
     (set_attr "mode" "<ssescalarmode>")])
  
  (define_expand "rsqrt<mode>2"
***************
*** 3161,3166 ****
--- 3181,3187 ----
    "TARGET_AVX512F"
    "vrsqrt14<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3175,3180 ****
--- 3196,3202 ----
    "TARGET_AVX512F"
    "vrsqrt14<ssescalarmodesuffix>\t{%1, %2, %0|%0, %2, %<iptr>1}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3192,3197 ****
--- 3214,3220 ----
    "TARGET_AVX512F"
    "vrsqrt14<ssescalarmodesuffix>\t{%1, %2, %0%{%4%}%N3|%0%{%4%}%N3, %2, %<iptr>1}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "rcp")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3316,3321 ****
--- 3339,3345 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseadd")
     (set_attr "btver2_sse_attr" "maxmin")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix" "<mask_prefix3>")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3403,3408 ****
--- 3427,3433 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseadd")
     (set_attr "btver2_sse_attr" "maxmin")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix" "<mask_prefix3>")
     (set_attr "mode" "<MODE>")])
  
***************
*** 3427,3432 ****
--- 3452,3458 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseadd")
     (set_attr "btver2_sse_attr" "maxmin")
+    (set_attr "c86_attr" "maxmin")
     (set (attr "prefix")
       (cond [(eq_attr "alternative" "0")
  	      (const_string "orig")
***************
*** 3474,3479 ****
--- 3500,3506 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sse")
     (set_attr "btver2_sse_attr" "maxmin")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix" "<round_saeonly_scalar_prefix>")
     (set_attr "mode" "<ssescalarmode>")])
  
***************
*** 3670,3675 ****
--- 3697,3703 ----
    "TARGET_AVX"
    "vh<plusminus_mnemonic>pd\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sseadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "gpr16")
     (set_attr "prefix" "vex")
     (set_attr "mode" "V4DF")])
***************
*** 3715,3720 ****
--- 3743,3749 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "addr" "*,gpr16")
     (set_attr "type" "sseadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "V2DF")])
  
***************
*** 3737,3742 ****
--- 3766,3772 ----
     vhsubpd\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "*,gpr16")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "V2DF")])
***************
*** 3757,3762 ****
--- 3787,3793 ----
     vhaddpd\t{%1, %1, %0|%0, %1, %1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "V2DF")])
  
***************
*** 3775,3780 ****
--- 3806,3812 ----
     vhsubpd\t{%1, %1, %0|%0, %1, %1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "V2DF")])
  
***************
*** 3818,3823 ****
--- 3850,3856 ----
    "TARGET_AVX"
    "vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sseadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "gpr16")
     (set_attr "prefix" "vex")
     (set_attr "mode" "V8SF")])
***************
*** 3849,3854 ****
--- 3882,3888 ----
     vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "*,gpr16")
     (set_attr "atom_unit" "complex")
     (set_attr "prefix" "orig,vex")
***************
*** 4028,4033 ****
--- 4062,4068 ----
    "TARGET_AVX512DQ || (VALID_AVX512FP16_REG_MODE (<MODE>mode))"
    "vreduce<ssemodesuffix>\t{%2, <round_saeonly_mask_op3>%1, %0<mask_operand3>|%0<mask_operand3>, %1<round_saeonly_mask_op3>, %2}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "aes")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 4044,4049 ****
--- 4079,4085 ----
    "TARGET_AVX512DQ || (VALID_AVX512FP16_REG_MODE (<MODE>mode))"
    "vreduce<ssescalarmodesuffix>\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %<iptr>2<round_saeonly_scalar_mask_op4>, %3}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "aes")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 4587,4592 ****
--- 4623,4629 ----
     vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}
     vptestnm<ssemodesuffix>\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}"
    [(set_attr "type" "ssecmp")
+    (set_attr "c86_attr" "*,ptest")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 4676,4681 ****
--- 4713,4719 ----
     vpcmpeq<ssemodesuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}
     vptestnm<ssemodesuffix>\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}"
    [(set_attr "type" "ssecmp")
+    (set_attr "c86_attr" "*,ptest")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 5284,5289 ****
--- 5322,5328 ----
    [(set_attr "isa" "noavx,avx_noavx512f,avx512dq,avx512f")
     (set_attr "addr" "*,gpr16,*,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "prefix" "orig,maybe_vex,evex,evex")
     (set (attr "mode")
  	(cond [(and (match_test "<mask_applied>")
***************
*** 5335,5340 ****
--- 5374,5380 ----
    return "";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "prefix" "evex")
     (set (attr "mode")
          (if_then_else (match_test "TARGET_AVX512DQ")
***************
*** 5411,5416 ****
--- 5451,5457 ----
  }
    [(set_attr "isa" "noavx,avx,avx512dq,avx512f")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "prefix" "orig,maybe_evex,evex,evex")
     (set (attr "mode")
  	(cond [(and (match_test "<mask_applied>")
***************
*** 5458,5463 ****
--- 5499,5505 ----
    return "";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "prefix" "evex")
     (set (attr "mode")
          (if_then_else (match_test "TARGET_AVX512DQ")
***************
*** 5575,5580 ****
--- 5617,5623 ----
  }
    [(set_attr "isa" "noavx,avx,avx512vl,avx512f_512")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "prefix" "orig,vex,evex,evex")
     (set (attr "mode")
  	(cond [(eq_attr "alternative" "2")
***************
*** 5705,5710 ****
--- 5748,5754 ----
  }
    [(set_attr "isa" "noavx,avx,avx512vl,avx512f_512")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "prefix" "orig,vex,evex,evex")
     (set (attr "mode")
  	(cond [(eq_attr "alternative" "2")
***************
*** 5767,5772 ****
--- 5811,5817 ----
  }
    [(set_attr "isa" "noavx,avx,avx512vl,avx512f_512")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set (attr "prefix_data16")
       (if_then_else
         (and (eq_attr "alternative" "0")
***************
*** 8517,8522 ****
--- 8562,8568 ----
     (set_attr "bdver1_decode" "double,direct,*")
     (set_attr "btver2_decode" "double,double,double")
     (set_attr "znver1_decode" "double,double,double")
+    (set_attr "c86_decode" "double,double,double")
     (set (attr "length_vex")
  	(if_then_else
  	  (and (match_test "<MODE>mode == DImode")
***************
*** 8978,8983 ****
--- 9024,9030 ----
     (set_attr "bdver1_decode" "double,direct,*")
     (set_attr "btver2_decode" "double,double,double")
     (set_attr "znver1_decode" "double,double,double")
+    (set_attr "c86_decode" "double,double,double")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "DF")])
  
***************
*** 11907,11912 ****
--- 11954,11963 ----
  	      (const_string "ssemov2")
  	   ]
  	   (const_string "ssemov")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "9,10,11")
+ 		   (const_string "insr")
+ 		   (const_string "*")))
     (set (attr "addr")
       (if_then_else (eq_attr "alternative" "9,10")
  		   (const_string "gpr16")
***************
*** 11981,11986 ****
--- 12032,12044 ----
       (if_then_else (eq_attr "alternative" "0,1,2,3,6,7,10")
  		   (const_string "ssemov")
  		   (const_string "sselog")))
+    (set (attr "c86_attr")
+ 	(cond [(eq_attr "alternative" "6,7,10")
+ 		 (const_string "blend")
+ 	       (eq_attr "alternative" "4,5,8,9,11,12")
+ 		 (const_string "insr")
+ 	      ]
+ 	      (const_string "*")))
     (set (attr "prefix_data16")
       (if_then_else (eq_attr "alternative" "4,5")
  		   (const_string "1")
***************
*** 12349,12354 ****
--- 12407,12413 ----
    [(set_attr "isa" "noavx,noavx,avx,noavx,avx")
     (set_attr "addr" "gpr16,gpr16,*,*,*")
     (set_attr "type" "sselog,sselog,sselog,*,*")
+    (set_attr "c86_attr" "extr,extr,extr,*,*")
     (set_attr "prefix_data16" "1,1,1,*,*")
     (set_attr "prefix_extra" "1,1,1,*,*")
     (set_attr "length_immediate" "1,1,1,*,*")
***************
*** 13252,13257 ****
--- 13311,13317 ----
    [(set_attr "isa" "*,sse4_noavx,avx,noavx,avx")
     (set_attr "addr" "*,gpr16,*,*,*")
     (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1")
+    (set_attr "c86_attr" "extr,extr,extr,other,other")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "TI")])
  
***************
*** 14042,14047 ****
--- 14102,14108 ----
    "TARGET_AVX512F"
    "valign<ssemodesuffix>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}";
    [(set_attr "prefix" "evex")
+    (set_attr "c86_attr" "shufx")
     (set_attr "mode" "<sseinsnmode>")])
  
  (define_mode_attr vec_extract_imm_predicate
***************
*** 16657,16662 ****
--- 16718,16724 ----
     "TARGET_AVX512BW && <mask_mode512bit_condition>"
     "vpmaddwd\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}";
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 16728,16733 ****
--- 16790,16796 ----
    "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
    "vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "prefix" "vex")
     (set_attr "mode" "OI")])
  
***************
*** 16786,16791 ****
--- 16849,16855 ----
     vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "atom_unit" "simul")
     (set_attr "prefix_data16" "1,*")
     (set_attr "prefix" "orig,vex")
***************
*** 17653,17658 ****
--- 17717,17723 ----
    "TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
    "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "vex")
     (set_attr "mode" "OI")])
***************
*** 17694,17699 ****
--- 17759,17765 ----
    "TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
    "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 17705,17710 ****
--- 17771,17777 ----
    "TARGET_AVX512BW && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
    "vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 17803,17808 ****
--- 17870,17876 ----
     vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix_extra" "1")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "prefix" "orig,orig,vex")
***************
*** 17819,17824 ****
--- 17887,17893 ----
     vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "addr" "gpr16,*")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "TI")])
***************
*** 17887,17892 ****
--- 17956,17962 ----
     vp<maxmin_int><ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "prefix_extra" "1,1,*")
     (set_attr "prefix" "orig,orig,vex")
***************
*** 17904,17909 ****
--- 17974,17980 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "maxmin")
     (set_attr "prefix" "orig,vex")
     (set_attr "mode" "TI")])
  
***************
*** 18559,18564 ****
--- 18630,18636 ----
    [(set_attr "isa" "noavx,avx_noavx512f,avx512f,*,*")
     (set_attr "addr" "*,gpr16,*,*,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set (attr "prefix_data16")
       (if_then_else
         (and (eq_attr "alternative" "0")
***************
*** 18666,18671 ****
--- 18738,18744 ----
    "TARGET_AVX512F"
    "vpandn<ssemodesuffix>\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}";
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 18790,18795 ****
--- 18863,18869 ----
    [(set_attr "isa" "noavx,avx_noavx512f,avx512f")
     (set_attr "addr" "*,gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set (attr "prefix_data16")
       (if_then_else
         (and (eq_attr "alternative" "0")
***************
*** 18887,18892 ****
--- 18961,18967 ----
    [(set_attr "isa" "noavx,avx_noavx512f,avx512f")
     (set_attr "addr" "*,gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set (attr "prefix_data16")
       (if_then_else
         (and (eq_attr "alternative" "0")
***************
*** 18923,18928 ****
--- 18998,19004 ----
     (set_attr "prefix" "orig,vex,evex")
     (set_attr "prefix_data16" "1,*,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "sselogic")
     (set_attr "mode" "TI")])
  
  (define_expand "one_cmplv1ti2"
***************
*** 19898,19903 ****
--- 19974,19980 ----
  }
    [(set_attr "isa" "noavx,noavx,avx,avx,<pinsr_evex_isa>,<pinsr_evex_isa>,avx2")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insr")
     (set (attr "addr")
  	(if_then_else (eq_attr "alternative" "0,1")
  		      (const_string "gpr16")
***************
*** 20011,20016 ****
--- 20088,20094 ----
      }
  }
    [(set_attr "type" "sselog,ssemov,ssemov")
+    (set_attr "c86_attr" "insertx,*,*")
     (set_attr "length_immediate" "1,0,0")
     (set_attr "prefix" "evex,vex,evex")
     (set_attr "mode" "<sseinsnmode>,<ssequarterinsnmode>,<ssequarterinsnmode>")])
***************
*** 20043,20048 ****
--- 20121,20127 ----
    return "vinsert<shuffletype><extract_suf>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 20081,20086 ****
--- 20160,20166 ----
    "TARGET_AVX512DQ"
    "vinsert<shuffletype>32x8\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x0}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 20098,20103 ****
--- 20178,20184 ----
    "TARGET_AVX512DQ"
    "vinsert<shuffletype>32x8\t{$0x1, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x1}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 20113,20118 ****
--- 20194,20200 ----
    "TARGET_AVX512F"
    "vinsert<shuffletype>64x4\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x0}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
***************
*** 20128,20133 ****
--- 20210,20216 ----
    "TARGET_AVX512F"
    "vinsert<shuffletype>64x4\t{$0x1, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x1}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
***************
*** 20177,20182 ****
--- 20260,20266 ----
    return "vshuf<shuffletype>64x2\t{%3, %2, %1, %0<mask_operand7>|%0<mask_operand7>, %1, %2, %3}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "shufx")
     (set_attr "addr" "gpr16,*")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
***************
*** 20240,20245 ****
--- 20324,20330 ----
    return "vshuf<shuffletype>64x2\t{%3, %2, %1, %0<mask_operand11>|%0<mask_operand11>, %1, %2, %3}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "shufx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 20276,20281 ****
--- 20361,20367 ----
    return "vshuf<shuffletype>64x2\t{%2, %1, %1, %0<mask_operand10>|%0<mask_operand10>, %1, %1, %2}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "shufx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 20339,20344 ****
--- 20425,20431 ----
    return "vshuf<shuffletype>32x4\t{%3, %2, %1, %0<mask_operand11>|%0<mask_operand11>, %1, %2, %3}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "shufx")
     (set_attr "addr" "gpr16,*")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
***************
*** 20426,20431 ****
--- 20513,20519 ----
    return "vshuf<shuffletype>32x4\t{%3, %2, %1, %0<mask_operand19>|%0<mask_operand19>, %1, %2, %3}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "shufx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 20478,20483 ****
--- 20566,20572 ----
    return "vshuf<shuffletype>32x4\t{%2, %1, %1, %0<mask_operand18>|%0<mask_operand18>, %1, %1, %2}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "shufx")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 21082,21087 ****
--- 21171,21177 ----
    [(set_attr "isa" "sse2_noavx,avx,sse4_noavx,avx")
     (set_attr "addr" "*,*,gpr16,*")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set (attr "prefix_extra")
       (if_then_else
         (eq (const_string "<MODE>mode") (const_string "V8HImode"))
***************
*** 21103,21108 ****
--- 21193,21199 ----
    "%vpextr<PEXTR_MODE12:ssemodesuffix>\t{%2, %1, %k0|%k0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set (attr "prefix_extra")
       (if_then_else
         (eq (const_string "<PEXTR_MODE12:MODE>mode") (const_string "V8HImode"))
***************
*** 21123,21128 ****
--- 21214,21220 ----
    "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 21257,21262 ****
--- 21349,21355 ----
  }
    [(set_attr "isa" "noavx,avx,avx512dq,noavx,noavx,avx")
     (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1,sseishft1")
+    (set_attr "c86_attr" "extr,extr,*,*,*,*")
     (set (attr "addr")
  	(if_then_else (eq_attr "alternative" "0")
  		      (const_string "gpr16")
***************
*** 21279,21284 ****
--- 21372,21378 ----
    "%vpextrd\t{%2, %1, %k0|%k0, %1, %2}"
    [(set_attr "isa" "noavx,avx,avx512dq")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "extr")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 21351,21356 ****
--- 21445,21454 ----
  	      (const_string "imov")
  	   ]
  	   (const_string "sselog1")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "0,1,2")
+ 		   (const_string "extr")
+ 		   (const_string "other")))
     (set (attr "addr")
  	(if_then_else (eq_attr "alternative" "0")
  		      (const_string "gpr16")
***************
*** 21516,21521 ****
--- 21614,21623 ----
  	      (const_string "mmxmov")
  	   ]
  	   (const_string "sselog")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "0,1,2,3")
+ 		   (const_string "insr")
+ 		   (const_string "other")))
     (set (attr "addr")
       (if_then_else (eq_attr "alternative" "0,1")
  		   (const_string "gpr16")
***************
*** 21674,21679 ****
--- 21776,21785 ----
         (eq_attr "alternative" "0,1,2,3,4,5")
         (const_string "sselog")
         (const_string "ssemov2")))
+    (set (attr "c86_attr")
+      (if_then_else (eq_attr "alternative" "0,1,2,3")
+ 		   (const_string "insr")
+ 		   (const_string "other")))
     (set (attr "addr")
       (if_then_else (eq_attr "alternative" "0,1")
  		   (const_string "gpr16")
***************
*** 21893,21898 ****
--- 21999,22005 ----
     vpavg<ssemodesuffix>\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "avg")
     (set_attr "prefix_data16" "1,*")
     (set_attr "prefix" "orig,<mask_prefix>")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 21921,21926 ****
--- 22028,22034 ----
     vpsadbw\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "sadbw")
     (set_attr "atom_unit" "simul")
     (set_attr "prefix_data16" "1,*")
     (set_attr "prefix" "orig,maybe_evex")
***************
*** 21935,21940 ****
--- 22043,22049 ----
    "%vmovmsk<ssemodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 21948,21953 ****
--- 22057,22063 ----
    "%vmovmsk<ssemodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "<MODE>")])
  
***************
*** 22085,22090 ****
--- 22195,22201 ----
    "%vpmovmskb\t{%1, %0|%0, %1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set (attr "prefix_data16")
       (if_then_else
         (match_test "TARGET_AVX")
***************
*** 22103,22108 ****
--- 22214,22220 ----
    "%vpmovmskb\t{%1, %k0|%k0, %1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set (attr "prefix_data16")
       (if_then_else
         (match_test "TARGET_AVX")
***************
*** 22121,22126 ****
--- 22233,22239 ----
    "%vpmovmskb\t{%1, %k0|%k0, %1}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set (attr "prefix_data16")
       (if_then_else
         (match_test "TARGET_AVX")
***************
*** 22470,22475 ****
--- 22583,22589 ----
    return "%vmaskmovdqu\t{%2, %1|%1, %2}";
  }
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "prefix_data16" "1")
     (set (attr "length_address")
       (symbol_ref ("Pmode != word_mode")))
***************
*** 22478,22483 ****
--- 22592,22598 ----
       (symbol_ref ("3 + REX_SSE_REGNO_P (REGNO (operands[2]))")))
     (set_attr "prefix" "maybe_vex")
     (set_attr "znver1_decode" "vector")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "TI")])
  
  (define_insn "sse_ldmxcsr"
***************
*** 22570,22575 ****
--- 22685,22691 ----
    "TARGET_AVX2"
    "vph<plusminus_mnemonic>w\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "vex")
***************
*** 22596,22601 ****
--- 22712,22718 ----
     vph<plusminus_mnemonic>w\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "gpr16")
     (set_attr "atom_unit" "complex")
     (set_attr "prefix_extra" "1")
***************
*** 22637,22642 ****
--- 22754,22760 ----
  }
    [(set_attr "mmx_isa" "native,sse_noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "atom_unit" "complex")
     (set_attr "prefix_extra" "1")
     (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
***************
*** 22660,22665 ****
--- 22778,22784 ----
    "TARGET_AVX2"
    "vph<plusminus_mnemonic>d\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "vex")
***************
*** 22684,22689 ****
--- 22803,22809 ----
     vph<plusminus_mnemonic>d\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "gpr16")
     (set_attr "atom_unit" "complex")
     (set_attr "prefix_data16" "1,*")
***************
*** 22724,22729 ****
--- 22844,22850 ----
  }
    [(set_attr "mmx_isa" "native,sse_noavx,avx")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "hplus")
     (set_attr "addr" "gpr16")
     (set_attr "atom_unit" "complex")
     (set_attr "prefix_extra" "1")
***************
*** 22780,22785 ****
--- 22901,22907 ----
    "TARGET_AVX2"
    "vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "vex")
     (set_attr "mode" "OI")])
***************
*** 22795,22800 ****
--- 22917,22923 ----
     "TARGET_AVX512BW"
     "vpmaddubsw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}";
    [(set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 22871,22876 ****
--- 22994,23000 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "atom_unit" "simul")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,vex")
***************
*** 22907,22912 ****
--- 23031,23037 ----
    [(set_attr "isa" "*,noavx,avx")
     (set_attr "mmx_isa" "native,*,*")
     (set_attr "type" "sseiadd")
+    (set_attr "c86_attr" "madd")
     (set_attr "atom_unit" "simul")
     (set_attr "prefix_extra" "1")
     (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
***************
*** 23190,23195 ****
--- 23315,23321 ----
     vpsign<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "sign")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,vex")
***************
*** 23209,23214 ****
--- 23335,23341 ----
    [(set_attr "isa" "*,noavx,avx")
     (set_attr "mmx_isa" "native,*,*")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "sign")
     (set_attr "prefix_extra" "1")
     (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
     (set_attr "mode" "DI,TI,TI")])
***************
*** 23358,23363 ****
--- 23485,23491 ----
     (set_attr "type" "sselog1")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_vex")
+    (set_attr "c86_attr" "abs")
     (set_attr "mode" "<sseinsnmode>")])
  
  (define_insn "abs<mode>2_mask"
***************
*** 23370,23375 ****
--- 23498,23504 ----
    "TARGET_AVX512F"
    "vpabs<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "abs")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 23383,23388 ****
--- 23512,23518 ----
    "TARGET_AVX512BW"
    "vpabs<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "abs")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 23415,23420 ****
--- 23545,23551 ----
    "TARGET_SSE4A"
    "movnt<ssemodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "mode" "<MODE>")])
  
  (define_insn "sse4a_vmmovnt<mode>"
***************
*** 23427,23432 ****
--- 23558,23564 ----
    "TARGET_SSE4A"
    "movnt<ssescalarmodesuffix>\t{%1, %0|%0, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "mode" "<ssescalarmode>")])
  
  (define_insn "sse4a_extrqi"
***************
*** 23503,23508 ****
--- 23635,23641 ----
     vblend<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "addr" "gpr16")
     (set_attr "length_immediate" "1")
     (set_attr "prefix_data16" "1,1,*")
***************
*** 23524,23529 ****
--- 23657,23663 ----
     vblendv<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blendv")
     (set_attr "addr" "gpr16")
     (set_attr "length_immediate" "1")
     (set_attr "prefix_data16" "1,1,*")
***************
*** 23557,23562 ****
--- 23691,23697 ----
  }
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blendv")
     (set_attr "length_immediate" "1")
     (set_attr "prefix_data16" "1,1,*")
     (set_attr "prefix_extra" "1")
***************
*** 23769,23774 ****
--- 23904,23910 ----
     (set_attr "prefix" "orig,orig,vex")
     (set_attr "btver2_decode" "vector,vector,vector")
     (set_attr "znver1_decode" "vector,vector,vector")
+    (set_attr "c86_decode" "vector,vector,vector")
     (set_attr "mode" "<MODE>")])
  
  ;; Mode attribute used by `vmovntdqa' pattern
***************
*** 23784,23789 ****
--- 23920,23926 ----
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "movnt")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 23808,23813 ****
--- 23945,23951 ----
     (set_attr "prefix" "orig,orig,vex")
     (set_attr "btver2_decode" "vector,vector,vector")
     (set_attr "znver1_decode" "vector,vector,vector")
+    (set_attr "c86_decode" "vector,vector,vector")
     (set_attr "mode" "<sseinsnmode>")])
  
  (define_insn "avx10_2_mpsadbw<mask_name>"
***************
*** 23867,23872 ****
--- 24005,24011 ----
     vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blendv")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "*,*,1")
***************
*** 24008,24013 ****
--- 24147,24153 ----
     vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 24080,24085 ****
--- 24220,24226 ----
    return "vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}";
  }
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 24095,24100 ****
--- 24236,24242 ----
    "TARGET_AVX2"
    "vpblendd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "blend")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 24121,24126 ****
--- 24263,24269 ----
    "TARGET_AVX2 && <mask_avx512bw_condition> && <mask_avx512vl_condition>"
    "vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 24175,24180 ****
--- 24318,24324 ----
    "TARGET_AVX512BW && TARGET_EVEX512"
    "vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 24234,24239 ****
--- 24378,24384 ----
    "%vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 24250,24255 ****
--- 24395,24401 ----
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 24396,24401 ****
--- 24542,24548 ----
    "TARGET_AVX512F && TARGET_EVEX512"
    "vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 24417,24422 ****
--- 24564,24570 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 24428,24433 ****
--- 24576,24582 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "%vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 24505,24510 ****
--- 24654,24660 ----
    "%vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 24518,24523 ****
--- 24668,24674 ----
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 24595,24600 ****
--- 24746,24752 ----
    "TARGET_AVX512F && TARGET_EVEX512"
    "vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 24648,24653 ****
--- 24800,24806 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 24707,24712 ****
--- 24860,24866 ----
    "%vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 24720,24725 ****
--- 24874,24880 ----
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 24864,24869 ****
--- 25019,25025 ----
    "TARGET_AVX512F && TARGET_EVEX512"
    "vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 24874,24879 ****
--- 25030,25036 ----
    "TARGET_AVX512F && TARGET_EVEX512"
    "vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 24947,24952 ****
--- 25104,25110 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 24958,24963 ****
--- 25116,25122 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 25038,25043 ****
--- 25197,25203 ----
    "%vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 25051,25056 ****
--- 25211,25217 ----
    [(set_attr "isa" "noavx,avx")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 25100,25105 ****
--- 25261,25267 ----
    "TARGET_AVX512F && TARGET_EVEX512"
    "vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 25119,25124 ****
--- 25281,25287 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 25130,25135 ****
--- 25293,25299 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_evex")
     (set_attr "mode" "OI")])
***************
*** 25202,25207 ****
--- 25366,25372 ----
    "%vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 25215,25220 ****
--- 25380,25386 ----
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 25290,25295 ****
--- 25456,25462 ----
    "TARGET_AVX512F && TARGET_EVEX512"
    "vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 25341,25346 ****
--- 25508,25514 ----
    "TARGET_AVX2 && <mask_avx512vl_condition>"
    "vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix" "maybe_evex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "OI")])
***************
*** 25396,25401 ****
--- 25564,25570 ----
    "%vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 25409,25414 ****
--- 25578,25584 ----
    [(set_attr "isa" "noavx,noavx,avx")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "type" "ssemov")
+    (set_attr "c86_attr" "vpmovx")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,orig,maybe_evex")
     (set_attr "mode" "TI")])
***************
*** 25831,25836 ****
--- 26001,26007 ----
  }
    [(set_attr "isa" "noavx,noavx,noavx512f,avx512f")
     (set_attr "type" "ssecvt")
+    (set_attr "c86_attr" "aes")
     (set_attr "addr" "gpr16,gpr16,gpr16,*")
     (set_attr "length_immediate" "1")
     (set_attr "prefix_data16" "1,1,*,*")
***************
*** 25868,25873 ****
--- 26039,26045 ----
  }
    [(set_attr "isa" "noavx,noavx,noavx512f,avx512f")
     (set_attr "type" "ssecvt")
+    (set_attr "c86_attr" "aes")
     (set_attr "addr" "gpr16,gpr16,gpr16,*")
     (set_attr "length_immediate" "1")
     (set_attr "prefix_data16" "1,1,*,*")
***************
*** 26137,26142 ****
--- 26309,26315 ----
    "TARGET_SSE4_2"
    "%vpcmpestri\t{%5, %3, %1|%1, %3, %5}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "cmpestr")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 26165,26170 ****
--- 26338,26344 ----
    "TARGET_SSE4_2"
    "%vpcmpestrm\t{%5, %3, %1|%1, %3, %5}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "cmpestr")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 26191,26196 ****
--- 26365,26371 ----
     %vpcmpestri\t{%6, %4, %2|%2, %4, %6}
     %vpcmpestri\t{%6, %4, %2|%2, %4, %6}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "cmpestr")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 26268,26273 ****
--- 26443,26449 ----
    "TARGET_SSE4_2"
    "%vpcmpistri\t{%3, %2, %1|%1, %2, %3}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "cmpestr")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 26292,26297 ****
--- 26468,26474 ----
    "TARGET_SSE4_2"
    "%vpcmpistrm\t{%3, %2, %1|%1, %2, %3}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "cmpestr")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 26316,26321 ****
--- 26493,26499 ----
     %vpcmpistri\t{%4, %3, %2|%2, %3, %4}
     %vpcmpistri\t{%4, %3, %2|%2, %3, %4}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "cmpestr")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 26502,26507 ****
--- 26680,26686 ----
    "TARGET_XOP"
    "vphadd<u>bw\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 26534,26539 ****
--- 26713,26719 ----
    "TARGET_XOP"
    "vphadd<u>bd\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 26582,26587 ****
--- 26762,26768 ----
    "TARGET_XOP"
    "vphadd<u>bq\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 26602,26607 ****
--- 26783,26789 ----
    "TARGET_XOP"
    "vphadd<u>wd\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 26630,26635 ****
--- 26812,26818 ----
    "TARGET_XOP"
    "vphadd<u>wq\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 26648,26653 ****
--- 26831,26837 ----
    "TARGET_XOP"
    "vphadd<u>dq\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 26672,26677 ****
--- 26856,26862 ----
    "TARGET_XOP"
    "vphsubbw\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 26692,26697 ****
--- 26877,26883 ----
    "TARGET_XOP"
    "vphsubwd\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 26710,26715 ****
--- 26896,26902 ----
    "TARGET_XOP"
    "vphsubdq\t{%1, %0|%0, %1}"
    [(set_attr "type" "sseiadd1")
+    (set_attr "c86_attr" "hplus")
     (set_attr "prefix" "vex")
     (set_attr "prefix_extra" "1")
     (set_attr "mode" "TI")])
***************
*** 27343,27348 ****
--- 27530,27536 ----
     vaesenc\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx,vaes_avx512vl")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "aes")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,maybe_evex,evex")
***************
*** 27361,27366 ****
--- 27549,27555 ----
     vaesenclast\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx,vaes_avx512vl")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "aes")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,maybe_evex,evex")
***************
*** 27379,27384 ****
--- 27568,27574 ----
     vaesdec\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "isa" "noavx,avx,vaes_avx512vl")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "aes")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,maybe_evex,evex")
***************
*** 27398,27403 ****
--- 27588,27594 ----
    [(set_attr "isa" "noavx,avx,vaes_avx512vl")
     (set_attr "addr" "gpr16,gpr16,*")
     (set_attr "type" "sselog1")
+    (set_attr "c86_attr" "aes")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "orig,maybe_evex,evex")
     (set_attr "btver2_decode" "double,double,double")
***************
*** 27410,27415 ****
--- 27601,27607 ----
    "TARGET_AES"
    "%vaesimc\t{%1, %0|%0, %1}"
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "aes")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "maybe_vex")
***************
*** 27423,27428 ****
--- 27615,27621 ----
    "TARGET_AES"
    "%vaeskeygenassist\t{%2, %1, %0|%0, %1, %2}"
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "aes")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 27446,27451 ****
--- 27639,27645 ----
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "orig,vex,evex")
+    (set_attr "c86_decode" "*,vector,vector")
     (set_attr "mode" "TI")])
  
  (define_expand "avx_vzeroall"
***************
*** 27563,27568 ****
--- 27757,27763 ----
    return "vperm<ssemodesuffix>\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm")
     (set_attr "prefix" "<mask_prefix2>")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 27575,27580 ****
--- 27770,27776 ----
    "TARGET_AVX512VBMI && <mask_mode512bit_condition>"
    "vperm<ssemodesuffix>\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm")
     (set_attr "prefix" "<mask_prefix2>")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 27587,27592 ****
--- 27783,27789 ----
    "TARGET_AVX512BW && <mask_mode512bit_condition>"
    "vpermw\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm")
     (set_attr "prefix" "<mask_prefix2>")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 27805,27810 ****
--- 28002,28008 ----
    return "vperm<ssemodesuffix>\t{%2, %1, %0<mask_operand6>|%0<mask_operand6>, %1, %2}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm")
     (set_attr "prefix" "<mask_prefix2>")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 27880,27885 ****
--- 28078,28084 ----
    return "vperm<ssemodesuffix>\t{%2, %1, %0<mask_operand10>|%0<mask_operand10>, %1, %2}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm")
     (set_attr "prefix" "<mask_prefix2>")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 27986,27991 ****
--- 28185,28191 ----
     vshuf<shuffletype>32x4\t{$0x0, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x0}
     vbroadcast<shuffletype>32x4\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "shufx,*")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 27998,28003 ****
--- 28198,28204 ----
     vshuf<shuffletype>64x2\t{$0x44, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x44}
     vbroadcast<shuffletype>64x4\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "shufx,*")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28251,28256 ****
--- 28452,28458 ----
     vinsert<shuffletype>32x4\t{$1, %1, %0, %0|%0, %0, %1, 1}"
    [(set_attr "isa" "noavx512vl,*,*,avx512dq,avx512dq,avx512vl,avx512vl")
     (set_attr "type" "ssemov,sselog1,sselog1,ssemov,sselog1,ssemov,sselog1")
+    (set_attr "c86_attr" "*,insertx,*,*,insertx,*,insertx")
     (set (attr "addr")
  	(if_then_else (eq_attr "alternative" "0")
  		      (const_string "gpr16")
***************
*** 28294,28299 ****
--- 28496,28502 ----
     vshuf<shuffletype>32x4\t{$0x0, %t1, %t1, %0<mask_operand2>|%0<mask_operand2>, %t1, %t1, 0x0}
     vbroadcast<shuffletype>32x4\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "shufx,*")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 28307,28312 ****
--- 28510,28516 ----
     vshuf<shuffletype>32x4\t{$0x44, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x44}
     vbroadcast<shuffletype>32x8\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "shufx,*")
     (set_attr "length_immediate" "1,*")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 28325,28330 ****
--- 28529,28535 ----
     vshuf<shuffletype>64x2\t{$0x0, %<xtg_mode>1, %<xtg_mode>1, %0<mask_operand2>|%0<mask_operand2>, %<xtg_mode>1, %<xtg_mode>1, 0x0}
     vbroadcast<shuffletype>64x2\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "shufx,*")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 28423,28428 ****
--- 28628,28634 ----
    "TARGET_AVX512F"
    "vpermi2<ssemodesuffix>\t{%3, %1, %0%{%4%}|%0%{%4%}, %1, %3}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm2")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28439,28444 ****
--- 28645,28651 ----
    "TARGET_AVX512F"
    "vpermi2<ssemodesuffix>\t{%3, %1, %0%{%4%}|%0%{%4%}, %1, %3}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm2")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28468,28473 ****
--- 28675,28681 ----
     vpermt2<ssemodesuffix>\t{%3, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %3}
     vpermi2<ssemodesuffix>\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm2")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28499,28504 ****
--- 28707,28713 ----
    "TARGET_AVX512F"
    "vpermt2<ssemodesuffix>\t{%3, %1, %0%{%4%}|%0%{%4%}, %1, %3}"
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "perm2")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 28577,28582 ****
--- 28786,28792 ----
    return "vperm2<i128>\t{%3, %2, %1, %0|%0, %1, %2, %3}";
  }
    [(set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 28684,28689 ****
--- 28894,28900 ----
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "vex")
***************
*** 28708,28713 ****
--- 28919,28925 ----
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "vex")
***************
*** 28731,28736 ****
--- 28943,28949 ----
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "vex")
***************
*** 28754,28759 ****
--- 28967,28973 ----
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "vex")
***************
*** 28776,28781 ****
--- 28990,28996 ----
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "vex,evex")
***************
*** 28798,28803 ****
--- 29013,29019 ----
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "addr" "gpr16,*")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "vex,evex")
***************
*** 28823,28828 ****
--- 29039,29045 ----
     vinserti32x4\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "addr" "gpr16,*")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
***************
*** 28850,28855 ****
--- 29067,29073 ----
    [(set_attr "isa" "noavx512vl,avx512vl")
     (set_attr "addr" "gpr16")
     (set_attr "type" "sselog")
+    (set_attr "c86_attr" "insertx")
     (set_attr "prefix_extra" "1")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "vex,evex")
***************
*** 28869,28874 ****
--- 29087,29093 ----
      return "vmaskmov<ssefltmodesuffix>\t{%1, %2, %0|%0, %2, %1}";
  }
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "blend")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "vex")
***************
*** 28890,28895 ****
--- 29109,29115 ----
      return "vmaskmov<ssefltmodesuffix>\t{%2, %1, %0|%0, %1, %2}";
  }
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "blend")
     (set_attr "addr" "gpr16")
     (set_attr "prefix_extra" "1")
     (set_attr "prefix" "vex")
***************
*** 29286,29291 ****
--- 29506,29512 ----
    [(set_attr "isa" "noavx512f,avx512f,*,*")
     (set_attr "addr" "gpr16,*,*,*")
     (set_attr "type" "sselog,sselog,ssemov,ssemov")
+    (set_attr "c86_attr" "insertx,insertx,*,*")
     (set_attr "prefix_extra" "1,1,*,*")
     (set_attr "length_immediate" "1,1,*,*")
     (set_attr "prefix" "maybe_evex")
***************
*** 29896,29901 ****
--- 30117,30123 ----
    "TARGET_AVX512F"
    "v<sseintprefix>compress<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "compress")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 29909,29914 ****
--- 30131,30137 ----
    "TARGET_AVX512VBMI2"
    "vpcompress<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "compress")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 29922,29927 ****
--- 30145,30151 ----
    "TARGET_AVX512F"
    "v<sseintprefix>compress<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "compress")
     (set_attr "prefix" "evex")
     (set_attr "memory" "store")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 29936,29941 ****
--- 30160,30166 ----
    "TARGET_AVX512VBMI2"
    "vpcompress<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "compress")
     (set_attr "prefix" "evex")
     (set_attr "memory" "store")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 29960,29965 ****
--- 30185,30191 ----
    "TARGET_AVX512F"
    "v<sseintprefix>expand<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "expand")
     (set_attr "prefix" "evex")
     (set_attr "memory" "none,load")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 29974,29979 ****
--- 30200,30206 ----
    "TARGET_AVX512VBMI2"
    "v<sseintprefix>expand<ssemodesuffix>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
    [(set_attr "type" "ssemov")
+    (set_attr "c86_attr" "expand")
     (set_attr "prefix" "evex")
     (set_attr "memory" "none,load")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 30166,30171 ****
--- 30393,30399 ----
     "TARGET_AVX512BW"
    "vdbpsadbw\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}"
    [(set_attr "type" "sselog1")
+    (set_attr "c86_attr" "sadbw")
     (set_attr "length_immediate" "1")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 30177,30182 ****
--- 30405,30411 ----
    "TARGET_AVX512CD"
    "vplzcnt<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "sse")
+    (set_attr "c86_attr" "abs")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 30189,30194 ****
--- 30418,30424 ----
    "vpconflict<ssemodesuffix>\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
    [(set_attr "type" "sse")
     (set_attr "prefix" "evex")
+    (set_attr "c86_decode" "vector")
     (set_attr "mode" "<sseinsnmode>")])
  
  (define_insn "sha1msg1"
***************
*** 30451,30456 ****
--- 30681,30687 ----
    "TARGET_AVX512IFMA && TARGET_EVEX512"
    "vpmadd52<vpmadd52type>\t{%3, %2, %0|%0, %2, %3}"
    [(set_attr "type" "ssemuladd")
+    (set_attr "c86_attr" "madd")
     (set_attr "prefix" "evex")
     (set_attr "mode" "XI")])
  
***************
*** 30467,30472 ****
--- 30698,30704 ----
    vpmadd52<vpmadd52type>\t{%3, %2, %0|%0, %2, %3}"
    [(set_attr "isa" "avxifma,avx512ifmavl")
     (set_attr "type" "ssemuladd")
+    (set_attr "c86_attr" "madd")
     (set_attr "addr" "gpr16,*")
     (set_attr "prefix" "vex,evex")
     (set_attr "mode" "<sseinsnmode>")])
***************
*** 30484,30489 ****
--- 30716,30722 ----
    "TARGET_AVX512IFMA"
    "vpmadd52<vpmadd52type>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3}"
    [(set_attr "type" "ssemuladd")
+    (set_attr "c86_attr" "madd")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 30500,30505 ****
--- 30733,30739 ----
    "TARGET_AVX512IFMA"
    "vpmadd52<vpmadd52type>\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}"
    [(set_attr "type" "ssemuladd")
+    (set_attr "c86_attr" "madd")
     (set_attr "prefix" "evex")
     (set_attr "mode" "<sseinsnmode>")])
  
***************
*** 31103,31108 ****
--- 31337,31343 ----
  }
  [(set_attr "isa" "avx,vaes_avx512vl")
   (set_attr "type" "sselog1")
+  (set_attr "c86_attr" "aes")
   (set_attr "addr" "gpr16,*")
   (set_attr "mode" "TI")])
  
***************
*** 31121,31126 ****
--- 31356,31362 ----
  }
  [(set_attr "isa" "avx,vaes_avx512vl")
   (set_attr "type" "sselog1")
+  (set_attr "c86_attr" "aes")
   (set_attr "addr" "gpr16,*")
   (set_attr "mode" "TI")])
  
***************
*** 31139,31144 ****
--- 31375,31381 ----
  }
  [(set_attr "isa" "avx,vaes_avx512vl")
   (set_attr "type" "sselog1")
+  (set_attr "c86_attr" "aes")
   (set_attr "addr" "gpr16,*")
   (set_attr "mode" "TI")])
  
***************
*** 31157,31162 ****
--- 31394,31400 ----
  }
  [(set_attr "isa" "avx,vaes_avx512vl")
   (set_attr "type" "sselog1")
+  (set_attr "c86_attr" "aes")
   (set_attr "addr" "gpr16,*")
   (set_attr "mode" "TI")])
  
diff -Nrcpad gcc-15-20260612/gcc/config/i386/x86-tune-costs.h gcc-15-20260619/gcc/config/i386/x86-tune-costs.h
*** gcc-15-20260612/gcc/config/i386/x86-tune-costs.h	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/i386/x86-tune-costs.h	Fri Jun 19 22:32:06 2026
*************** struct processor_costs core_cost = {
*** 4065,4067 ****
--- 4065,4338 ----
    COSTS_N_INSNS (2),			/* Branch mispredict scale.  */
  };
  
+ /*  C86_4G_M4 has optimized REP instruction for medium sized blocks, but for
+     very small blocks it is better to use loop.  For large blocks, libcall
+     can do nontemporary accesses and beat inline considerably.  */
+ static stringop_algs c86_4g_m4_memcpy[2] = {
+   /* 32-bit tuning.  */
+   {libcall, {{6, loop, false},
+ 	     {14, unrolled_loop, false},
+ 	     {-1, libcall, false}}},
+   /* 64-bit tuning.  */
+   {libcall, {{16, loop, false},
+ 	     {128, rep_prefix_8_byte, false},
+ 	     {-1, libcall, false}}}};
+ static stringop_algs c86_4g_m4_memset[2] = {
+   /* 32-bit tuning.  */
+   {libcall, {{8, loop, false},
+ 	     {24, unrolled_loop, false},
+ 	     {128, rep_prefix_4_byte, false},
+ 	     {-1, libcall, false}}},
+   /* 64-bit tuning.  */
+   {libcall, {{48, unrolled_loop, false},
+ 	     {128, rep_prefix_8_byte, false},
+ 	     {-1, libcall, false}}}};
+ static const
+ struct processor_costs c86_4g_m4_cost = {
+   {
+   /* Start of register allocator costs.  integer->integer move cost is 2.  */
+ 
+   /* reg-reg moves are done by renaming and thus they are even cheaper than
+      1 cycle.  Because reg-reg move cost is 2 and the following tables
+      correspond to doubles of latencies, we do not model this correctly.
+      It does not seem to make practical difference to bump prices up even
+      more.  */
+   6,					/* cost for loading QImode using
+ 					   movzbl.  */
+   {6, 6, 6},				/* cost of loading integer registers
+ 					   in QImode, HImode and SImode.
+ 					   Relative to reg-reg move (2).  */
+   {8, 8, 8},				/* cost of storing integer
+ 					   registers.  */
+   2,					/* cost of reg,reg fld/fst.  */
+   {6, 6, 16},				/* cost of loading fp registers
+ 					   in SFmode, DFmode and XFmode.  */
+   {8, 8, 16},				/* cost of storing fp registers
+ 					   in SFmode, DFmode and XFmode.  */
+   2,					/* cost of moving MMX register.  */
+   {6, 6},				/* cost of loading MMX registers
+ 					   in SImode and DImode.  */
+   {8, 8},				/* cost of storing MMX registers
+ 					   in SImode and DImode.  */
+   2, 3, 6,				/* cost of moving XMM,YMM,ZMM register.  */
+   {6, 6, 6, 12, 24},			/* cost of loading SSE registers
+ 					   in 32,64,128,256 and 512-bit.  */
+   {8, 8, 8, 16, 32},			/* cost of storing SSE registers
+ 					   in 32,64,128,256 and 512-bit.  */
+   6, 6,				/* SSE->integer and integer->SSE moves.  */
+   8, 8,				/* mask->integer and integer->mask moves */
+   {6, 6, 6},				/* cost of loading mask register
+ 					   in QImode, HImode, SImode.  */
+   {8, 8, 8},				/* cost if storing mask register
+ 					   in QImode, HImode, SImode.  */
+   2,					/* cost of moving mask register.  */
+   /* End of register allocator costs.  */
+   },
+ 
+   COSTS_N_INSNS (1),			/* cost of an add instruction.  */
+   COSTS_N_INSNS (1),			/* cost of a lea instruction.  */
+   COSTS_N_INSNS (1),			/* variable shift costs.  */
+   COSTS_N_INSNS (1),			/* constant shift costs.  */
+   {COSTS_N_INSNS (3),			/* cost of starting multiply for QI.  */
+    COSTS_N_INSNS (3),			/*				 HI.  */
+    COSTS_N_INSNS (3),			/*				 SI.  */
+    COSTS_N_INSNS (3),			/*				 DI.  */
+    COSTS_N_INSNS (3)},			/*			      other.  */
+   0,					/* cost of multiply per each bit
+ 					    set.  */
+    /* Depending on parameters, idiv can get faster on HYGON.  This is upper
+       bound.  */
+   {COSTS_N_INSNS (16),			/* cost of a divide/mod for QI.  */
+    COSTS_N_INSNS (22),			/*			    HI.  */
+    COSTS_N_INSNS (30),			/*			    SI.  */
+    COSTS_N_INSNS (45),			/*			    DI.  */
+    COSTS_N_INSNS (45)},			/*			    other.  */
+   COSTS_N_INSNS (1),			/* cost of movsx.  */
+   COSTS_N_INSNS (1),			/* cost of movzx.  */
+   8,					/* "large" insn.  */
+   9,					/* MOVE_RATIO.  */
+   6,					/* CLEAR_RATIO */
+   {6, 6, 6},				/* cost of loading integer registers
+ 					   in QImode, HImode and SImode.
+ 					   Relative to reg-reg move (2).  */
+   {8, 8, 8},				/* cost of storing integer
+ 					   registers.  */
+   {6, 6, 6, 12, 24},			/* cost of loading SSE register
+ 					   in 32bit, 64bit, 128bit, 256bit and 512bit */
+   {8, 8, 8, 16, 32},			/* cost of storing SSE register
+ 					   in 32bit, 64bit, 128bit, 256bit and 512bit */
+   {6, 6, 6, 12, 24},			/* cost of unaligned loads.  */
+   {8, 8, 8, 16, 32},			/* cost of unaligned stores.  */
+   2, 3, 6,				/* cost of moving XMM,YMM,ZMM register.  */
+   6,					/* cost of moving SSE register to integer.  */
+ 
+   18, 8,				/* Gather load static, per_elt.  */
+   18, 10,				/* Gather store static, per_elt.  */
+   32,					/* size of l1 cache.  */
+   512,					/* size of l2 cache.  */
+   64,					/* size of prefetch block.  */
+   /* C86_4G_M4 processors never drop prefetches; if they cannot be performed
+      immediately, they are queued.  We set number of simultaneous prefetches
+      to a large constant to reflect this (it probably is not a good idea not
+      to limit number of prefetches at all, as their execution also takes some
+      time).  */
+   100,					/* number of parallel prefetches.  */
+   3,					/* Branch cost.  */
+   COSTS_N_INSNS (5),			/* cost of FADD and FSUB insns.  */
+   COSTS_N_INSNS (5),			/* cost of FMUL instruction.  */
+ 
+   COSTS_N_INSNS (15),			/* cost of FDIV instruction.  */
+   COSTS_N_INSNS (1),			/* cost of FABS instruction.  */
+   COSTS_N_INSNS (1),			/* cost of FCHS instruction.  */
+ 
+   COSTS_N_INSNS (10),			/* cost of FSQRT instruction.  */
+ 
+   COSTS_N_INSNS (1),			/* cost of cheap SSE instruction.  */
+   COSTS_N_INSNS (3),			/* cost of ADDSS/SD SUBSS/SD insns.  */
+   COSTS_N_INSNS (3),			/* cost of MULSS instruction.  */
+   COSTS_N_INSNS (4),			/* cost of MULSD instruction.  */
+   COSTS_N_INSNS (5),			/* cost of FMA SS instruction.  */
+   COSTS_N_INSNS (5),			/* cost of FMA SD instruction.  */
+   COSTS_N_INSNS (10),			/* cost of DIVSS instruction.  */
+ 
+   COSTS_N_INSNS (13),			/* cost of DIVSD instruction.  */
+   COSTS_N_INSNS (10),			/* cost of SQRTSS instruction.  */
+   COSTS_N_INSNS (15),			/* cost of SQRTSD instruction.  */
+ 
+   4, 4, 3, 6,				/* reassoc int, fp, vec_int, vec_fp.  */
+   c86_4g_m4_memcpy,
+   c86_4g_m4_memset,
+   COSTS_N_INSNS (4),			/* cond_taken_branch_cost.  */
+   COSTS_N_INSNS (2),			/* cond_not_taken_branch_cost.  */
+   "16",					/* Loop alignment.  */
+   "16",					/* Jump alignment.  */
+   "0:0:8",				/* Label alignment.  */
+   "16",					/* Func alignment.  */
+   4,					/* Small unroll limit.  */
+   2,					/* Small unroll factor.  */
+   COSTS_N_INSNS (2),			/* Branch mispredict scale.  */
+ };
+ 
+ struct processor_costs c86_4g_m6_cost = c86_4g_m4_cost;
+ 
+ struct processor_costs c86_4g_m7_cost = {
+   {
+   /* Start of register allocator costs.  integer->integer move cost is 2.  */
+ 
+   /* reg-reg moves are done by renaming and thus they are even cheaper than
+      1 cycle.  Because reg-reg move cost is 2 and following tables correspond
+      to doubles of latencies, we do not model this correctly.  It does not
+      seem to make practical difference to bump prices up even more.  */
+   6,					/* cost for loading QImode using
+ 					   movzbl.  */
+   {6, 6, 6},				/* cost of loading integer registers
+ 					   in QImode, HImode and SImode.
+ 					   Relative to reg-reg move (2).  */
+   {8, 8, 8},				/* cost of storing integer
+ 					   registers.  */
+   2,					/* cost of reg,reg fld/fst.  */
+   {14, 14, 17},				/* cost of loading fp registers
+ 					   in SFmode, DFmode and XFmode.  */
+   {12, 12, 16},				/* cost of storing fp registers
+ 					   in SFmode, DFmode and XFmode.  */
+   2,					/* cost of moving MMX register.  */
+   {6, 6},				/* cost of loading MMX registers
+ 					   in SImode and DImode.  */
+   {8, 8},				/* cost of storing MMX registers
+ 					   in SImode and DImode.  */
+   2, 2, 3,				/* cost of moving XMM,YMM,ZMM
+ 					   register.  */
+   {6, 6, 10, 10, 12},			/* cost of loading SSE registers
+ 					   in 32,64,128,256 and 512-bit.  */
+   {8, 8, 8, 12, 12},			/* cost of storing SSE registers
+ 					   in 32,64,128,256 and 512-bit.  */
+   6, 8,					/* SSE->integer and integer->SSE
+ 					   moves.  */
+   8, 8,					/* mask->integer and integer->mask moves */
+   {6, 6, 6},				/* cost of loading mask register
+ 					   in QImode, HImode, SImode.  */
+   {8, 8, 8},				/* cost if storing mask register
+ 					   in QImode, HImode, SImode.  */
+   2,					/* cost of moving mask register.  */
+   /* End of register allocator costs.  */
+   },
+ 
+   COSTS_N_INSNS (1),			/* cost of an add instruction.  */
+ 
+   COSTS_N_INSNS (1),			/* cost of a lea instruction.  */
+   COSTS_N_INSNS (1),			/* variable shift costs.  */
+   COSTS_N_INSNS (1),			/* constant shift costs.  */
+   {COSTS_N_INSNS (3),			/* cost of starting multiply for QI.  */
+    COSTS_N_INSNS (3),			/* 				 HI.  */
+    COSTS_N_INSNS (3),			/*				 SI.  */
+    COSTS_N_INSNS (3),			/*				 DI.  */
+    COSTS_N_INSNS (3)},			/*			other.  */
+   0,					/* cost of multiply per each bit
+ 					   set.  */
+   {COSTS_N_INSNS (15),			/* cost of a divide/mod for QI.  */
+    COSTS_N_INSNS (17),			/* 			    HI.  */
+    COSTS_N_INSNS (25),			/*			    SI.  */
+    COSTS_N_INSNS (41),			/*			    DI.  */
+    COSTS_N_INSNS (41)},			/*			    other.  */
+   COSTS_N_INSNS (1),			/* cost of movsx.  */
+   COSTS_N_INSNS (1),			/* cost of movzx.  */
+   8,					/* "large" insn.  */
+   9,					/* MOVE_RATIO.  */
+   6,					/* CLEAR_RATIO */
+   {6, 6, 6},				/* cost of loading integer registers
+ 					   in QImode, HImode and SImode.
+ 					   Relative to reg-reg move (2).  */
+   {8, 8, 8},				/* cost of storing integer
+ 					   registers.  */
+   {6, 6, 10, 10, 12},			/* cost of loading SSE registers
+ 					   in 32bit, 64bit, 128bit, 256bit and 512bit */
+   {8, 8, 8, 12, 12},			/* cost of storing SSE register
+ 					   in 32bit, 64bit, 128bit, 256bit and 512bit */
+   {6, 6, 10, 10, 12},			/* cost of unaligned loads.  */
+   {8, 8, 8, 12, 12},			/* cost of unaligned stores.  */
+   2, 2, 3,				/* cost of moving XMM,YMM,ZMM
+ 					   register.  */
+   6,					/* cost of moving SSE register to integer.  */
+ 
+   14, 10,				/* Gather load static, per_elt.  */
+   14, 20,				/* Gather store static, per_elt.  */
+   32,					/* size of l1 cache.  */
+   512,					/* size of l2 cache.  */
+   64,					/* size of prefetch block.  */
+ 
+   100,					/* number of parallel prefetches.  */
+   3,					/* Branch cost.  */
+   COSTS_N_INSNS (5),			/* cost of FADD and FSUB insns.  */
+   COSTS_N_INSNS (5),			/* cost of FMUL instruction.  */
+ 
+   COSTS_N_INSNS (15),			/* cost of FDIV instruction.  */
+   COSTS_N_INSNS (1),			/* cost of FABS instruction.  */
+   COSTS_N_INSNS (1),			/* cost of FCHS instruction.  */
+ 
+   COSTS_N_INSNS (22),			/* cost of FSQRT instruction.  */
+ 
+   COSTS_N_INSNS (1),			/* cost of cheap SSE instruction.  */
+   COSTS_N_INSNS (3),			/* cost of ADDSS/SD SUBSS/SD insns.  */
+   COSTS_N_INSNS (3),			/* cost of MULSS instruction.  */
+   COSTS_N_INSNS (3),			/* cost of MULSD instruction.  */
+   COSTS_N_INSNS (4),			/* cost of FMA SS instruction.  */
+   COSTS_N_INSNS (4),			/* cost of FMA SD instruction.  */
+   COSTS_N_INSNS (13),			/* cost of DIVSS instruction.  */
+ 
+   COSTS_N_INSNS (10),			/* cost of DIVSD instruction.  */
+   COSTS_N_INSNS (14),			/* cost of SQRTSS instruction.  */
+   COSTS_N_INSNS (20),			/* cost of SQRTSD instruction.  */
+ 
+   4, 4, 3, 6,				/* reassoc int, fp, vec_int, vec_fp.  */
+   c86_4g_m4_memcpy,
+   c86_4g_m4_memset,
+   COSTS_N_INSNS (4),			/* cond_taken_branch_cost.  */
+   COSTS_N_INSNS (2),			/* cond_not_taken_branch_cost.  */
+   "16",					/* Loop alignment.  */
+   "16",					/* Jump alignment.  */
+   "0:0:8",				/* Label alignment.  */
+   "16",					/* Func alignment.  */
+   4,					/* Small unroll limit.  */
+   2,					/* Small unroll factor.  */
+   COSTS_N_INSNS (2),			/* Branch mispredict scale.  */
+ };
diff -Nrcpad gcc-15-20260612/gcc/config/i386/x86-tune-sched.cc gcc-15-20260619/gcc/config/i386/x86-tune-sched.cc
*** gcc-15-20260612/gcc/config/i386/x86-tune-sched.cc	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/i386/x86-tune-sched.cc	Fri Jun 19 22:32:06 2026
*************** ix86_issue_rate (void)
*** 89,94 ****
--- 89,97 ----
         is not going to be able to use more than 4 instructions since that
         is limits of the decoders.  */
      case PROCESSOR_ZNVER5:
+     case PROCESSOR_C86_4G_M4:
+     case PROCESSOR_C86_4G_M6:
+     case PROCESSOR_C86_4G_M7:
        return 4;
  
      case PROCESSOR_ICELAKE_CLIENT:
*************** ix86_adjust_cost (rtx_insn *insn, int de
*** 426,431 ****
--- 429,437 ----
      case PROCESSOR_ZNVER3:
      case PROCESSOR_ZNVER4:
      case PROCESSOR_ZNVER5:
+     case PROCESSOR_C86_4G_M4:
+     case PROCESSOR_C86_4G_M6:
+     case PROCESSOR_C86_4G_M7:
        /* Stack engine allows to execute push&pop instructions in parall.  */
        if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)
  	  && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))
diff -Nrcpad gcc-15-20260612/gcc/config/i386/x86-tune.def gcc-15-20260619/gcc/config/i386/x86-tune.def
*** gcc-15-20260612/gcc/config/i386/x86-tune.def	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/i386/x86-tune.def	Fri Jun 19 22:32:06 2026
*************** see the files COPYING3 and COPYING.RUNTI
*** 42,48 ****
  DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
            m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
  	  | m_INTEL | m_K6_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
! 	  | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
  	  | m_GENERIC)
  
  /* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
--- 42,48 ----
  DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
            m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
  	  | m_INTEL | m_K6_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
! 	  | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G
  	  | m_GENERIC)
  
  /* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
*************** DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENC
*** 53,59 ****
            m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE | m_CORE_AVX2
  	  | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL
  	  | m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
     destinations to be 128bit to allow register renaming on 128bit SSE units,
--- 53,59 ----
            m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE | m_CORE_AVX2
  	  | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL
  	  | m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
     destinations to be 128bit to allow register renaming on 128bit SSE units,
*************** DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENC
*** 64,70 ****
  DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
            m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
  	  | m_BDVER | m_ZNVER | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY: This knob avoids
     partial write to the destination in scalar SSE conversion from FP
--- 64,70 ----
  DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
            m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
  	  | m_BDVER | m_ZNVER | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY: This knob avoids
     partial write to the destination in scalar SSE conversion from FP
*************** DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_FP_CO
*** 73,79 ****
  	  "sse_partial_reg_fp_converts_dependency",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
  	  | m_BDVER | m_ZNVER | m_ZHAOXIN | m_CORE_HYBRID | m_CORE_ATOM
! 	  | m_GENERIC)
  
  /* X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY: This knob avoids partial
     write to the destination in scalar SSE conversion from integer to FP.  */
--- 73,79 ----
  	  "sse_partial_reg_fp_converts_dependency",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
  	  | m_BDVER | m_ZNVER | m_ZHAOXIN | m_CORE_HYBRID | m_CORE_ATOM
! 	  | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY: This knob avoids partial
     write to the destination in scalar SSE conversion from integer to FP.  */
*************** DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_CONVE
*** 81,87 ****
  	  "sse_partial_reg_converts_dependency",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
  	  | m_BDVER | m_ZNVER | m_ZHAOXIN | m_CORE_HYBRID | m_CORE_ATOM
! 	  | m_GENERIC)
  
  /* X86_TUNE_DEST_FALSE_DEP_FOR_GLC: This knob inserts zero-idiom before
     several insns to break false dependency on the dest register for GLC
--- 81,87 ----
  	  "sse_partial_reg_converts_dependency",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
  	  | m_BDVER | m_ZNVER | m_ZHAOXIN | m_CORE_HYBRID | m_CORE_ATOM
! 	  | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_DEST_FALSE_DEP_FOR_GLC: This knob inserts zero-idiom before
     several insns to break false dependency on the dest register for GLC
*************** DEF_TUNE (X86_TUNE_MOVX, "movx",
*** 113,144 ****
            m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE
  	  | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_INTEL
  	  | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN
! 	  | m_CORE_AVX2 | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
     full sized loads.  */
  DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
            m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
  	  | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE | m_ZHAOXIN
! 	  | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
     conditional jump instruction for 32 bit TARGET.  */
  DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32",
! 	  m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_GENERIC)
  
  /* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent
     conditional jump instruction for TARGET_64BIT.  */
  DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64",
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
! 	  | m_ZNVER | m_ZHAOXIN | m_GENERIC)
  
  /* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a
     subsequent conditional jump instruction when the condition jump
     check sign flag (SF) or overflow flag (OF).  */
  DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags",
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
! 	  | m_ZNVER | m_ZHAOXIN | m_GENERIC)
  
  /* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional
     jump instruction when the alu instruction produces the CCFLAG consumed by
--- 113,145 ----
            m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM  | m_SANDYBRIDGE
  	  | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_INTEL
  	  | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN
! 	  | m_CORE_AVX2 | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
! 	  | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
     full sized loads.  */
  DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
            m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
  	  | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE | m_ZHAOXIN
! 	  | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
     conditional jump instruction for 32 bit TARGET.  */
  DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32",
! 	  m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent
     conditional jump instruction for TARGET_64BIT.  */
  DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64",
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
! 	  | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a
     subsequent conditional jump instruction when the condition jump
     check sign flag (SF) or overflow flag (OF).  */
  DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags",
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
! 	  | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional
     jump instruction when the alu instruction produces the CCFLAG consumed by
*************** DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE,
*** 200,213 ****
  /* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits.  */
  DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
  	  m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN
! 	  | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
     Some chips, like 486 and Pentium works faster with separate load
     and push instructions.  */
  DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
            m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
! 	  | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
     over esp subtraction.  */
--- 201,215 ----
  /* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits.  */
  DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
  	  m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN
! 	  | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
     Some chips, like 486 and Pentium works faster with separate load
     and push instructions.  */
  DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
            m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
! 	  | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G
! 	  | m_GENERIC)
  
  /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
     over esp subtraction.  */
*************** DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES,
*** 291,297 ****
            ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
  	    | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
  	    | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
! 	    | m_GENERIC))
  
  /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
     will impact LEA instruction selection. */
--- 293,299 ----
            ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
  	    | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
  	    | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
! 	    | m_C86_4G | m_GENERIC))
  
  /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
     will impact LEA instruction selection. */
*************** DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVS
*** 338,351 ****
  DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
  	  "misaligned_move_string_pro_epilogues",
  	  m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT
! 	  | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_USE_SAHF: Controls use of SAHF.  */
  DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
  	  | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER
  	  | m_ZNVER | m_ZHAOXIN | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
! 	  | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions.  */
  DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
--- 340,353 ----
  DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
  	  "misaligned_move_string_pro_epilogues",
  	  m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT
! 	  | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_USE_SAHF: Controls use of SAHF.  */
  DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
  	  | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER
  	  | m_ZNVER | m_ZHAOXIN | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
! 	  | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions.  */
  DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
*************** DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
*** 356,362 ****
  DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
  	  m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL | m_LAKEMONT
  	  | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT | m_GOLDMONT_PLUS
! 	  | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
     for bit-manipulation instructions.  */
--- 358,364 ----
  DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
  	  m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL | m_LAKEMONT
  	  | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT | m_GOLDMONT_PLUS
! 	  | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
     for bit-manipulation instructions.  */
*************** DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "on
*** 390,396 ****
  /* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence.  */
  DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence",
  	 m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
! 	 | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by
     generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) -
--- 392,398 ----
  /* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence.  */
  DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence",
  	 m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
! 	 | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by
     generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) -
*************** DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use
*** 414,423 ****
            ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
  	    | m_SILVERMONT | m_INTEL | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
  	    | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
! 	    | m_GENERIC))
  
  /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp.  */
! DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_ZHAOXIN)
  
  /* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI.  */
  DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
--- 416,426 ----
            ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
  	    | m_SILVERMONT | m_INTEL | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
  	    | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
! 	    | m_C86_4G | m_GENERIC))
  
  /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp.  */
! DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_ZHAOXIN
! 	  | m_C86_4G)
  
  /* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI.  */
  DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
*************** DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OP
*** 441,470 ****
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_INTEL
  	  | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID
  	  | m_CORE_ATOM | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_ZHAOXIN
! 	  | m_GENERIC)
  
  /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores
     instead of a sequence loading registers by parts.  */
  DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT
  	  | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_BDVER | m_ZNVER | m_ZHAOXIN | m_GENERIC)
  
  /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single
     precision 128bit instructions instead of double where possible.   */
  DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optimal",
! 	  m_BDVER | m_ZNVER)
  
  /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores.   */
  DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
  	  m_AMD_MULTIPLE | m_ZHAOXIN | m_CORE_ALL | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
     xorps/xorpd and other variants.  */
  DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER
! 	  | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
     to SSE registers.  If disabled, the moves will be done by storing
--- 444,474 ----
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_INTEL
  	  | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID
  	  | m_CORE_ATOM | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_ZHAOXIN
! 	  | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores
     instead of a sequence loading registers by parts.  */
  DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
  	  m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT
  	  | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_BDVER | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single
     precision 128bit instructions instead of double where possible.   */
  DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optimal",
! 	  m_BDVER | m_ZNVER | m_C86_4G)
  
  /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores.   */
  DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
  	  m_AMD_MULTIPLE | m_ZHAOXIN | m_CORE_ALL | m_TREMONT | m_CORE_HYBRID
! 	  | m_CORE_ATOM | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
     xorps/xorpd and other variants.  */
  DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
  	  m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER
! 	  | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
! 	  | m_C86_4G | m_GENERIC)
  
  /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
     to SSE registers.  If disabled, the moves will be done by storing
*************** DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES,
*** 515,560 ****
     elements.  */
  DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts",
  	  ~(m_ZNVER | m_CORE_HYBRID | m_DIAMONDRAPIDS
! 	    | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS))
  
  /* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, "use_scatter_2parts",
! 	  ~(m_ZNVER4 | m_ZNVER5))
  
  /* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4
     elements.  */
  DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts",
  	  ~(m_ZNVER | m_CORE_HYBRID | m_DIAMONDRAPIDS
! 	    | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS))
  
  /* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, "use_scatter_4parts",
! 	  ~(m_ZNVER4 | m_ZNVER5))
  
  /* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more
     elements.  */
  DEF_TUNE (X86_TUNE_USE_GATHER_8PARTS, "use_gather_8parts",
  	  ~(m_ZNVER | m_CORE_HYBRID | m_CORE_ATOM
! 	    | m_YONGFENG | m_SHIJIDADAO | m_GENERIC | m_GDS))
  
  /* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_8PARTS, "use_scatter_8parts",
! 	  ~(m_ZNVER4 | m_ZNVER5))
  
  /* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or
     smaller FMA chain.  */
  DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER
!           | m_YONGFENG | m_SHIJIDADAO | m_GENERIC)
  
  /* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or
     smaller FMA chain.  */
  DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains",
  	  m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ZNVER5 | m_CORE_HYBRID
  	  | m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
! 	  | m_DIAMONDRAPIDS | m_CORE_ATOM | m_GENERIC)
  
  /* X86_TUNE_AVOID_512FMA_CHAINS: Avoid creating loops with tight 512bit or
     smaller FMA chain.  */
--- 519,566 ----
     elements.  */
  DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts",
  	  ~(m_ZNVER | m_CORE_HYBRID | m_DIAMONDRAPIDS
! 	    | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS
! 	    | m_C86_4G))
  
  /* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, "use_scatter_2parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7))
  
  /* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4
     elements.  */
  DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts",
  	  ~(m_ZNVER | m_CORE_HYBRID | m_DIAMONDRAPIDS
! 	    | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS
! 	    | m_C86_4G))
  
  /* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, "use_scatter_4parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7))
  
  /* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more
     elements.  */
  DEF_TUNE (X86_TUNE_USE_GATHER_8PARTS, "use_gather_8parts",
  	  ~(m_ZNVER | m_CORE_HYBRID | m_CORE_ATOM
! 	    | m_YONGFENG | m_SHIJIDADAO | m_GENERIC | m_GDS | m_C86_4G))
  
  /* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more
     elements.  */
  DEF_TUNE (X86_TUNE_USE_SCATTER_8PARTS, "use_scatter_8parts",
! 	  ~(m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7))
  
  /* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or
     smaller FMA chain.  */
  DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER
! 	  | m_YONGFENG | m_SHIJIDADAO | m_GENERIC | m_C86_4G)
  
  /* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or
     smaller FMA chain.  */
  DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains",
  	  m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ZNVER5 | m_CORE_HYBRID
  	  | m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
! 	  | m_DIAMONDRAPIDS | m_CORE_ATOM | m_GENERIC | m_C86_4G)
  
  /* X86_TUNE_AVOID_512FMA_CHAINS: Avoid creating loops with tight 512bit or
     smaller FMA chain.  */
*************** DEF_TUNE (X86_TUNE_AVX256_AVOID_VEC_PERM
*** 606,634 ****
  	 "avx256_avoid_vec_perm", m_CORE_ATOM)
  
  /* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX512 ops are split into two AVX256 ops.  */
! DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4)
  
  /* It's better to align MOVE_MAX with prefer_vector_width to reduce
     risk of STLF stalls(small store followed by big load.)  */
  /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
! 	  m_CORE_HYBRID | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3)
  
  /* X86_TUNE_AVX256_STORE_BY_PIECES: Optimize store_by_pieces with 256-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECES, "avx256_store_by_pieces",
! 	  m_CORE_HYBRID | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3)
  
  /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
! 	   m_ZNVER4 | m_ZNVER5)
  
  /* X86_TUNE_AVX512_STORE_BY_PIECES: Optimize store_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_STORE_BY_PIECES, "avx512_store_by_pieces",
! 	  m_ZNVER4 | m_ZNVER5)
  
  /* X86_TUNE_AVX512_TWO_EPILOGUES: Use two vector epilogues for 512-bit
     vectorized loops.  */
--- 612,643 ----
  	 "avx256_avoid_vec_perm", m_CORE_ATOM)
  
  /* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX512 ops are split into two AVX256 ops.  */
! DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4
! 	  | m_C86_4G_M7)
  
  /* It's better to align MOVE_MAX with prefer_vector_width to reduce
     risk of STLF stalls(small store followed by big load.)  */
  /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
! 	  m_CORE_HYBRID | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3
! 	  | m_C86_4G_M4 | m_C86_4G_M6)
  
  /* X86_TUNE_AVX256_STORE_BY_PIECES: Optimize store_by_pieces with 256-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECES, "avx256_store_by_pieces",
! 	  m_CORE_HYBRID | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3
! 	  | m_C86_4G_M4 | m_C86_4G_M6)
  
  /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
! 	   m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7)
  
  /* X86_TUNE_AVX512_STORE_BY_PIECES: Optimize store_by_pieces with 512-bit
     AVX instructions.  */
  DEF_TUNE (X86_TUNE_AVX512_STORE_BY_PIECES, "avx512_store_by_pieces",
! 	  m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7)
  
  /* X86_TUNE_AVX512_TWO_EPILOGUES: Use two vector epilogues for 512-bit
     vectorized loops.  */
*************** DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "pro
*** 775,778 ****
  DEF_TUNE (X86_TUNE_SLOW_STC, "slow_stc", m_PENT4)
  
  /* X86_TUNE_USE_RCR: Controls use of rcr 1 instruction instead of shrd.  */
! DEF_TUNE (X86_TUNE_USE_RCR, "use_rcr", m_AMD_MULTIPLE)
--- 784,787 ----
  DEF_TUNE (X86_TUNE_SLOW_STC, "slow_stc", m_PENT4)
  
  /* X86_TUNE_USE_RCR: Controls use of rcr 1 instruction instead of shrd.  */
! DEF_TUNE (X86_TUNE_USE_RCR, "use_rcr", m_AMD_MULTIPLE | m_C86_4G)
diff -Nrcpad gcc-15-20260612/gcc/config/mips/mips.h gcc-15-20260619/gcc/config/mips/mips.h
*** gcc-15-20260612/gcc/config/mips/mips.h	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/mips/mips.h	Fri Jun 19 22:32:07 2026
*************** FP_ASM_SPEC "\
*** 1685,1694 ****
     doesn't support 128-bit integers for MIPS32 currently.  */
  #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
  
- /* long double is not a fixed mode, but the idea is that, if we
-    support long double, we also want a 128-bit integer type.  */
- #define MAX_FIXED_MODE_SIZE MIPS_LONG_DOUBLE_TYPE_SIZE
- 
  /* Width in bits of a pointer.  */
  #ifndef POINTER_SIZE
  #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
--- 1685,1690 ----
diff -Nrcpad gcc-15-20260612/gcc/config/riscv/riscv-v.cc gcc-15-20260619/gcc/config/riscv/riscv-v.cc
*** gcc-15-20260612/gcc/config/riscv/riscv-v.cc	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config/riscv/riscv-v.cc	Fri Jun 19 22:32:07 2026
*************** expand_const_vector (rtx target, rtx src
*** 1480,1619 ****
  	    = rtx_to_poly_int64 (builder.elt (builder.npatterns () + 1))
  	      - rtx_to_poly_int64 (base2);
  
! 	  /* For { 1, 0, 2, 0, ... , n - 1, 0 }, we can use larger EEW
! 	     integer vector mode to generate such vector efficiently.
! 
! 	     E.g. EEW = 16, { 2, 0, 4, 0, ... }
! 
! 	     can be interpreted into:
! 
! 		  EEW = 32, { 2, 4, ... }.
! 
! 	     Both the series1 and series2 may overflow before taking the IOR
! 	     to generate the final result.  However, only series1 matters
! 	     because the series2 will shift before IOR, thus the overflow
! 	     bits will never pollute the final result.
! 
! 	     For now we forbid the negative steps and overflow, and they
! 	     will fall back to the default merge way to generate the
! 	     const_vector.  */
! 
! 	  unsigned int new_smode_bitsize = builder.inner_bits_size () * 2;
! 	  scalar_int_mode new_smode;
! 	  machine_mode new_mode;
! 	  poly_uint64 new_nunits
! 	    = exact_div (GET_MODE_NUNITS (builder.mode ()), 2);
! 
! 	  poly_int64 base1_poly = rtx_to_poly_int64 (base1);
! 	  bool overflow_smode_p = false;
! 
! 	  if (!step1.is_constant ())
! 	    overflow_smode_p = true;
! 	  else
! 	    {
! 	      int elem_count = XVECLEN (src, 0);
! 	      uint64_t step1_val = step1.to_constant ();
! 	      uint64_t base1_val = base1_poly.to_constant ();
! 	      uint64_t elem_val = base1_val + (elem_count - 1) * step1_val;
! 
! 	      if ((elem_val >> builder.inner_bits_size ()) != 0)
! 		overflow_smode_p = true;
! 	    }
! 
! 	  if (known_ge (step1, 0) && known_ge (step2, 0)
! 	      && int_mode_for_size (new_smode_bitsize, 0).exists (&new_smode)
! 	      && get_vector_mode (new_smode, new_nunits).exists (&new_mode)
! 	      && !overflow_smode_p)
  	    {
! 	      rtx tmp1 = gen_reg_rtx (new_mode);
! 	      base1 = gen_int_mode (base1_poly, new_smode);
! 	      expand_vec_series (tmp1, base1, gen_int_mode (step1, new_smode));
! 
! 	      if (rtx_equal_p (base2, const0_rtx) && known_eq (step2, 0))
! 		/* { 1, 0, 2, 0, ... }.  */
! 		emit_move_insn (result, gen_lowpart (mode, tmp1));
! 	      else if (known_eq (step2, 0))
! 		{
! 		  /* { 1, 1, 2, 1, ... }.  */
! 		  rtx scalar = expand_simple_binop (
! 		    Xmode, ASHIFT,
! 		    gen_int_mode (rtx_to_poly_int64 (base2), Xmode),
! 		    gen_int_mode (builder.inner_bits_size (), Xmode),
! 		    NULL_RTX, false, OPTAB_DIRECT);
! 		  scalar = simplify_gen_subreg (new_smode, scalar, Xmode, 0);
! 		  rtx tmp2 = gen_reg_rtx (new_mode);
! 		  rtx ior_ops[] = {tmp2, tmp1, scalar};
! 		  emit_vlmax_insn (code_for_pred_scalar (IOR, new_mode),
! 				   BINARY_OP, ior_ops);
! 		  emit_move_insn (result, gen_lowpart (mode, tmp2));
! 		}
! 	      else
! 		{
! 		  /* { 1, 3, 2, 6, ... }.  */
! 		  rtx tmp2 = gen_reg_rtx (new_mode);
! 		  base2 = gen_int_mode (rtx_to_poly_int64 (base2), new_smode);
! 		  expand_vec_series (tmp2, base2,
! 				     gen_int_mode (step2, new_smode));
! 		  rtx shifted_tmp2;
! 		  rtx shift = gen_int_mode (builder.inner_bits_size (), Xmode);
! 		  if (lra_in_progress)
! 		    {
! 		      shifted_tmp2 = gen_reg_rtx (new_mode);
! 		      rtx shift_ops[] = {shifted_tmp2, tmp2, shift};
! 		      emit_vlmax_insn (code_for_pred_scalar
! 				       (ASHIFT, new_mode), BINARY_OP,
! 				       shift_ops);
! 		    }
! 		  else
! 		    shifted_tmp2 = expand_simple_binop (new_mode, ASHIFT, tmp2,
! 							shift, NULL_RTX, false,
! 							OPTAB_DIRECT);
! 		  rtx tmp3 = gen_reg_rtx (new_mode);
! 		  rtx ior_ops[] = {tmp3, tmp1, shifted_tmp2};
! 		  emit_vlmax_insn (code_for_pred (IOR, new_mode), BINARY_OP,
! 				   ior_ops);
! 		  emit_move_insn (result, gen_lowpart (mode, tmp3));
! 		}
  	    }
  	  else
! 	    {
! 	      rtx vid = gen_reg_rtx (mode);
! 	      expand_vec_series (vid, const0_rtx, const1_rtx);
! 	      /* Transform into { 0, 0, 1, 1, 2, 2, ... }.  */
! 	      rtx shifted_vid;
! 	      if (lra_in_progress)
! 		{
! 		  shifted_vid = gen_reg_rtx (mode);
! 		  rtx shift = gen_int_mode (1, Xmode);
! 		  rtx shift_ops[] = {shifted_vid, vid, shift};
! 		  emit_vlmax_insn (code_for_pred_scalar
! 				   (LSHIFTRT, mode), BINARY_OP,
! 				   shift_ops);
! 		}
! 	      else
! 		shifted_vid = expand_simple_binop (mode, LSHIFTRT, vid,
! 						   const1_rtx, NULL_RTX,
! 						   false, OPTAB_DIRECT);
! 	      rtx tmp1 = gen_reg_rtx (mode);
! 	      rtx tmp2 = gen_reg_rtx (mode);
! 	      expand_vec_series (tmp1, base1,
! 				 gen_int_mode (step1, builder.inner_mode ()),
! 				 shifted_vid);
! 	      expand_vec_series (tmp2, base2,
! 				 gen_int_mode (step2, builder.inner_mode ()),
! 				 shifted_vid);
  
! 	      /* Transform into { 0, 1, 0, 1, 0, 1, ... }.  */
! 	      rtx and_vid = gen_reg_rtx (mode);
! 	      rtx and_ops[] = {and_vid, vid, const1_rtx};
! 	      emit_vlmax_insn (code_for_pred_scalar (AND, mode), BINARY_OP,
! 			       and_ops);
! 	      rtx mask = gen_reg_rtx (builder.mask_mode ());
! 	      expand_vec_cmp (mask, EQ, and_vid, CONST1_RTX (mode));
  
! 	      rtx ops[] = {result, tmp1, tmp2, mask};
! 	      emit_vlmax_insn (code_for_pred_merge (mode), MERGE_OP, ops);
! 	    }
  	}
        else
  	/* TODO: We will enable more variable-length vector in the future.  */
--- 1480,1521 ----
  	    = rtx_to_poly_int64 (builder.elt (builder.npatterns () + 1))
  	      - rtx_to_poly_int64 (base2);
  
! 	  rtx vid = gen_reg_rtx (mode);
! 	  expand_vec_series (vid, const0_rtx, const1_rtx);
! 	  /* Transform into { 0, 0, 1, 1, 2, 2, ... }.  */
! 	  rtx shifted_vid;
! 	  if (lra_in_progress)
  	    {
! 	      shifted_vid = gen_reg_rtx (mode);
! 	      rtx shift = gen_int_mode (1, Xmode);
! 	      rtx shift_ops[] = {shifted_vid, vid, shift};
! 	      emit_vlmax_insn (code_for_pred_scalar
! 			       (LSHIFTRT, mode), BINARY_OP,
! 			       shift_ops);
  	    }
  	  else
! 	    shifted_vid = expand_simple_binop (mode, LSHIFTRT, vid,
! 					       const1_rtx, NULL_RTX,
! 					       false, OPTAB_DIRECT);
! 	  rtx tmp1 = gen_reg_rtx (mode);
! 	  rtx tmp2 = gen_reg_rtx (mode);
! 	  expand_vec_series (tmp1, base1,
! 			     gen_int_mode (step1, builder.inner_mode ()),
! 			     shifted_vid);
! 	  expand_vec_series (tmp2, base2,
! 			     gen_int_mode (step2, builder.inner_mode ()),
! 			     shifted_vid);
  
! 	  /* Transform into { 0, 1, 0, 1, 0, 1, ... }.  */
! 	  rtx and_vid = gen_reg_rtx (mode);
! 	  rtx and_ops[] = {and_vid, vid, const1_rtx};
! 	  emit_vlmax_insn (code_for_pred_scalar (AND, mode), BINARY_OP,
! 			   and_ops);
! 	  rtx mask = gen_reg_rtx (builder.mask_mode ());
! 	  expand_vec_cmp (mask, EQ, and_vid, CONST1_RTX (mode));
  
! 	  rtx ops[] = {result, tmp1, tmp2, mask};
! 	  emit_vlmax_insn (code_for_pred_merge (mode), MERGE_OP, ops);
  	}
        else
  	/* TODO: We will enable more variable-length vector in the future.  */
diff -Nrcpad gcc-15-20260612/gcc/config/rs6000/rs6000.h gcc-15-20260619/gcc/config/rs6000/rs6000.h
*** gcc-15-20260612/gcc/config/rs6000/rs6000.h	Fri Jun 12 22:32:06 2026
--- gcc-15-20260619/gcc/config/rs6000/rs6000.h	Fri Jun 19 22:32:07 2026
*************** extern int rs6000_vector_align[];
*** 532,540 ****
  				 || TARGET_VSX				 \
  				 || TARGET_HARD_FLOAT)
  
! /* E500 cores only support plain "sync", not lwsync.  */
  #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
! 			  || rs6000_cpu == PROCESSOR_PPC8548)
  
  
  /* Which machine supports the various reciprocal estimate instructions.  */
--- 532,544 ----
  				 || TARGET_VSX				 \
  				 || TARGET_HARD_FLOAT)
  
! /* E500 and MPC8xx cores require all should-be-zero bits in sync to
!    actually be zero; using lwsync (L=1) causes a fault on these cores.
!    Classic cores (601, 603, 604, 750 etc.) simply ignore the L field
!    and always do a full hwsync.  */
  #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
! 			  || rs6000_cpu == PROCESSOR_PPC8548 \
! 			  || rs6000_cpu == PROCESSOR_MPCCORE)
  
  
  /* Which machine supports the various reciprocal estimate instructions.  */
diff -Nrcpad gcc-15-20260612/gcc/config.gcc gcc-15-20260619/gcc/config.gcc
*** gcc-15-20260612/gcc/config.gcc	Fri Jun 12 22:32:05 2026
--- gcc-15-20260619/gcc/config.gcc	Fri Jun 19 22:32:06 2026
*************** skylake goldmont goldmont-plus tremont c
*** 715,721 ****
  sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \
  nano-x2 eden-x4 nano-x4 lujiazui yongfeng shijidadao x86-64 x86-64-v2 \
  x86-64-v3 x86-64-v4 sierraforest graniterapids graniterapids-d grandridge \
! arrowlake arrowlake-s clearwaterforest pantherlake diamondrapids native"
  
  # Additional x86 processors supported by --with-cpu=.  Each processor
  # MUST be separated by exactly one space.
--- 715,722 ----
  sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \
  nano-x2 eden-x4 nano-x4 lujiazui yongfeng shijidadao x86-64 x86-64-v2 \
  x86-64-v3 x86-64-v4 sierraforest graniterapids graniterapids-d grandridge \
! arrowlake arrowlake-s clearwaterforest pantherlake diamondrapids \
! c86-4g-m4 c86-4g-m6 c86-4g-m7 native"
  
  # Additional x86 processors supported by --with-cpu=.  Each processor
  # MUST be separated by exactly one space.
*************** case ${target} in
*** 3909,3914 ****
--- 3910,3927 ----
  	cpu=pentiumpro
  	arch_without_sse2=yes
  	;;
+       c86_4g_m4-*)
+ 	arch=c86-4g-m4
+ 	cpu=c86-4g-m4
+ 	;;
+       c86_4g_m6-*)
+ 	arch=c86-4g-m6
+ 	cpu=c86-4g-m6
+ 	;;
+       c86_4g_m7-*)
+ 	arch=c86-4g-m7
+ 	cpu=c86-4g-m7
+ 	;;
        *)
  	arch=pentiumpro
  	cpu=generic
*************** case ${target} in
*** 4007,4012 ****
--- 4020,4037 ----
  	arch=corei7
  	cpu=corei7
  	;;
+       c86_4g_m4-*)
+ 	arch=c86-4g-m4
+ 	cpu=c86-4g-m4
+ 	;;
+       c86_4g_m6-*)
+ 	arch=c86-4g-m6
+ 	cpu=c86-4g-m6
+ 	;;
+       c86_4g_m7-*)
+ 	arch=c86-4g-m7
+ 	cpu=c86-4g-m7
+ 	;;
        *)
  	arch=x86-64
  	cpu=generic
diff -Nrcpad gcc-15-20260612/gcc/cp/ChangeLog gcc-15-20260619/gcc/cp/ChangeLog
*** gcc-15-20260612/gcc/cp/ChangeLog	Fri Jun 12 22:32:06 2026
--- gcc-15-20260619/gcc/cp/ChangeLog	Fri Jun 19 22:32:07 2026
***************
*** 1,3 ****
--- 1,11 ----
+ 2026-06-17  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-05-04  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR c++/65271
+ 	* parser.cc (cp_parser_class_specifier): Accept &&.
+ 
  2026-06-12  Release Manager
  
  	* GCC 15.3.0 released.
diff -Nrcpad gcc-15-20260612/gcc/cp/parser.cc gcc-15-20260619/gcc/cp/parser.cc
*** gcc-15-20260612/gcc/cp/parser.cc	Fri Jun 12 22:32:06 2026
--- gcc-15-20260619/gcc/cp/parser.cc	Fri Jun 19 22:32:07 2026
*************** cp_parser_class_specifier (cp_parser* pa
*** 27634,27639 ****
--- 27634,27640 ----
        case CPP_SEMICOLON:
        case CPP_MULT:
        case CPP_AND:
+       case CPP_AND_AND:
        case CPP_OPEN_PAREN:
        case CPP_CLOSE_PAREN:
        case CPP_COMMA:
diff -Nrcpad gcc-15-20260612/gcc/doc/extend.texi gcc-15-20260619/gcc/doc/extend.texi
*** gcc-15-20260612/gcc/doc/extend.texi	Fri Jun 12 22:32:06 2026
--- gcc-15-20260619/gcc/doc/extend.texi	Fri Jun 19 22:32:07 2026
*************** AMD Family 19h Zen version 4.
*** 28291,28296 ****
--- 28291,28308 ----
  
  @item znver5
  AMD Family 1ah Zen version 5.
+ 
+ @item hygonfam18h
+ HYGON Family 18h CPU.
+ 
+ @item c86-4g-m4
+ HYGON Family 18h model 4 dharma CPU.
+ 
+ @item c86-4g-m6
+ HYGON Family 18h model 6 shanghai CPU.
+ 
+ @item c86-4g-m7
+ HYGON Family 18h model 7 chengdu CPU.
  @end table
  
  Here is an example:
diff -Nrcpad gcc-15-20260612/gcc/doc/invoke.texi gcc-15-20260619/gcc/doc/invoke.texi
*** gcc-15-20260612/gcc/doc/invoke.texi	Fri Jun 12 22:32:06 2026
--- gcc-15-20260619/gcc/doc/invoke.texi	Fri Jun 19 22:32:07 2026
*************** instruction set support.
*** 35502,35507 ****
--- 35502,35528 ----
  
  @item geode
  AMD Geode embedded processor with MMX and 3DNow!@: instruction set support.
+ 
+ @item c86-4g-m4
+ HYGON c86-4g-m4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3,
+ SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA,
+ XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO,
+ CLFLUSHOPT, XSAVES, LZCNT, POPCNT instruction set support.
+ 
+ @item c86-4g-m6
+ HYGON c86-4g-m6 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3,
+ SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA,
+ XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO,
+ CLFLUSHOPT, XSAVES, LZCNT, POPCNT instruction set support.
+ 
+ @item c86-4g-m7
+ HYGON c86-4g-m7 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3,
+ SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA,
+ XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO,
+ CLFLUSHOPT, XSAVES, LZCNT, POPCNT, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD,
+ AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, GFNI, AVX512VNNI, VAES,
+ AVX512BITALG, AVX512VPOPCNTDQ, AVX512VP2INTERSECT, AVXVNNI, VPCLMULQDQ,
+ WBNOINVD instruction set support.
  @end table
  
  @opindex mtune
diff -Nrcpad gcc-15-20260612/gcc/expmed.cc gcc-15-20260619/gcc/expmed.cc
*** gcc-15-20260612/gcc/expmed.cc	Fri Jun 12 22:32:06 2026
--- gcc-15-20260619/gcc/expmed.cc	Fri Jun 19 22:32:07 2026
*************** make_tree (tree type, rtx x)
*** 5395,5400 ****
--- 5395,5403 ----
        t = wide_int_to_tree (type, rtx_mode_t (x, TYPE_MODE (type)));
        return t;
  
+     case CONST_POLY_INT:
+       return wide_int_to_tree (type, const_poly_int_value (x));
+ 
      case CONST_DOUBLE:
        STATIC_ASSERT (HOST_BITS_PER_WIDE_INT * 2 <= MAX_BITSIZE_MODE_ANY_INT);
        if (TARGET_SUPPORTS_WIDE_INT == 0 && GET_MODE (x) == VOIDmode)
*************** make_tree (tree type, rtx x)
*** 5486,5494 ****
        /* fall through.  */
  
      default:
-       if (CONST_POLY_INT_P (x))
- 	return wide_int_to_tree (t, const_poly_int_value (x));
- 
        t = build_decl (RTL_LOCATION (x), VAR_DECL, NULL_TREE, type);
  
        /* If TYPE is a POINTER_TYPE, we might need to convert X from
--- 5489,5494 ----
diff -Nrcpad gcc-15-20260612/gcc/fortran/ChangeLog gcc-15-20260619/gcc/fortran/ChangeLog
*** gcc-15-20260612/gcc/fortran/ChangeLog	Fri Jun 12 22:32:06 2026
--- gcc-15-20260619/gcc/fortran/ChangeLog	Fri Jun 19 22:32:07 2026
***************
*** 1,3 ****
--- 1,13 ----
+ 2026-06-12  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	Backported from master:
+ 	2026-06-06  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	PR fortran/125606
+ 	* trans-intrinsic.cc (gfc_conv_intrinsic_loc): When the argument
+ 	of LOC() is not scalar or known to be simply contiguous, simply
+ 	take the address of the argument array's first element.
+ 
  2026-06-12  Release Manager
  
  	* GCC 15.3.0 released.
diff -Nrcpad gcc-15-20260612/gcc/gimple-range-fold.cc gcc-15-20260619/gcc/gimple-range-fold.cc
*** gcc-15-20260612/gcc/gimple-range-fold.cc	Fri Jun 12 22:32:06 2026
--- gcc-15-20260619/gcc/gimple-range-fold.cc	Fri Jun 19 22:32:07 2026
*************** fold_using_range::relation_fold_and_or (
*** 1341,1347 ****
      return;
  
    if (reverse_op2)
!     relation2 = relation_negate (relation2);
  
    // x && y is false if the relation intersection of the true cases is NULL.
    if (is_and && relation_intersect (relation1, relation2) == VREL_UNDEFINED)
--- 1341,1347 ----
      return;
  
    if (reverse_op2)
!     relation2 = relation_swap (relation2);
  
    // x && y is false if the relation intersection of the true cases is NULL.
    if (is_and && relation_intersect (relation1, relation2) == VREL_UNDEFINED)
diff -Nrcpad gcc-15-20260612/gcc/ipa-param-manipulation.cc gcc-15-20260619/gcc/ipa-param-manipulation.cc
*** gcc-15-20260612/gcc/ipa-param-manipulation.cc	Fri Jun 12 22:32:06 2026
--- gcc-15-20260619/gcc/ipa-param-manipulation.cc	Fri Jun 19 22:32:07 2026
*************** ipa_param_body_adjustments::prepare_debu
*** 1348,1355 ****
  	}
  
        gcc_assert (TREE_CODE (value) == SSA_NAME);
!       tree *d = m_dead_ssa_debug_equiv.get (value);
!       m_dead_ssa_debug_equiv.put (dead_ssa, *d);
        return true;
      }
  
--- 1348,1355 ----
  	}
  
        gcc_assert (TREE_CODE (value) == SSA_NAME);
!       tree d = *m_dead_ssa_debug_equiv.get (value);
!       m_dead_ssa_debug_equiv.put (dead_ssa, d);
        return true;
      }
  
diff -Nrcpad gcc-15-20260612/gcc/regcprop.cc gcc-15-20260619/gcc/regcprop.cc
*** gcc-15-20260612/gcc/regcprop.cc	Fri Jun 12 22:32:06 2026
--- gcc-15-20260619/gcc/regcprop.cc	Fri Jun 19 22:32:08 2026
***************
*** 36,41 ****
--- 36,42 ----
  #include "cfgrtl.h"
  #include "target.h"
  #include "function-abi.h"
+ #include "cfgcleanup.h"
  
  /* The following code does forward propagation of hard register copies.
     The object is to eliminate as many dependencies as possible, so that
*************** copyprop_hardreg_forward_1 (basic_block
*** 858,864 ****
  	  && !side_effects_p (SET_DEST (set)))
  	{
  	  bool last = insn == BB_END (bb);
! 	  delete_insn (insn);
  	  if (last)
  	    break;
  	  continue;
--- 859,865 ----
  	  && !side_effects_p (SET_DEST (set)))
  	{
  	  bool last = insn == BB_END (bb);
! 	  delete_insn_and_edges (insn);
  	  if (last)
  	    break;
  	  continue;
*************** pass_cprop_hardreg::execute (function *f
*** 1439,1444 ****
--- 1440,1446 ----
    auto_vec<int> *curr = &worklist1;
    auto_vec<int> *next = &worklist2;
    bool any_debug_changes = false;
+   bool any_changes = false;
  
    /* We need accurate notes.  Earlier passes such as if-conversion may
       leave notes in an inconsistent state.  */
*************** pass_cprop_hardreg::execute (function *f
*** 1458,1464 ****
    FOR_EACH_BB_FN (bb, fun)
      {
        if (cprop_hardreg_bb (bb, all_vd, visited))
! 	curr->safe_push (bb->index);
        if (all_vd[bb->index].n_debug_insn_changes)
  	any_debug_changes = true;
      }
--- 1460,1469 ----
    FOR_EACH_BB_FN (bb, fun)
      {
        if (cprop_hardreg_bb (bb, all_vd, visited))
! 	{
! 	  curr->safe_push (bb->index);
! 	  any_changes = true;
! 	}
        if (all_vd[bb->index].n_debug_insn_changes)
  	any_debug_changes = true;
      }
*************** pass_cprop_hardreg::execute (function *f
*** 1485,1491 ****
  	{
  	  bb = BASIC_BLOCK_FOR_FN (fun, index);
            if (cprop_hardreg_bb (bb, all_vd, visited))
! 	    next->safe_push (bb->index);
  	  if (all_vd[bb->index].n_debug_insn_changes)
  	    any_debug_changes = true;
  	}
--- 1490,1499 ----
  	{
  	  bb = BASIC_BLOCK_FOR_FN (fun, index);
            if (cprop_hardreg_bb (bb, all_vd, visited))
! 	    {
! 	      next->safe_push (bb->index);
! 	      any_changes = true;
! 	    }
  	  if (all_vd[bb->index].n_debug_insn_changes)
  	    any_debug_changes = true;
  	}
*************** pass_cprop_hardreg::execute (function *f
*** 1497,1502 ****
--- 1505,1519 ----
      }
  
    free (all_vd);
+ 
+   /* Copy propagation of the sp register into an mem's address
+      can cause what was a trapping instruction into
+      a non-trapping one so cleanup after that in the case of non-call
+      exceptions.  */
+   if (any_changes
+       && cfun->can_throw_non_call_exceptions
+       && purge_all_dead_edges ())
+     cleanup_cfg (0);
    return 0;
  }
  
diff -Nrcpad gcc-15-20260612/gcc/simplify-rtx.cc gcc-15-20260619/gcc/simplify-rtx.cc
*** gcc-15-20260612/gcc/simplify-rtx.cc	Fri Jun 12 22:32:07 2026
--- gcc-15-20260619/gcc/simplify-rtx.cc	Fri Jun 19 22:32:08 2026
*************** simplify_context::simplify_subreg (machi
*** 8184,8190 ****
        res = simplify_subreg (outermode, part, part_mode, final_offset);
        if (res)
  	return res;
!       if (validate_subreg (outermode, part_mode, part, final_offset))
  	return gen_rtx_SUBREG (outermode, part, final_offset);
        return NULL_RTX;
      }
--- 8184,8191 ----
        res = simplify_subreg (outermode, part, part_mode, final_offset);
        if (res)
  	return res;
!       if (GET_MODE (part) != VOIDmode
! 	  && validate_subreg (outermode, part_mode, part, final_offset))
  	return gen_rtx_SUBREG (outermode, part, final_offset);
        return NULL_RTX;
      }
diff -Nrcpad gcc-15-20260612/gcc/testsuite/ChangeLog gcc-15-20260619/gcc/testsuite/ChangeLog
*** gcc-15-20260612/gcc/testsuite/ChangeLog	Fri Jun 12 22:32:07 2026
--- gcc-15-20260619/gcc/testsuite/ChangeLog	Fri Jun 19 22:32:08 2026
***************
*** 1,3 ****
--- 1,151 ----
+ 2026-06-18  Xin Liu  <liulxx@hygon.cn>
+ 
+ 	Backported from master:
+ 	2026-04-29  Xin Liu  <liulxx@hygon.cn>
+ 		    Zhaoling Bao  <baozhaoling@hygon.cn>
+ 
+ 	* gcc.target/i386/builtin_target.c: Add handling for HYGON CPUs by
+ 	validating the vendor and invoking HYGON-specific CPU detection.
+ 	* gcc.target/i386/funcspec-56.inc: Test function target attribute on
+ 	{arch,tune}=c86-4g-m{4,6,7}.
+ 	* g++.target/i386/mv33.C: New test.
+ 
+ 2026-06-17  Zhongyao Chen  <chen.zhongyao@zte.com.cn>
+ 
+ 	PR target/125215
+ 	* gcc.target/riscv/rvv/autovec/pr125215.c: New test.
+ 	* gcc.target/riscv/rvv/autovec/slp-interleave-1.c: Remove.
+ 	* gcc.target/riscv/rvv/autovec/slp-interleave-2.c: Remove.
+ 	* gcc.target/riscv/rvv/autovec/slp-interleave-3.c: Remove.
+ 	* gcc.target/riscv/rvv/autovec/slp-interleave-4.c: Remove.
+ 	* gcc.target/riscv/rvv/autovec/slp-interleave-5.c: Remove.
+ 
+ 2026-06-17  Alex Coplan  <alex.coplan@arm.com>
+ 
+ 	Backported from master:
+ 	2026-06-09  Alex Coplan  <alex.coplan@arm.com>
+ 
+ 	PR middle-end/125621
+ 	* gcc.target/aarch64/torture/pr125621.c: New test.
+ 
+ 2026-06-17  Kishan Parmar  <kishan@linux.ibm.com>
+ 
+ 	Backported from master:
+ 	2026-05-27  Kishan Parmar  <kishan@linux.ibm.com>
+ 		    Surya Kumari Jangala  <jskumari@linux.ibm.com>
+ 
+ 	PR target/125448
+ 	* gcc.target/powerpc/mpc860_no_lwsync.c: Restrict to ilp32 targets.
+ 
+ 2026-06-17  Kishan Parmar  <kishan@linux.ibm.com>
+ 
+ 	Backported from master:
+ 	2026-05-22  Steve Markgraf  <steve@steve-m.de>
+ 
+ 	* gcc.target/powerpc/mpc860_no_lwsync.c: New test.
+ 
+ 2026-06-17  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	Backported from master:
+ 	2026-06-15  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	PR target/125795
+ 	* gcc.target/aarch64/pr125795.c: New test.
+ 
+ 2026-06-17  Carter Rennick  <carter.rennick@gmail.com>
+ 
+ 	Backported from master:
+ 	2026-04-24  Carter Rennick  <carter.rennick@gmail.com>
+ 
+ 	PR target/120144
+ 	* gcc.dg/torture/pr120144.c: New test.
+ 
+ 2026-06-17  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-06-13  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/125776
+ 	* gcc.dg/torture/pr125776-1.c: New test.
+ 	* gcc.dg/torture/pr125776-2.c: New test.
+ 
+ 2026-06-17  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-06-14  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/125774
+ 	* gcc.dg/torture/pr125774-1.c: New test.
+ 
+ 2026-06-17  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-05-04  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR c++/65271
+ 	* g++.dg/cpp0x/rv-decl1.C: New test.
+ 
+ 2026-06-17  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-03-12  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR rtl-optimization/123822
+ 	* gcc.dg/torture/pr123822-1.c: New test.
+ 
+ 2026-06-17  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-03-13  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR rtl-optimization/124454
+ 	* gcc.dg/pr124454-1.c: New test.
+ 
+ 2026-06-17  Thomas Schwinge  <tschwinge@baylibre.com>
+ 
+ 	Backported from master:
+ 	2026-02-19  Thomas Schwinge  <tschwinge@baylibre.com>
+ 
+ 	PR rtl-optimization/116053
+ 	* gcc.dg/pr116053-1.c: 'dg-require-effective-target int128'.
+ 
+ 2026-06-17  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-02-18  Andrew Pinski  <andrew.pinski@oss.qualcomm.com>
+ 
+ 	PR rtl-optimization/116053
+ 	* gcc.dg/pr116053-1.c: New test.
+ 
+ 2026-06-17  Andrew MacLeod  <amacleod@redhat.com>
+ 
+ 	PR tree-optimization/125501
+ 	* gcc.dg/pr125501.c: New.
+ 
+ 2026-06-16  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	Backported from master:
+ 	2026-05-12  Martin Jambor  <mjambor@suse.cz>
+ 
+ 	PR tree-optimization/124151
+ 	* gcc.dg/tree-ssa/pr124151.c: New test.
+ 
+ 2026-06-12  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	Backported from master:
+ 	2026-06-06  Harald Anlauf  <anlauf@gmx.de>
+ 
+ 	PR fortran/125606
+ 	* gfortran.dg/loc_3.f90: New test.
+ 
+ 2026-06-12  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2026-06-11  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/125752
+ 	* gcc.target/avr/torture/fx-to-double.c: New test.
+ 
  2026-06-12  Release Manager
  
  	* GCC 15.3.0 released.
diff -Nrcpad gcc-15-20260612/gcc/testsuite/g++.dg/cpp0x/rv-decl1.C gcc-15-20260619/gcc/testsuite/g++.dg/cpp0x/rv-decl1.C
*** gcc-15-20260612/gcc/testsuite/g++.dg/cpp0x/rv-decl1.C	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/g++.dg/cpp0x/rv-decl1.C	Fri Jun 19 22:32:08 2026
***************
*** 0 ****
--- 1,7 ----
+ // PR c++/65271
+ // { dg-do compile { target c++11 } }
+ 
+ struct {} && m0 = {};
+ union  {} && m1 = {};
+ class  {} && m2 = {};
+ enum   {} && m3 = {};
diff -Nrcpad gcc-15-20260612/gcc/testsuite/g++.target/i386/mv33.C gcc-15-20260619/gcc/testsuite/g++.target/i386/mv33.C
*** gcc-15-20260612/gcc/testsuite/g++.target/i386/mv33.C	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/g++.target/i386/mv33.C	Fri Jun 19 22:32:09 2026
***************
*** 0 ****
--- 1,42 ----
+ // Test that dispatching can choose the right multiversion
+ // for HYGON CPUs with the same internal GCC processor id
+ 
+ // { dg-do run }
+ // { dg-require-ifunc "" }
+ // { dg-options "-O2" }
+ 
+ #include <assert.h>
+ 
+ int __attribute__ ((target("default")))
+ foo ()
+ {
+   return 0;
+ }
+ 
+ int __attribute__ ((target("arch=c86-4g-m4"))) foo () {
+   return 1;
+ }
+ 
+ int __attribute__ ((target("arch=c86-4g-m6"))) foo () {
+   return 2;
+ }
+ 
+ int __attribute__ ((target("arch=c86-4g-m7"))) foo () {
+   return 3;
+ }
+ 
+ int main ()
+ {
+   int val = foo ();
+ 
+   if  (__builtin_cpu_is ("c86-4g-m4"))
+     assert (val == 1);
+   else if (__builtin_cpu_is ("c86-4g-m6"))
+     assert (val == 2);
+   else if (__builtin_cpu_is ("c86-4g-m7"))
+     assert (val == 3);
+   else
+     assert (val == 0);
+ 
+   return 0;
+ }
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.dg/pr116053-1.c gcc-15-20260619/gcc/testsuite/gcc.dg/pr116053-1.c
*** gcc-15-20260612/gcc/testsuite/gcc.dg/pr116053-1.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/gcc.dg/pr116053-1.c	Fri Jun 19 22:32:10 2026
***************
*** 0 ****
--- 1,12 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O1 -finstrument-functions -fno-forward-propagate -fno-delete-dead-exceptions -fnon-call-exceptions" } */
+ /* { dg-require-effective-target exceptions } */
+ /* { dg-require-effective-target int128 } */
+ 
+ /* PR rtl-optimization/116053 */
+ 
+ void
+ foo (__int128 x)
+ {
+   x = *(__int128 *) __builtin_memset (&x, 0, 10);
+ }
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.dg/pr124454-1.c gcc-15-20260619/gcc/testsuite/gcc.dg/pr124454-1.c
*** gcc-15-20260612/gcc/testsuite/gcc.dg/pr124454-1.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/gcc.dg/pr124454-1.c	Fri Jun 19 22:32:10 2026
***************
*** 0 ****
--- 1,15 ----
+ /* { dg-do compile } */
+ /* { dg-additional-options "-O3 -fno-forward-propagate -fnon-call-exceptions -fno-dse -fprofile-generate -fopenmp -finstrument-functions" } */
+ /* { dg-additional-options "-mno-outline-atomics" { target aarch64*-*-* } } */
+ 
+ /* PR rtl-optimization/124454 */
+ 
+ int a, b;
+ 
+ void
+ foo()
+ {
+   long c;
+   a *= b;
+   b = *(char *)__builtin_memset(&c, 1, 4);
+ }
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.dg/pr125501.c gcc-15-20260619/gcc/testsuite/gcc.dg/pr125501.c
*** gcc-15-20260612/gcc/testsuite/gcc.dg/pr125501.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/gcc.dg/pr125501.c	Fri Jun 19 22:32:10 2026
***************
*** 0 ****
--- 1,35 ----
+ // { dg-do run }
+ // { dg-options "-O3" }
+ 
+ #include <stdint.h>
+ int64_t g2, g27, g10;
+ static void *g13, *g24;
+ _Bool f11___trans_tmp_1, f11_c17;
+ void __attribute__((noinline)) f11(int64_t a0, void *a4, void *a5)
+ {
+     _Bool ob6;
+     int32_t v12;
+     int64_t v15;
+ lbl_entry:
+ lbl_sw_def4:
+     ob6 = g13 == a4;
+     if (ob6 || f11_c17) return;
+     if (f11___trans_tmp_1) v12 = g10;
+     a0 = (char *)a5 - (char *)a4;
+     ob6 = 0 == a0;
+     *(_Bool *)4 = 0;
+     if (ob6) goto lbl_b22;
+     __builtin_unreachable();
+ lbl_b22:
+     g27 = v12;
+     switch (v15)
+     {
+         case 6009053803839173278: goto lbl_sw_def4;
+         case 70689892217558167: goto lbl_entry;
+     }
+ }
+ 
+ int main()
+ {
+     f11(0, 0, g24);
+ }
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.dg/torture/pr120144.c gcc-15-20260619/gcc/testsuite/gcc.dg/torture/pr120144.c
*** gcc-15-20260612/gcc/testsuite/gcc.dg/torture/pr120144.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/gcc.dg/torture/pr120144.c	Fri Jun 19 22:32:10 2026
***************
*** 0 ****
--- 1,8 ----
+ /* PR target/120144 */
+ /* { dg-do compile } */
+ /* { dg-require-effective-target int128 } */
+ 
+ int f(unsigned __int128 t)
+ {
+   return __builtin_clzg(t);
+ }
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.dg/torture/pr123822-1.c gcc-15-20260619/gcc/testsuite/gcc.dg/torture/pr123822-1.c
*** gcc-15-20260612/gcc/testsuite/gcc.dg/torture/pr123822-1.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/gcc.dg/torture/pr123822-1.c	Fri Jun 19 22:32:10 2026
***************
*** 0 ****
--- 1,16 ----
+ /* { dg-do compile } */
+ /* { dg-additional-options "-ffast-math" } */
+ /* { dg-require-effective-target dfp } */
+ 
+ /* PR rtl-optimization/123822 */
+ 
+ typedef __attribute__((__vector_size__(16))) _Decimal64 D;
+ 
+ int i;
+ D d;
+ 
+ void
+ foo()
+ {
+   d /= (D)(d >= *(D *)__builtin_memset(&d, i, 3));
+ }
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.dg/torture/pr125774-1.c gcc-15-20260619/gcc/testsuite/gcc.dg/torture/pr125774-1.c
*** gcc-15-20260612/gcc/testsuite/gcc.dg/torture/pr125774-1.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/gcc.dg/torture/pr125774-1.c	Fri Jun 19 22:32:10 2026
***************
*** 0 ****
--- 1,48 ----
+ /* { dg-do run } */
+ /* { dg-additional-options "-fgimple -fdump-tree-optimized" } */
+ /* { dg-skip-if "" { *-*-* } { "-fno-fat-lto-objects" } { "" } } */
+ /* PR tree-optimization/125774 */
+ 
+ __attribute__((noipa))
+ _Bool __GIMPLE (ssa,startwith("dom2"))
+ f (int a, int b)
+ {
+   _Bool _3;
+   _Bool _4;
+   _Bool _5;
+ 
+   __BB(2):
+   _3 = a_1(D) > b_2(D);
+   _4 = b_2(D) > a_1(D);
+   _5 = _3 | _4;
+   return _5;
+ }
+ 
+ __attribute__((noipa))
+ _Bool __GIMPLE (ssa,startwith("dom2"))
+ f1 (int a, int b)
+ {
+   _Bool _3;
+   _Bool _4;
+   _Bool _5;
+ 
+   __BB(2):
+   _3 = a_1(D) > b_2(D);
+   _4 = a_1(D) < b_2(D);
+   _5 = _3 | _4;
+   return _5;
+ }
+ 
+ int main()
+ {
+   int a = 10, b = 10;
+   if (f(a,b))
+     __builtin_abort();
+   if (f1(a,b))
+     __builtin_abort();
+   return 0;
+ }
+ 
+ /* { dg-final { scan-tree-dump-not "return 1" "optimized" } } */
+ /* Both functions should be optimized to `a_1 != b_2`. */
+ /* { dg-final { scan-tree-dump-times "a_1.D. != b_2.D." 2 "optimized" { target __OPTIMIZE__ } } } */
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.dg/torture/pr125776-1.c gcc-15-20260619/gcc/testsuite/gcc.dg/torture/pr125776-1.c
*** gcc-15-20260612/gcc/testsuite/gcc.dg/torture/pr125776-1.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/gcc.dg/torture/pr125776-1.c	Fri Jun 19 22:32:10 2026
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile } */
+ /* { dg-additional-options "-fcompare-debug" } */
+ /* PR tree-optimization/125776 */
+ 
+ int a, b, d, e, f;
+ long c;
+ void g();
+ void h() {
+   unsigned i;
+   for (;;) {
+     unsigned j = a ? a : d;
+     i += j;
+     f = b & 40 | b > 4;
+     e = a ? a : b;
+     if (e)
+       break;
+     if (j)
+       g();
+   }
+   c = i;
+ }
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.dg/torture/pr125776-2.c gcc-15-20260619/gcc/testsuite/gcc.dg/torture/pr125776-2.c
*** gcc-15-20260612/gcc/testsuite/gcc.dg/torture/pr125776-2.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/gcc.dg/torture/pr125776-2.c	Fri Jun 19 22:32:10 2026
***************
*** 0 ****
--- 1,21 ----
+ /* { dg-do compile } */
+ /* { dg-additional-options "-fcompare-debug" } */
+ /* PR tree-optimization/125776 */
+ int a, b, d, e, f;
+ long c;
+ void g();
+ void h(int i) {
+   for (;;) {
+     i++;
+     int j = a  ? a : d;
+     i = i > 0 ? i : -i;
+     f = b & 40 | b > 4;
+     e = a ? a : b;
+     if (e)
+       break;
+     if (j)
+       g();
+   }
+   c = i;
+ }
+ 
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.dg/tree-ssa/pr124151.c gcc-15-20260619/gcc/testsuite/gcc.dg/tree-ssa/pr124151.c
*** gcc-15-20260612/gcc/testsuite/gcc.dg/tree-ssa/pr124151.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/gcc.dg/tree-ssa/pr124151.c	Fri Jun 19 22:32:10 2026
***************
*** 0 ****
--- 1,31 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O1" } */
+ 
+ typedef struct {
+   _Bool : 1;
+ } Http2Identifier;
+ typedef struct {
+   _Bool is_end;
+   Http2Identifier identifier;
+ } Http2DataFrame;
+ typedef struct {
+   Http2Identifier identifier;
+   _Bool end_headers;
+ } Http2ContinuationFrame;
+ typedef struct {
+   union {
+     Http2DataFrame data;
+     Http2ContinuationFrame continuation;
+   };
+ } Http2Frame;
+ typedef struct {
+   Http2Identifier stream_identifier;
+ } Http2RawHeader;
+ Http2RawHeader parse_http2_continuation_frame_http2_raw_header;
+ Http2Frame gh2f;
+ void http2_send_and_receive_preface() {
+   Http2ContinuationFrame continuation_frame = {
+       parse_http2_continuation_frame_http2_raw_header.stream_identifier, 0};
+   Http2Frame frame = {.continuation = continuation_frame};
+   gh2f = frame;
+ }
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.target/aarch64/pr125795.c gcc-15-20260619/gcc/testsuite/gcc.target/aarch64/pr125795.c
*** gcc-15-20260612/gcc/testsuite/gcc.target/aarch64/pr125795.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/gcc.target/aarch64/pr125795.c	Fri Jun 19 22:32:11 2026
***************
*** 0 ****
--- 1,47 ----
+ /* PR target/125795 */
+ /* { dg-do run } */
+ /* { dg-options "-O2 -funroll-loops" } */
+ 
+ /* This loop is vectorized with LD2 (deinterleave) and TBL (lane reversal),
+    then unrolled.  The unrolled body builds a full-width (32 FPR) early-ra
+    color group, which used to trigger a "1U << 32" undefined shift in
+    early_ra::allocate_colors.  As a result the long-lived TBL permute index
+    was wrongly allocated to the same FPR as an LD2 tuple destination and got
+    clobbered, so the result was miscomputed.  */
+ 
+ extern void abort (void);
+ 
+ #define N 256
+ 
+ static int __attribute__ ((noipa))
+ foo (void)
+ {
+   int k[N];
+   int k2[N];
+   int i;
+ 
+   for (i = 0; i < N; i++)
+     k2[i] = i;
+ 
+   for (i = 0; i < 64; i++)
+     {
+       k[i] = k2[2 * i + 0];
+       k[255 - i] = k2[2 * i + 1];
+       k[64 + i] = k2[2 * i + 128];
+       k[191 - i] = k2[2 * i + 129];
+     }
+ 
+   for (i = 0; i < N; i++)
+     if (k[i] != ((i < 128) ? (2 * i) : (511 - 2 * i)))
+       return 1;
+ 
+   return 0;
+ }
+ 
+ int
+ main (void)
+ {
+   if (foo ())
+     abort ();
+   return 0;
+ }
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.target/aarch64/torture/pr125621.c gcc-15-20260619/gcc/testsuite/gcc.target/aarch64/torture/pr125621.c
*** gcc-15-20260612/gcc/testsuite/gcc.target/aarch64/torture/pr125621.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/gcc.target/aarch64/torture/pr125621.c	Fri Jun 19 22:32:11 2026
***************
*** 0 ****
--- 1,7 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=armv8.2-a+sve -fsanitize=undefined" } */
+ #include <arm_sve.h>
+ 
+ long foo(long x) {
+   return (long)svcntd() * x;
+ }
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.target/i386/builtin_target.c gcc-15-20260619/gcc/testsuite/gcc.target/i386/builtin_target.c
*** gcc-15-20260612/gcc/testsuite/gcc.target/i386/builtin_target.c	Fri Jun 12 22:32:10 2026
--- gcc-15-20260619/gcc/testsuite/gcc.target/i386/builtin_target.c	Fri Jun 19 22:32:12 2026
*************** check_detailed ()
*** 54,59 ****
--- 54,63 ----
        assert (__builtin_cpu_is ("amd"));
        get_amd_cpu (&cpu_model, &cpu_model2, cpu_features2);
        break;
+     case VENDOR_HYGON:
+       assert (__builtin_cpu_is ("hygon"));
+       get_hygon_cpu (&cpu_model, &cpu_model2, cpu_features2);
+       break;
      default:
        break;
      }
*************** quick_check ()
*** 127,132 ****
--- 131,138 ----
  
    assert (__builtin_cpu_is ("bdver2") >= 0);
  
+   assert (__builtin_cpu_is ("c86-4g-m4") >= 0);
+ 
    return 0;
  }
  
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.target/i386/funcspec-56.inc gcc-15-20260619/gcc/testsuite/gcc.target/i386/funcspec-56.inc
*** gcc-15-20260612/gcc/testsuite/gcc.target/i386/funcspec-56.inc	Fri Jun 12 22:32:10 2026
--- gcc-15-20260619/gcc/testsuite/gcc.target/i386/funcspec-56.inc	Fri Jun 19 22:32:12 2026
*************** extern void test_arch_znver2 (void)
*** 239,244 ****
--- 239,247 ----
  extern void test_arch_znver3 (void)             __attribute__((__target__("arch=znver3")));
  extern void test_arch_znver4 (void)             __attribute__((__target__("arch=znver4")));
  extern void test_arch_znver5 (void)             __attribute__((__target__("arch=znver5")));
+ extern void test_arch_c86_4g_m4 (void)          __attribute__((__target__("arch=c86-4g-m4")));
+ extern void test_arch_c86_4g_m6 (void)          __attribute__((__target__("arch=c86-4g-m6")));
+ extern void test_arch_c86_4g_m7 (void)          __attribute__((__target__("arch=c86-4g-m7")));
  
  extern void test_tune_nocona (void)		__attribute__((__target__("tune=nocona")));
  extern void test_tune_core2 (void)		__attribute__((__target__("tune=core2")));
*************** extern void test_tune_znver2 (void)
*** 266,271 ****
--- 269,277 ----
  extern void test_tune_znver3 (void)             __attribute__((__target__("tune=znver3")));
  extern void test_tune_znver4 (void)             __attribute__((__target__("tune=znver4")));
  extern void test_tune_znver5 (void)             __attribute__((__target__("tune=znver5")));
+ extern void test_tune_c86_4g_m4 (void)          __attribute__((__target__("tune=c86-4g-m4")));
+ extern void test_tune_c86_4g_m6 (void)          __attribute__((__target__("tune=c86-4g-m6")));
+ extern void test_tune_c86_4g_m7 (void)          __attribute__((__target__("tune=c86-4g-m7")));
  
  extern void test_fpmath_sse (void)		__attribute__((__target__("sse2,fpmath=sse")));
  extern void test_fpmath_387 (void)		__attribute__((__target__("sse2,fpmath=387")));
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.target/powerpc/mpc860_no_lwsync.c gcc-15-20260619/gcc/testsuite/gcc.target/powerpc/mpc860_no_lwsync.c
*** gcc-15-20260612/gcc/testsuite/gcc.target/powerpc/mpc860_no_lwsync.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/gcc.target/powerpc/mpc860_no_lwsync.c	Fri Jun 19 22:32:12 2026
***************
*** 0 ****
--- 1,13 ----
+ /* { dg-do compile { target { powerpc*-*-* && ilp32 } } } */
+ /* { dg-options "-mcpu=860 -O2" } */
+ 
+ /* Check that we do not emit lwsync when targeting MPC8xx (MPCCORE),
+    since the MPC8xx core does not support and faults on this instruction.  */
+ 
+ void
+ store_release (int *ptr, int val)
+ {
+   __atomic_store_n (ptr, val, __ATOMIC_RELEASE);
+ }
+ 
+ /* { dg-final { scan-assembler-not "\mlwsync\M" } } */
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr125215.c gcc-15-20260619/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr125215.c
*** gcc-15-20260612/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr125215.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260619/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr125215.c	Fri Jun 19 22:32:12 2026
***************
*** 0 ****
--- 1,24 ----
+ /* { dg-do run { target { riscv_v } } } */
+ /* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -fno-vect-cost-model" } */
+ 
+ #include <stdint-gcc.h>
+ 
+ __attribute__((noipa))
+ void foo(uint8_t *d)
+ {
+   d[0] = 128; d[1] = 135; d[2] = 130; d[3] = 149;
+   d[4] = 132; d[5] = 163; d[6] = 134; d[7] = 177;
+   d[8] = 136; d[9] = 191; d[10] = 138; d[11] = 205;
+   d[12] = 140; d[13] = 219; d[14] = 142; d[15] = 233;
+ }
+ 
+ int main()
+ {
+   uint8_t d[16];
+   uint8_t e[] = {128, 135, 130, 149, 132, 163, 134, 177, 136, 191, 138, 205, 140, 219, 142, 233};
+   foo(d);
+   for (int i = 0; i < 16; i++)
+     if (d[i] != e[i])
+       __builtin_abort ();
+   return 0;
+ }
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-1.c gcc-15-20260619/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-1.c
*** gcc-15-20260612/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-1.c	Fri Jun 12 22:32:11 2026
--- gcc-15-20260619/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-1.c	Thu Jan  1 00:00:00 1970
***************
*** 1,17 ****
- /* { dg-do compile } */
- /* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized-details" } */
- 
- struct S { int a, b; } s[8];
- 
- void
- foo ()
- {
-   int i;
-   for (i = 0; i < 8; i++)
-     {
-       s[i].b = 0;
-       s[i].a = i;
-     }
- }
- 
- /* { dg-final { scan-tree-dump-times "\{ 0, 0, 1, 0, 2, 0, ... \}" 1 "optimized" } } */
--- 0 ----
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-2.c gcc-15-20260619/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-2.c
*** gcc-15-20260612/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-2.c	Fri Jun 12 22:32:11 2026
--- gcc-15-20260619/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-2.c	Thu Jan  1 00:00:00 1970
***************
*** 1,18 ****
- /* { dg-do compile } */
- /* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized-details" } */
- 
- struct S { int a, b; } s[8];
- 
- void
- foo ()
- {
-   int i;
-   for (i = 0; i < 8; i++)
-     {
-       s[i].b = 1;
-       s[i].a = i;
-     }
- }
- 
- /* { dg-final { scan-tree-dump-times "\{ 0, 1, 1, 1, 2, 1, ... \}" 1 "optimized" } } */
- /* { dg-final { scan-assembler-times {slli\t[a-x0-9]+,\s*[a-x0-9]+,\s*32} 1 } } */
--- 0 ----
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-3.c gcc-15-20260619/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-3.c
*** gcc-15-20260612/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-3.c	Fri Jun 12 22:32:11 2026
--- gcc-15-20260619/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-3.c	Thu Jan  1 00:00:00 1970
***************
*** 1,19 ****
- /* { dg-do compile } */
- /* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -fno-vect-cost-model -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized-details" } */
- 
- struct S { int a, b; } s[8];
- 
- void
- foo ()
- {
-   int i;
-   for (i = 0; i < 8; i++)
-     {
-       s[i].b = i*3 + 100;
-       s[i].a = i + 200;
-     }
- }
- 
- /* { dg-final { scan-tree-dump-times "\{ 200, 100, 201, 103, 202, 106, ... \}" 1 "optimized" } } */
- /* { dg-final { scan-assembler-times {vsll\.vx} 1 } } */
- /* { dg-final { scan-assembler-times {vor\.vv} 1 } } */
--- 0 ----
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-4.c gcc-15-20260619/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-4.c
*** gcc-15-20260612/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-4.c	Fri Jun 12 22:32:11 2026
--- gcc-15-20260619/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-4.c	Thu Jan  1 00:00:00 1970
***************
*** 1,19 ****
- /* { dg-do compile } */
- /* { dg-options "-march=rv64gc_zve32f_zvl1024b -mabi=lp64d -fno-vect-cost-model -mrvv-max-lmul=m8 -O3 -fdump-tree-optimized-details" } */
- 
- struct S { int a, b; } s[8];
- 
- void
- foo ()
- {
-   int i;
-   for (i = 0; i < 8; i++)
-     {
-       s[i].b = i*3 + 100;
-       s[i].a = i + 200;
-     }
- }
- 
- /* { dg-final { scan-tree-dump-times "\{ 200, 100, 201, 103, 202, 106, ... \}" 1 "optimized" } } */
- /* { dg-final { scan-assembler-times {vand\.vi} 1 } } */
- /* { dg-final { scan-assembler-times {vmseq\.vi} 1 } } */
--- 0 ----
diff -Nrcpad gcc-15-20260612/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-5.c gcc-15-20260619/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-5.c
*** gcc-15-20260612/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-5.c	Fri Jun 12 22:32:11 2026
--- gcc-15-20260619/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-5.c	Thu Jan  1 00:00:00 1970
***************
*** 1,35 ****
- /* { dg-do compile } */
- /* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -O3 -fdump-tree-optimized-details" } */
- 
- struct S { int a, b; } s[8];
- 
- void
- foo ()
- {
-   int i;
-   for (i = 0; i < 8; i++)
-     {
-       s[i].b = 1;
-       s[i].a = i+1;
-     }
- }
- 
- /* { dg-final { scan-tree-dump-times "\{ 1, 1, 2, 1, 3, 1, 4, 1 \}" 1 "optimized" } } */
- /* { dg-final { scan-assembler {vid\.v} } } */
- /* { dg-final { scan-assembler {vadd\.v} } } */
- /* { dg-final { scan-assembler {vor\.v} } } */
- 
- void
- foo2 ()
- {
-   int i;
-   for (i = 0; i < 8; i++)
-     {
-       s[i].b = 0;
-       s[i].a = i+1;
-     }
- }
- 
- /* { dg-final { scan-tree-dump-times "\{ 1, 0, 2, 0, 3, 0, 4, 0 \}" 1 "optimized" } } */
- /* { dg-final { scan-assembler {vid\.v} } } */
- /* { dg-final { scan-assembler {vadd\.v} } } */
--- 0 ----
diff -Nrcpad gcc-15-20260612/gcc/tree-sra.cc gcc-15-20260619/gcc/tree-sra.cc
*** gcc-15-20260612/gcc/tree-sra.cc	Fri Jun 12 22:32:12 2026
--- gcc-15-20260619/gcc/tree-sra.cc	Fri Jun 19 22:32:14 2026
*************** build_debug_ref_for_model (location_t lo
*** 2085,2100 ****
  }
  
  /* Construct a memory reference consisting of component_refs and array_refs to
!    a part of an aggregate *RES (which is of type TYPE).  The requested part
!    should have type EXP_TYPE at be the given OFFSET.  This function might not
!    succeed, it returns true when it does and only then *RES points to something
!    meaningful.  This function should be used only to build expressions that we
!    might need to present to user (e.g. in warnings).  In all other situations,
     build_ref_for_model or build_ref_for_offset should be used instead.  */
  
  static bool
  build_user_friendly_ref_for_offset (tree *res, tree type, HOST_WIDE_INT offset,
! 				    tree exp_type)
  {
    while (1)
      {
--- 2085,2104 ----
  }
  
  /* Construct a memory reference consisting of component_refs and array_refs to
!    a part of an aggregate *RES which is of type TYPE.  The requested part
!    should have type EXP_TYPE at the given OFFSET.  CUR_SIZE must be the size of
!    *RES unless it is known that *RES alone cannot be the result.  This function
!    might not succeed, it returns true when it does and only then *RES points to
!    something meaningful.
! 
!    This function should be used only to build expressions that we might need to
!    present to user (e.g. in warnings).  In all other situations,
     build_ref_for_model or build_ref_for_offset should be used instead.  */
  
  static bool
  build_user_friendly_ref_for_offset (tree *res, tree type, HOST_WIDE_INT offset,
! 				    HOST_WIDE_INT cur_size, tree exp_type,
! 				    HOST_WIDE_INT exp_size)
  {
    while (1)
      {
*************** build_user_friendly_ref_for_offset (tree
*** 2102,2108 ****
        tree tr_size, index, minidx;
        HOST_WIDE_INT el_size;
  
!       if (offset == 0 && exp_type
  	  && types_compatible_p (exp_type, type))
  	return true;
  
--- 2106,2113 ----
        tree tr_size, index, minidx;
        HOST_WIDE_INT el_size;
  
!       if (offset == 0
! 	  && cur_size == exp_size
  	  && types_compatible_p (exp_type, type))
  	return true;
  
*************** build_user_friendly_ref_for_offset (tree
*** 2140,2146 ****
  			     NULL_TREE);
  	      expr_ptr = &expr;
  	      if (build_user_friendly_ref_for_offset (expr_ptr, TREE_TYPE (fld),
! 						      offset - pos, exp_type))
  		{
  		  *res = expr;
  		  return true;
--- 2145,2152 ----
  			     NULL_TREE);
  	      expr_ptr = &expr;
  	      if (build_user_friendly_ref_for_offset (expr_ptr, TREE_TYPE (fld),
! 						      offset - pos, size,
! 						      exp_type, exp_size))
  		{
  		  *res = expr;
  		  return true;
*************** build_user_friendly_ref_for_offset (tree
*** 2163,2179 ****
  	  *res = build4 (ARRAY_REF, TREE_TYPE (type), *res, index,
  			 NULL_TREE, NULL_TREE);
  	  offset = offset % el_size;
  	  type = TREE_TYPE (type);
  	  break;
  
  	default:
! 	  if (offset != 0)
! 	    return false;
! 
! 	  if (exp_type)
! 	    return false;
! 	  else
! 	    return true;
  	}
      }
  }
--- 2169,2180 ----
  	  *res = build4 (ARRAY_REF, TREE_TYPE (type), *res, index,
  			 NULL_TREE, NULL_TREE);
  	  offset = offset % el_size;
+ 	  cur_size = el_size;
  	  type = TREE_TYPE (type);
  	  break;
  
  	default:
! 	  return false;
  	}
      }
  }
*************** create_artificial_child_access (struct a
*** 3064,3070 ****
    struct access *access = access_pool.allocate ();
    memset (access, 0, sizeof (struct access));
    if (!build_user_friendly_ref_for_offset (&expr, TREE_TYPE (expr), new_offset,
! 					   model->type))
      {
        access->grp_no_warning = true;
        expr = build_ref_for_model (EXPR_LOCATION (parent->base), parent->base,
--- 3065,3072 ----
    struct access *access = access_pool.allocate ();
    memset (access, 0, sizeof (struct access));
    if (!build_user_friendly_ref_for_offset (&expr, TREE_TYPE (expr), new_offset,
! 					   parent->size, model->type,
! 					   model->size))
      {
        access->grp_no_warning = true;
        expr = build_ref_for_model (EXPR_LOCATION (parent->base), parent->base,
*************** propagate_subaccesses_from_rhs (struct a
*** 3205,3212 ****
  	  tree t = lacc->base;
  
  	  lacc->type = racc->type;
  	  if (build_user_friendly_ref_for_offset (&t, TREE_TYPE (t),
! 						  lacc->offset, racc->type))
  	    {
  	      lacc->expr = t;
  	      lacc->grp_same_access_path = true;
--- 3207,3217 ----
  	  tree t = lacc->base;
  
  	  lacc->type = racc->type;
+ 	  /* We know racc and lacc are of different types so can pass -1 as
+ 	     cur_size.  */
  	  if (build_user_friendly_ref_for_offset (&t, TREE_TYPE (t),
! 						  lacc->offset, -1,
! 						  racc->type, racc->size))
  	    {
  	      lacc->expr = t;
  	      lacc->grp_same_access_path = true;
*************** propagate_subaccesses_from_rhs (struct a
*** 3264,3270 ****
  	}
  
        if (rchild->grp_unscalarizable_region
- 	  || (rchild->size % BITS_PER_UNIT) != 0
  	  || !budget_for_propagation_access (lacc->base))
  	{
  	  if (!lacc->grp_write && access_or_its_child_written (rchild))
--- 3269,3274 ----
*************** propagate_subaccesses_from_lhs (struct a
*** 3324,3330 ****
        HOST_WIDE_INT norm_offset = lchild->offset + norm_delta;
  
        if (lchild->grp_unscalarizable_region
- 	  || (lchild->size % BITS_PER_UNIT) != 0
  	  || child_would_conflict_in_acc (racc, norm_offset, lchild->size,
  					  &matching_acc)
  	  || !budget_for_propagation_access (racc->base))
--- 3328,3333 ----
diff -Nrcpad gcc-15-20260612/gcc/tree-ssa-dom.cc gcc-15-20260619/gcc/tree-ssa-dom.cc
*** gcc-15-20260612/gcc/tree-ssa-dom.cc	Fri Jun 12 22:32:12 2026
--- gcc-15-20260619/gcc/tree-ssa-dom.cc	Fri Jun 19 22:32:14 2026
*************** dom_opt_dom_walker::set_global_ranges_fr
*** 1429,1434 ****
--- 1429,1440 ----
        || !assert_unreachable_fallthru_edge_p (pred_e))
      return;
  
+   // Bail if the condition leading to the assert has 2 ssa-names.
+   // See PR 125501.
+   if ((TREE_CODE (gimple_cond_lhs (stmt)) == SSA_NAME
+       && TREE_CODE (gimple_cond_rhs (stmt)) == SSA_NAME))
+     return;
+ 
    tree name;
    FOR_EACH_GORI_EXPORT_NAME (m_ranger->gori_ssa (), pred_e->src, name)
      if (all_uses_feed_or_dominated_by_stmt (name, stmt)
diff -Nrcpad gcc-15-20260612/gcc/tree-ssa-phiopt.cc gcc-15-20260619/gcc/tree-ssa-phiopt.cc
*** gcc-15-20260612/gcc/tree-ssa-phiopt.cc	Fri Jun 12 22:32:12 2026
--- gcc-15-20260619/gcc/tree-ssa-phiopt.cc	Fri Jun 19 22:32:14 2026
*************** is_factor_profitable (gimple *def_stmt,
*** 267,272 ****
--- 267,274 ----
    FOR_EACH_IMM_USE_FAST (use_p, iter, arg)
      {
        gimple *use_stmt = USE_STMT (use_p);
+       if (is_gimple_debug (use_stmt))
+ 	continue;
        basic_block use_bb = gimple_bb (use_stmt);
        if (dominated_by_p (CDI_DOMINATORS, merge, use_bb))
  	return true;
diff -Nrcpad gcc-15-20260612/libgcc/ChangeLog gcc-15-20260619/libgcc/ChangeLog
*** gcc-15-20260612/libgcc/ChangeLog	Fri Jun 12 22:32:12 2026
--- gcc-15-20260619/libgcc/ChangeLog	Fri Jun 19 22:32:14 2026
***************
*** 1,3 ****
--- 1,8 ----
+ 2026-06-12  Ramin Moussavi  <lordrasmus@gmail.com>
+ 
+ 	* config.host (microblaze*-linux*): Set md_unwind_header.
+ 	* config/microblaze/linux-unwind.h: New file.
+ 
  2026-06-12  Release Manager
  
  	* GCC 15.3.0 released.
diff -Nrcpad gcc-15-20260612/libgcc/config/avr/libf7/ChangeLog gcc-15-20260619/libgcc/config/avr/libf7/ChangeLog
*** gcc-15-20260612/libgcc/config/avr/libf7/ChangeLog	Fri Jun 12 22:32:12 2026
--- gcc-15-20260619/libgcc/config/avr/libf7/ChangeLog	Fri Jun 19 22:32:14 2026
***************
*** 1,3 ****
--- 1,22 ----
+ 2026-06-12  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	Backported from master:
+ 	2026-06-11  Georg-Johann Lay  <avr@gjlay.de>
+ 
+ 	PR target/125752
+ 	* libf7-asm.sx (ufx64_to_d, d_to_fx64): New DEFUNs.
+ 	(__fractdadf, __fractudadf, __fracttadf, __fractutadf)
+ 	(__fractdqdf, __fractudqdf): New _DEFUNs.
+ 	* libf7-common.mk (F7_ASM_PARTS) Add: fx2D, D2fx,
+ 	dq2D, udq2D, da2D, uda2D, ta2D uta2D.
+ 	(F7F): Add d_to_fx64, ufx64_to_d, sfx64_to_d.
+ 	* libf7.c (d_to_ufx, d_to_sfx): New protos.
+ 	(__fractdfda, __fractdfuda, __fractdfta, __fractdfuta)
+ 	(__fractdfdq, __fractdfudq): New modules.
+ 	* t-libf7 (LIBF7_DF_CONV): Add fractdfda,
+ 	fractdfta, fractdfdq, fractdfuda, fractdfuta, fractdfudq.
+ 	* f7-renames.h: Rebuild.
+ 
  2026-06-12  Release Manager
  
  	* GCC 15.3.0 released.
