diff -Nrcpad gcc-15-20260207/LAST_UPDATED gcc-15-20260214/LAST_UPDATED
*** gcc-15-20260207/LAST_UPDATED	Sat Feb  7 22:32:20 2026
--- gcc-15-20260214/LAST_UPDATED	Sat Feb 14 22:32:21 2026
***************
*** 1 ****
! Obtained from git: releases/gcc-15 revision ababaaf45fa0dc369c07e19ca64862c4eefaadc1
--- 1 ----
! Obtained from git: releases/gcc-15 revision 26e4f8ad7220f692cd8010f9cf7620d690f1b094
diff -Nrcpad gcc-15-20260207/MD5SUMS gcc-15-20260214/MD5SUMS
*** gcc-15-20260207/MD5SUMS	Sat Feb  7 22:32:25 2026
--- gcc-15-20260214/MD5SUMS	Sat Feb 14 22:32:26 2026
***************
*** 1,5 ****
  # This file contains the MD5 checksums of the files in the
! # gcc-15-20260207.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
--- 1,5 ----
  # This file contains the MD5 checksums of the files in the
! # gcc-15-20260214.tar.xz tarball.
  #
  # Besides verifying that all files in the tarball were correctly expanded,
  # it also can be used to determine if any files have changed since the
*************** d32239bcb673463ab874e80d47fae504  COPYIN
*** 25,31 ****
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! 6221cf8017b742c7c736dc27a21704ba  LAST_UPDATED
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--- 25,31 ----
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*** 514,520 ****
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--- 514,520 ----
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*************** fb3fadb88e1d2b3b640cfaaa5ff11780  gcc/Ch
*** 551,557 ****
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--- 551,557 ----
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*************** ec6799501b2eb2923d5de6a66169dbd2  gcc/ON
*** 563,569 ****
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--- 563,569 ----
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*************** c22c79787fe7516adb5a4c55613fb6ab  gcc/ad
*** 784,790 ****
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--- 784,790 ----
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*************** b042ff9582cb94caab7f476203ea6809  gcc/ad
*** 818,824 ****
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--- 818,824 ----
  52a5741c37559d0398594d7baa1c99ac  gcc/ada/exp_tss.ads
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! c03e4fe0f4491dfe1c74ad2e30ff3518  gcc/ada/exp_util.adb
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*************** f931bc8e97c2f1358ad3ad91e902d553  gcc/co
*** 3453,3459 ****
  c9a52df251f3132f3562d3fffaa39c7b  gcc/config/aarch64/aarch64-option-extensions.def
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! d9450e0fa15cd8b8f6659555820ec24e  gcc/config/aarch64/aarch64-protos.h
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--- 3453,3459 ----
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! 2b41eb9ae8146e717512d335e90ad5d0  gcc/config/aarch64/aarch64-protos.h
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*************** eb380a954053a41e73e4f6bb1d3572c0  gcc/co
*** 3481,3489 ****
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--- 3481,3489 ----
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*************** d1b95435bb177952f26d761fee7430d6  gcc/co
*** 3545,3551 ****
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! 7384cb5a512d446afe4c8d5d99ac4735  gcc/config/aarch64/tuning_models/olympus.h
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--- 3545,3551 ----
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*************** c242989ba84f31157338b4714b4248e1  gcc/co
*** 4178,4184 ****
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--- 4178,4184 ----
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*************** cc4d538f7d66895b427db54b9660a953  gcc/co
*** 4936,4962 ****
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--- 4936,4962 ----
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! e689fde027c44b52f074bd7c02361a6d  gcc/config/riscv/riscv-vector-builtins.h
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! c276faa29405cc7d6faf7df713486673  gcc/config/riscv/riscv-vsetvl.cc
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  7082a18dbfc574d47bf71f4d50dd30f9  gcc/config/riscv/riscv-zicfilp.cc
! 1a011f293eabcb0e39ea297e45b16e66  gcc/config/riscv/riscv.cc
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*************** bcf728ad2379630774fd5bb529d4ee86  gcc/co
*** 4992,4999 ****
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*************** dfb9fde7c7559a50905b02c01b6d6ee8  gcc/co
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*************** ec1e9c9456a8530e241079823e2fc126  gcc/cr
*** 5614,5620 ****
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*** 5846,5852 ****
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*************** e67bf1a2587fc7f7361e841145ff4cfb  gcc/es
*** 6042,6048 ****
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*************** db21881c77a22fd3dbfe253c364af5ee  gcc/fo
*** 6091,6098 ****
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--- 6091,6098 ----
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*************** ebbe3379528e7b9db85647b877e5b0bb  gcc/me
*** 7650,7656 ****
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*************** b3a965e425e6cf7888319667faf58da9  gcc/sy
*** 8448,8454 ****
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*************** e296551bbee90148974ff78d5066caf7  gcc/te
*** 37775,37780 ****
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*************** d21d6fbc6fc43c655a90fc622dc9b3c2  gcc/te
*** 49805,49810 ****
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*** 49901,49906 ****
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*************** fdf31615d4c23a6cda30ff2ff1493fcd  gcc/te
*** 62842,62847 ****
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*************** bf00cac22e30fab76ac74c7b2e5af207  gcc/te
*** 88932,88937 ****
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*************** e990c042b373d09f16b69f4b30f0ac20  gcc/te
*** 89734,89739 ****
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*************** eaed30eccbeb952165411cfd2c789b72  gcc/te
*** 91909,91916 ****
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*************** e5381974a3b2ccf0d38f73344c8a9078  gcc/te
*** 92276,92282 ****
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--- 92286,92292 ----
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*************** cbbf5673d8ca63042855a0cd377e13c2  gcc/te
*** 92621,92626 ****
--- 92631,92638 ----
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*************** b5858f375001f368a5271a2649982a89  gcc/te
*** 94186,94191 ****
--- 94198,94204 ----
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*************** e89ebd75d9b162289c929675222e8501  gcc/te
*** 95662,95667 ****
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*************** bd5f87ec53f49e6a8981f467e5bb9e41  gcc/te
*** 101384,101389 ****
--- 101398,101404 ----
  d7de9573af1b1b97fe9d86450aa3a0af  gcc/testsuite/gfortran.dg/class_array_21.f03
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*************** d845359337435f578035928aae3a54a9  gcc/te
*** 110837,110842 ****
--- 110852,110858 ----
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*************** f010d95f371dbccc1be8c51d48eb4db5  gcc/te
*** 112425,112430 ****
--- 112441,112447 ----
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*************** fbcc93539b376489c1256eb8cf2d4800  gcc/tr
*** 118097,118103 ****
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! 63757376d191769eb10c935d75de61bd  gcc/tree-ssa-math-opts.cc
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--- 118114,118120 ----
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  da72a60de8a6f51a635ead26120d3cc7  gcc/tree-ssa-operands.h
*************** d680e7307fb59fe24f8431e179191f16  libssp
*** 132189,132195 ****
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--- 132206,132212 ----
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*************** c2ed9b9ed62b02a5aba9733f5b376172  libstd
*** 132871,132877 ****
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  c54b27ddff7542cc6baa362f62fb5778  libstdc++-v3/include/bits/basic_ios.tcc
! 811aa7875a4cc11129344e9a96ad1f5b  libstdc++-v3/include/bits/basic_string.h
  ae1074cab6b583707efdb40bf0099caf  libstdc++-v3/include/bits/basic_string.tcc
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--- 132888,132894 ----
  4aec94297e365e5a284c252c0a72d1e5  libstdc++-v3/include/bits/atomic_wait.h
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*************** a155d2afa910d24be0955f42c4585228  libstd
*** 132882,132888 ****
  f220a3edd81f69f475178857df2cbeb7  libstdc++-v3/include/bits/chrono_io.h
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--- 132899,132905 ----
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*************** f0db6753fd67e8ef172c6851da248f62  libstd
*** 132929,132935 ****
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--- 132946,132952 ----
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*************** c94ad903b4e7baf364cdc3ef5e9f58a8  libstd
*** 133810,133816 ****
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--- 133827,133833 ----
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*************** dd27d37e228d376460f2fda9aee33443  libstd
*** 136020,136029 ****
--- 136037,136048 ----
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  07566e373883a954b71c561432ec0678  libstdc++-v3/testsuite/21_strings/basic_string/operations/compare/char/1.cc
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  b224efd629e9e7ebc8872ba94d3cd565  libstdc++-v3/testsuite/21_strings/basic_string/operations/compare/wchar_t/1.cc
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  d075354ce70a50537b2c548670651dd6  libstdc++-v3/testsuite/21_strings/basic_string/operations/compare/wchar_t/13650.cc
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  e0c2465a8e27301df596bd29409f3212  libstdc++-v3/testsuite/21_strings/basic_string/operations/contains/char.cc
diff -Nrcpad gcc-15-20260207/gcc/ChangeLog gcc-15-20260214/gcc/ChangeLog
*** gcc-15-20260207/gcc/ChangeLog	Sat Feb  7 22:32:05 2026
--- gcc-15-20260214/gcc/ChangeLog	Sat Feb 14 22:32:05 2026
***************
*** 1,3 ****
--- 1,134 ----
+ 2026-02-12  Pengfei Li  <Pengfei.Li2@arm.com>
+ 
+ 	PR middle-end/123447
+ 	* expr.cc (expand_expr_real_1): Increase stack slot alignment
+ 	for STRICT_ALIGNMENT targets.
+ 
+ 2026-02-11  Alice Carlotti  <alice.carlotti@arm.com>
+ 
+ 	PR target/123624
+ 	* config/aarch64/aarch64-protos.h
+ 	(aarch64_use_simple_return_insn_p): New.
+ 	* config/aarch64/aarch64.cc
+ 	(aarch64_use_simple_return_insn_p): New, used...
+ 	* config/aarch64/aarch64.md (simple_return): ...here.
+ 
+ 2026-02-11  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+ 
+ 	Backported from master:
+ 	2025-04-25  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+ 
+ 	PR rtl-optimization/116479
+ 	* modulo-sched.cc (doloop_register_get): Reject conditions with
+ 	decrements that are not 1.
+ 
+ 2026-02-10  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-02-06  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/123940
+ 	* tree-ssa-math-opts.cc (convert_mult_to_fma): Check
+ 	multiplication result is an addend.
+ 
+ 2026-02-10  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-02-05  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	PR target/123870
+ 	PR target/123969
+ 	* config/riscv/vector.md: Add vlds to "no ratio" for
+ 	theadvector.
+ 
+ 2026-02-10  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-02-05  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	PR target/123971
+ 	* config/riscv/riscv.cc (riscv_vector_mode_supported_any_target_p):
+ 	Remove TARGET_XTHEADVECTOR.
+ 
+ 2026-02-10  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-01-29  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	PR target/123806
+ 	* config/riscv/riscv-string.cc (expand_rawmemchr): Use unified
+ 	vl_read.
+ 	(expand_strcmp): Ditto.
+ 	* config/riscv/riscv-vector-builtins-bases.cc:
+ 	* config/riscv/riscv-vector-builtins.cc (function_expander::use_fof_load_insn):
+ 	Only emit the store and not the VL read.
+ 	* config/riscv/riscv-vsetvl.cc (get_fof_set_vl_reg): New
+ 	function.
+ 	(init_rtl_ssa): New wrapper.
+ 	(finish_rtl_ssa): Ditto.
+ 	(emit_fof_read_vls): Emit read_vl after each fault-only-first
+ 	load.
+ 	(pass_vsetvl::simple_vsetvl): Call emit_fof_read_vls ().
+ 	(pass_vsetvl::lazy_vsetvl): Ditto.
+ 	* config/riscv/vector-iterators.md: Add read_vl unspec.
+ 	* config/riscv/vector.md (read_vlsi): Unify.
+ 	(@read_vl<mode>): Ditto.
+ 	(read_vldi_zero_extend): Ditto.
+ 	(@pred_fault_load_set_vl<V_VLS:mode><P:mode>): New FoF variant
+ 	that saves VL in a register.
+ 	(@pred_fault_load_set_vl<VT:mode><P:mode>): Ditto.
+ 
+ 2026-02-10  Jeff Law  <jeffrey.law@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-01-19  Jeff Law  <jeffrey.law@oss.qualcomm.com>
+ 
+ 	PR rtl-optimization/121787
+ 	* config/riscv/riscv-vsetvl.cc (pre_vsetvl): Adjust call to
+ 	loop_optimizer_init to avoid making CFG changes.
+ 
+ 2026-02-10  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-01-22  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	PR target/122869
+ 	* config/riscv/riscv-vector-builtins-bases.cc (fold_fault_load):
+ 	Remove
+ 	* config/riscv/riscv-vector-builtins.cc (function_expander::use_contiguous_load_insn):
+ 	Use new helper.
+ 	(function_expander::prepare_contiguous_load_insn): New helper.
+ 	(function_expander::use_fof_load_insn): New function to emit FoF
+ 	loads.
+ 	* config/riscv/riscv-vector-builtins.h: Declare new functions.
+ 
+ 2026-02-10  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	Backported from master:
+ 	2026-02-10  Kyrylo Tkachov  <ktkachov@nvidia.com>
+ 
+ 	* config/aarch64/tuning_models/olympus.h (olympus_sve_vector_cost):
+ 	Set align_load_cost to 6.
+ 
+ 2026-02-09  LIU Hao  <lh_mouse@126.com>
+ 
+ 	Backported from master:
+ 	2025-05-06  LIU Hao  <lh_mouse@126.com>
+ 
+ 	PR pch/14940
+ 	* config/i386/host-mingw32.cc (mingw32_gt_pch_use_address):
+ 	Replace the loop that attempted to map the PCH only to its
+ 	original address with more adaptive operations
+ 
+ 2026-02-09  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-01-21  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	PR target/122781
+ 	* config/s390/vector.md: Don't emulate vec_cmpgtu for 128-bit
+ 	integers for VXE3.
+ 
  2026-02-06  xiezhiheng  <xiezhiheng@huawei.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20260207/gcc/DATESTAMP gcc-15-20260214/gcc/DATESTAMP
*** gcc-15-20260207/gcc/DATESTAMP	Sat Feb  7 22:32:06 2026
--- gcc-15-20260214/gcc/DATESTAMP	Sat Feb 14 22:32:05 2026
***************
*** 1 ****
! 20260207
--- 1 ----
! 20260214
diff -Nrcpad gcc-15-20260207/gcc/ada/ChangeLog gcc-15-20260214/gcc/ada/ChangeLog
*** gcc-15-20260207/gcc/ada/ChangeLog	Sat Feb  7 22:32:06 2026
--- gcc-15-20260214/gcc/ada/ChangeLog	Sat Feb 14 22:32:05 2026
***************
*** 1,3 ****
--- 1,17 ----
+ 2026-02-11  Eric Botcazou  <ebotcazou@adacore.com>
+ 	    Liam Powell  <liam@liampwll.com>
+ 
+ 	PR ada/124054
+ 	* exp_util.adb (Build_Allocate_Deallocate_Proc): Tidy up and pass
+ 	Proc_Id as the new scope in the call to the New_Copy_Tree function.
+ 
+ 2026-02-09  Eric Botcazou  <ebotcazou@adacore.com>
+ 	    Liam Powell  <liam@liampwll.com>
+ 
+ 	PR ada/124025
+ 	* exp_ch9.adb (Expand_Entry_Barrier.Is_Global_Entity): Use
+ 	Scope_Within_Or_Same to test whether the object is local.
+ 
  2026-02-01  Eric Botcazou  <ebotcazou@adacore.com>
  	    Liam Powell  <liam@liampwll.com>
  
diff -Nrcpad gcc-15-20260207/gcc/ada/exp_ch9.adb gcc-15-20260214/gcc/ada/exp_ch9.adb
*** gcc-15-20260207/gcc/ada/exp_ch9.adb	Sat Feb  7 22:32:06 2026
--- gcc-15-20260214/gcc/ada/exp_ch9.adb	Sat Feb 14 22:32:05 2026
*************** package body Exp_Ch9 is
*** 5824,5830 ****
                 --  during expansion, it is ok. If expansion is not performed,
                 --  then Func is Empty so this test cannot succeed.
  
!                if Scope (E) = Func_Id then
                    null;
  
                 --  A protected call from a barrier to another object is ok
--- 5824,5830 ----
                 --  during expansion, it is ok. If expansion is not performed,
                 --  then Func is Empty so this test cannot succeed.
  
!                if Scope_Within_Or_Same (S, Func_Id) then
                    null;
  
                 --  A protected call from a barrier to another object is ok
diff -Nrcpad gcc-15-20260207/gcc/ada/exp_util.adb gcc-15-20260214/gcc/ada/exp_util.adb
*** gcc-15-20260207/gcc/ada/exp_util.adb	Sat Feb  7 22:32:06 2026
--- gcc-15-20260214/gcc/ada/exp_util.adb	Sat Feb 14 22:32:05 2026
*************** package body Exp_Util is
*** 971,993 ****
           Size_Id : constant Entity_Id := Make_Temporary (Loc, 'S');
  
           Actuals      : List_Id;
!          Alloc_Expr   : Node_Id := Empty;
           Fin_Coll_Id  : Entity_Id;
           Proc_To_Call : Entity_Id;
           Ptr_Coll_Id  : Entity_Id;
!          Subpool      : Node_Id := Empty;
  
        begin
!          --  When we are building an allocator procedure, extract the allocator
!          --  node for later processing and calculation of alignment.
! 
!          if Is_Allocate then
!             --  Extract the qualified expression if there is one from the
!             --  allocator.
  
!             if Nkind (Expression (Expr)) = N_Qualified_Expression then
!                Alloc_Expr := Expression (Expr);
!             end if;
           end if;
  
           --  Step 1: Construct all the actuals for the call to library routine
--- 971,992 ----
           Size_Id : constant Entity_Id := Make_Temporary (Loc, 'S');
  
           Actuals      : List_Id;
!          Alloc_Expr   : Node_Id;
           Fin_Coll_Id  : Entity_Id;
           Proc_To_Call : Entity_Id;
           Ptr_Coll_Id  : Entity_Id;
!          Subpool      : Node_Id;
  
        begin
!          --  When we are building an allocator procedure, extract the qualified
!          --  expression from the allocator if there is one.
  
!          if Is_Allocate
!            and then Nkind (Expression (Expr)) = N_Qualified_Expression
!          then
!             Alloc_Expr := Expression (Expr);
!          else
!             Alloc_Expr := Empty;
           end if;
  
           --  Step 1: Construct all the actuals for the call to library routine
*************** package body Exp_Util is
*** 1001,1015 ****
  
              --  b) Subpool
  
!             if Nkind (Expr) = N_Allocator then
!                Subpool := Subpool_Handle_Name (Expr);
!             end if;
  
              --  If a subpool is present it can be an arbitrary name, so make
              --  the actual by copying the tree.
  
              if Present (Subpool) then
!                Append_To (Actuals, New_Copy_Tree (Subpool, New_Sloc => Loc));
              else
                 Append_To (Actuals, Make_Null (Loc));
              end if;
--- 1000,1013 ----
  
              --  b) Subpool
  
!             Subpool := Subpool_Handle_Name (Expr);
  
              --  If a subpool is present it can be an arbitrary name, so make
              --  the actual by copying the tree.
  
              if Present (Subpool) then
!                Append_To
!                  (Actuals, New_Copy_Tree (Subpool, New_Scope => Proc_Id));
              else
                 Append_To (Actuals, Make_Null (Loc));
              end if;
diff -Nrcpad gcc-15-20260207/gcc/config/aarch64/aarch64-protos.h gcc-15-20260214/gcc/config/aarch64/aarch64-protos.h
*** gcc-15-20260207/gcc/config/aarch64/aarch64-protos.h	Sat Feb  7 22:32:06 2026
--- gcc-15-20260214/gcc/config/aarch64/aarch64-protos.h	Sat Feb 14 22:32:06 2026
*************** bool aarch64_uimm12_shift (unsigned HOST
*** 970,975 ****
--- 970,976 ----
  int aarch64_movk_shift (const wide_int_ref &, const wide_int_ref &);
  bool aarch64_is_mov_xn_imm (unsigned HOST_WIDE_INT);
  bool aarch64_use_return_insn_p (void);
+ bool aarch64_use_simple_return_insn_p (void);
  const char *aarch64_output_casesi (rtx *);
  const char *aarch64_output_load_tp (rtx);
  const char *aarch64_output_sme_zero_za (rtx);
diff -Nrcpad gcc-15-20260207/gcc/config/aarch64/aarch64.cc gcc-15-20260214/gcc/config/aarch64/aarch64.cc
*** gcc-15-20260207/gcc/config/aarch64/aarch64.cc	Sat Feb  7 22:32:06 2026
--- gcc-15-20260214/gcc/config/aarch64/aarch64.cc	Sat Feb 14 22:32:06 2026
*************** aarch64_use_return_insn_p (void)
*** 10110,10115 ****
--- 10110,10129 ----
    return known_eq (cfun->machine->frame.frame_size, 0);
  }
  
+ /* Return false for locally streaming functions in order to avoid
+    shrink-wrapping them.  Shrink-wrapping is unsafe when the function prologue
+    and epilogue contain streaming state change, because these implicitly change
+    the meaning of poly_int values.  */
+ 
+ bool
+ aarch64_use_simple_return_insn_p (void)
+ {
+   if (aarch64_cfun_enables_pstate_sm ())
+     return false;
+ 
+   return true;
+ }
+ 
  /* Generate the epilogue instructions for returning from a function.
     This is almost exactly the reverse of the prolog sequence, except
     that we need to insert barriers to avoid scheduling loads that read
diff -Nrcpad gcc-15-20260207/gcc/config/aarch64/aarch64.md gcc-15-20260214/gcc/config/aarch64/aarch64.md
*** gcc-15-20260207/gcc/config/aarch64/aarch64.md	Sat Feb  7 22:32:06 2026
--- gcc-15-20260214/gcc/config/aarch64/aarch64.md	Sat Feb 14 22:32:06 2026
***************
*** 1116,1122 ****
  
  (define_insn "simple_return"
    [(simple_return)]
!   ""
    {
      output_asm_insn ("ret", operands);
      return aarch64_sls_barrier (aarch64_harden_sls_retbr_p ());
--- 1116,1122 ----
  
  (define_insn "simple_return"
    [(simple_return)]
!   "aarch64_use_simple_return_insn_p ()"
    {
      output_asm_insn ("ret", operands);
      return aarch64_sls_barrier (aarch64_harden_sls_retbr_p ());
diff -Nrcpad gcc-15-20260207/gcc/config/aarch64/tuning_models/olympus.h gcc-15-20260214/gcc/config/aarch64/tuning_models/olympus.h
*** gcc-15-20260207/gcc/config/aarch64/tuning_models/olympus.h	Sat Feb  7 22:32:06 2026
--- gcc-15-20260214/gcc/config/aarch64/tuning_models/olympus.h	Sat Feb 14 22:32:06 2026
*************** static sve_vec_cost olympus_sve_vector_c
*** 75,81 ****
      2, /* store_elt_extra_cost  */
      8, /* vec_to_scalar_cost  */
      4, /* scalar_to_vec_cost  */
!     4, /* align_load_cost  */
      6, /* unalign_load_cost  */
      1, /* unalign_store_cost  */
      1  /* store_cost  */
--- 75,81 ----
      2, /* store_elt_extra_cost  */
      8, /* vec_to_scalar_cost  */
      4, /* scalar_to_vec_cost  */
!     6, /* align_load_cost  */
      6, /* unalign_load_cost  */
      1, /* unalign_store_cost  */
      1  /* store_cost  */
diff -Nrcpad gcc-15-20260207/gcc/config/i386/host-mingw32.cc gcc-15-20260214/gcc/config/i386/host-mingw32.cc
*** gcc-15-20260207/gcc/config/i386/host-mingw32.cc	Sat Feb  7 22:32:06 2026
--- gcc-15-20260214/gcc/config/i386/host-mingw32.cc	Sat Feb 14 22:32:06 2026
*************** mingw32_gt_pch_use_address (void *&addr,
*** 135,141 ****
       and earlier, backslashes are invalid in object name.  So, we need
       to check if we are on Windows2000 or higher.  */
    OSVERSIONINFO version_info;
-   int r;
  
    version_info.dwOSVersionInfoSize = sizeof (version_info);
  
--- 135,140 ----
*************** mingw32_gt_pch_use_address (void *&addr,
*** 169,193 ****
        return -1;
      }
  
!   /* Retry five times, as here might occure a race with multiple gcc's
!      instances at same time.  */
!   for (r = 0; r < 5; r++)
!    {
!       mmap_addr = MapViewOfFileEx (mmap_handle, FILE_MAP_COPY, 0, offset,
! 				   size, addr);
!       if (mmap_addr == addr)
! 	break;
!       if (r != 4)
!         Sleep (500);
!    }
! 
!   if (mmap_addr != addr)
      {
!       w32_error (__FUNCTION__, __FILE__, __LINE__, "MapViewOfFileEx");
!       CloseHandle(mmap_handle);
!       return  -1;
      }
  
    return 1;
  }
  
--- 168,191 ----
        return -1;
      }
  
!   /* Try mapping the file at `addr`.  */
!   mmap_addr = MapViewOfFileEx (mmap_handle, FILE_MAP_COPY, 0, offset,
! 			       size, addr);
!   if (mmap_addr == NULL)
      {
!       /* We could not map the file at its original address, so let the
! 	 system choose a different one. The PCH can be relocated later.  */
!       mmap_addr = MapViewOfFileEx (mmap_handle, FILE_MAP_COPY, 0, offset,
! 				   size, NULL);
!       if (mmap_addr == NULL)
! 	{
! 	  w32_error (__FUNCTION__, __FILE__, __LINE__, "MapViewOfFileEx");
! 	  CloseHandle(mmap_handle);
! 	  return  -1;
! 	}
      }
  
+   addr = mmap_addr;
    return 1;
  }
  
diff -Nrcpad gcc-15-20260207/gcc/config/riscv/riscv-string.cc gcc-15-20260214/gcc/config/riscv/riscv-string.cc
*** gcc-15-20260207/gcc/config/riscv/riscv-string.cc	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/config/riscv/riscv-string.cc	Sat Feb 14 22:32:06 2026
*************** expand_rawmemchr (machine_mode mode, rtx
*** 1377,1386 ****
  		   riscv_vector::UNARY_OP, vlops);
  
    /* Read how far we read.  */
!   if (Pmode == SImode)
!     emit_insn (gen_read_vlsi (cnt));
!   else
!     emit_insn (gen_read_vldi_zero_extend (cnt));
  
    /* Compare needle with haystack and store in a mask.  */
    rtx eq = gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, needle), vec);
--- 1377,1383 ----
  		   riscv_vector::UNARY_OP, vlops);
  
    /* Read how far we read.  */
!   emit_insn (gen_read_vl (Pmode, cnt));
  
    /* Compare needle with haystack and store in a mask.  */
    rtx eq = gen_rtx_EQ (mask_mode, gen_const_vec_duplicate (vmode, needle), vec);
*************** expand_strcmp (rtx result, rtx src1, rtx
*** 1493,1502 ****
      }
  
    /* Read the vl for the next pointer bump.  */
!   if (Pmode == SImode)
!     emit_insn (gen_read_vlsi (cnt));
!   else
!     emit_insn (gen_read_vldi_zero_extend (cnt));
  
    if (with_length)
      {
--- 1490,1496 ----
      }
  
    /* Read the vl for the next pointer bump.  */
!   emit_insn (gen_read_vl (Pmode, cnt));
  
    if (with_length)
      {
diff -Nrcpad gcc-15-20260207/gcc/config/riscv/riscv-vector-builtins-bases.cc gcc-15-20260214/gcc/config/riscv/riscv-vector-builtins-bases.cc
*** gcc-15-20260207/gcc/config/riscv/riscv-vector-builtins-bases.cc	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/config/riscv/riscv-vector-builtins-bases.cc	Sat Feb 14 22:32:06 2026
*************** enum lst_type
*** 58,111 ****
    LST_INDEXED,
  };
  
- /* Helper function to fold vleff and vlsegff.  */
- static gimple *
- fold_fault_load (gimple_folder &f)
- {
-   /* fold fault_load (const *base, size_t *new_vl, size_t vl)
- 
-      ====> fault_load (const *base, size_t vl)
- 	   new_vl = MEM_REF[read_vl ()].  */
- 
-   auto_vec<tree> vargs (gimple_call_num_args (f.call) - 1);
- 
-   for (unsigned i = 0; i < gimple_call_num_args (f.call); i++)
-     {
-       /* Exclude size_t *new_vl argument.  */
-       if (i == gimple_call_num_args (f.call) - 2)
- 	continue;
- 
-       vargs.quick_push (gimple_call_arg (f.call, i));
-     }
- 
-   gimple *repl = gimple_build_call_vec (gimple_call_fn (f.call), vargs);
-   gimple_call_set_lhs (repl, f.lhs);
- 
-   /* Handle size_t *new_vl by read_vl.  */
-   tree new_vl = gimple_call_arg (f.call, gimple_call_num_args (f.call) - 2);
-   if (integer_zerop (new_vl))
-     {
-       /* This case happens when user passes the nullptr to new_vl argument.
- 	 In this case, we just need to ignore the new_vl argument and return
- 	 fault_load instruction directly. */
-       return repl;
-     }
- 
-   tree tmp_var = create_tmp_var (size_type_node, "new_vl");
-   tree decl = get_read_vl_decl ();
-   gimple *g = gimple_build_call (decl, 0);
-   gimple_call_set_lhs (g, tmp_var);
-   tree indirect
-     = fold_build2 (MEM_REF, size_type_node,
- 		   gimple_call_arg (f.call, gimple_call_num_args (f.call) - 2),
- 		   build_int_cst (build_pointer_type (size_type_node), 0));
-   gassign *assign = gimple_build_assign (indirect, tmp_var);
- 
-   gsi_insert_after (f.gsi, assign, GSI_SAME_STMT);
-   gsi_insert_after (f.gsi, g, GSI_SAME_STMT);
-   return repl;
- }
- 
  /* Implements vsetvl<mode> && vsetvlmax<mode>.  */
  template<bool VLMAX_P>
  class vsetvl : public function_base
--- 58,63 ----
*************** public:
*** 1925,1934 ****
  
    rtx expand (function_expander &e) const override
    {
!     if (Pmode == SImode)
!       emit_insn (gen_read_vlsi (e.target));
!     else
!       emit_insn (gen_read_vldi_zero_extend (e.target));
      return e.target;
    }
  };
--- 1877,1883 ----
  
    rtx expand (function_expander &e) const override
    {
!     emit_insn (gen_read_vl (Pmode, e.target));
      return e.target;
    }
  };
*************** public:
*** 1946,1960 ****
      return pred != PRED_TYPE_none;
    }
  
-   gimple *fold (gimple_folder &f) const override
-   {
-     return fold_fault_load (f);
-   }
- 
    rtx expand (function_expander &e) const override
    {
!     return e.use_contiguous_load_insn (
!       code_for_pred_fault_load (e.vector_mode ()));
    }
  };
  
--- 1895,1903 ----
      return pred != PRED_TYPE_none;
    }
  
    rtx expand (function_expander &e) const override
    {
!     return e.use_fof_load_insn ();
    }
  };
  
*************** public:
*** 2122,2136 ****
      return pred != PRED_TYPE_none;
    }
  
-   gimple *fold (gimple_folder &f) const override
-   {
-     return fold_fault_load (f);
-   }
- 
    rtx expand (function_expander &e) const override
    {
!     return e.use_contiguous_load_insn
!       (code_for_pred_fault_load (e.vector_mode ()));
    }
  };
  
--- 2065,2073 ----
      return pred != PRED_TYPE_none;
    }
  
    rtx expand (function_expander &e) const override
    {
!     return e.use_fof_load_insn ();
    }
  };
  
diff -Nrcpad gcc-15-20260207/gcc/config/riscv/riscv-vector-builtins.cc gcc-15-20260214/gcc/config/riscv/riscv-vector-builtins.cc
*** gcc-15-20260207/gcc/config/riscv/riscv-vector-builtins.cc	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/config/riscv/riscv-vector-builtins.cc	Sat Feb 14 22:32:06 2026
*************** function_expander::use_exact_insn (insn_
*** 4244,4252 ****
    return generate_insn (icode);
  }
  
! /* Use contiguous load INSN.  */
! rtx
! function_expander::use_contiguous_load_insn (insn_code icode)
  {
    gcc_assert (call_expr_nargs (exp) > 0);
    machine_mode mode = TYPE_MODE (TREE_TYPE (exp));
--- 4244,4251 ----
    return generate_insn (icode);
  }
  
! int
! function_expander::prepare_contiguous_load_insn ()
  {
    gcc_assert (call_expr_nargs (exp) > 0);
    machine_mode mode = TYPE_MODE (TREE_TYPE (exp));
*************** function_expander::use_contiguous_load_i
*** 4265,4274 ****
--- 4264,4282 ----
      add_vundef_operand (mode);
  
    add_mem_operand (mode, arg_offset++);
+   return arg_offset;
+ }
+ 
+ /* Use contiguous load INSN.  */
+ rtx
+ function_expander::use_contiguous_load_insn (insn_code icode)
+ {
+   int arg_offset = prepare_contiguous_load_insn ();
  
    for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
      add_input_operand (argno);
  
+   machine_mode mode = TYPE_MODE (TREE_TYPE (exp));
    if (GET_MODE_CLASS (mode) != MODE_VECTOR_BOOL)
      {
        add_input_operand (Pmode, get_tail_policy_for_pred (pred));
*************** function_expander::use_contiguous_load_i
*** 4277,4286 ****
  
    if (opno != insn_data[icode].n_generator_args)
      add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
- 
    return generate_insn (icode);
  }
  
  /* Use contiguous store INSN.  */
  rtx
  function_expander::use_contiguous_store_insn (insn_code icode)
--- 4285,4342 ----
  
    if (opno != insn_data[icode].n_generator_args)
      add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
    return generate_insn (icode);
  }
  
+ /* Similar to use_contiguous_load_insn but skips the vector-length destination
+    operand that a fault-only-first load intrinsic has.  Then we add tail and
+    mask policy as well as AVL operand.  Last, add the vector-length destination
+    operand that we skipped initially.  */
+ rtx
+ function_expander::use_fof_load_insn ()
+ {
+   int arg_offset = prepare_contiguous_load_insn ();
+ 
+   int vl_dest_arg = call_expr_nargs (exp) - 2;
+   for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)
+     {
+       /* Skip argument for VL destination in memory but add the others.  */
+       if (argno != vl_dest_arg)
+ 	add_input_operand (argno);
+     }
+ 
+   machine_mode mode = TYPE_MODE (TREE_TYPE (exp));
+   if (GET_MODE_CLASS (mode) != MODE_VECTOR_BOOL)
+     {
+       add_input_operand (Pmode, get_tail_policy_for_pred (pred));
+       add_input_operand (Pmode, get_mask_policy_for_pred (pred));
+     }
+ 
+   add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
+ 
+   tree arg = CALL_EXPR_ARG (exp, vl_dest_arg);
+ 
+   /* Use a regular FoF load if the user does not want to store VL.  */
+   if (integer_zerop (arg))
+     {
+       insn_code icode = code_for_pred_fault_load (mode);
+       return generate_insn (icode);
+     }
+ 
+   /* The VL-setting FoF load writes the new VL to VL_REG.
+      Store it to memory.  */
+   rtx vl_reg = gen_reg_rtx (Pmode);
+   add_output_operand (Pmode, vl_reg);
+   insn_code icode = code_for_pred_fault_load_set_vl (mode, Pmode);
+   rtx res = generate_insn (icode);
+ 
+   rtx addr = expand_normal (arg);
+   rtx mem = gen_rtx_MEM (Pmode, memory_address (Pmode, addr));
+   emit_move_insn (mem, vl_reg);
+ 
+   return res;
+ }
+ 
  /* Use contiguous store INSN.  */
  rtx
  function_expander::use_contiguous_store_insn (insn_code icode)
diff -Nrcpad gcc-15-20260207/gcc/config/riscv/riscv-vector-builtins.h gcc-15-20260214/gcc/config/riscv/riscv-vector-builtins.h
*** gcc-15-20260207/gcc/config/riscv/riscv-vector-builtins.h	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/config/riscv/riscv-vector-builtins.h	Sat Feb 14 22:32:06 2026
*************** public:
*** 513,519 ****
--- 513,521 ----
    machine_mode ret_mode (void) const;
  
    rtx use_exact_insn (insn_code);
+   int prepare_contiguous_load_insn ();
    rtx use_contiguous_load_insn (insn_code);
+   rtx use_fof_load_insn ();
    rtx use_contiguous_store_insn (insn_code);
    rtx use_compare_insn (rtx_code, insn_code);
    rtx use_ternop_insn (bool, insn_code);
diff -Nrcpad gcc-15-20260207/gcc/config/riscv/riscv-vsetvl.cc gcc-15-20260214/gcc/config/riscv/riscv-vsetvl.cc
*** gcc-15-20260207/gcc/config/riscv/riscv-vsetvl.cc	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/config/riscv/riscv-vsetvl.cc	Sat Feb 14 22:32:06 2026
*************** fault_first_load_p (rtx_insn *rinsn)
*** 294,299 ****
--- 294,380 ----
  	     || get_attr_type (rinsn) == TYPE_VLSEGDFF);
  }
  
+ /* Return the VL output register from a fault-only-first load with VL
+    output (pred_fault_load_set_vl pattern) if RINSN is such an insn
+    or NULL_RTX otherwise.
+    The pattern has: (set vl_output (unspec:P [(reg:SI VL_REGNUM)]
+ 					     UNSPEC_READ_VL))  */
+ static rtx
+ get_fof_set_vl_reg (rtx_insn *rinsn)
+ {
+   if (!fault_first_load_p (rinsn))
+     return NULL_RTX;
+ 
+   rtx pat = PATTERN (rinsn);
+   if (GET_CODE (pat) != PARALLEL)
+     return NULL_RTX;
+ 
+   if (XVECLEN (pat, 0) != 3)
+     return NULL_RTX;
+ 
+   rtx sub = XVECEXP (pat, 0, 2);
+   if (GET_CODE (sub) == SET
+       && GET_CODE (SET_SRC (sub)) == UNSPEC
+       && XINT (SET_SRC (sub), 1) == UNSPEC_READ_VL)
+     return SET_DEST (sub);
+ 
+   return NULL_RTX;
+ }
+ 
+ /* Initialize RTL SSA and related infrastructure for vsetvl analysis.  */
+ static void
+ init_rtl_ssa ()
+ {
+   calculate_dominance_info (CDI_DOMINATORS);
+   loop_optimizer_init (AVOID_CFG_MODIFICATIONS);
+   connect_infinite_loops_to_exit ();
+   df_analyze ();
+   crtl->ssa = new function_info (cfun);
+ }
+ 
+ /* Finalize RTL SSA and cleanup.  */
+ static void
+ finish_rtl_ssa ()
+ {
+   free_dominance_info (CDI_DOMINATORS);
+   loop_optimizer_finalize ();
+   if (crtl->ssa->perform_pending_updates ())
+     cleanup_cfg (0);
+   delete crtl->ssa;
+   crtl->ssa = nullptr;
+ }
+ 
+ /* Emit read_vl instructions after fault-only-first loads that have
+    a VL output register.
+    This needs to happen last, i.e. when we made the VL dataflow
+    explicit by inserting vsetvls.  */
+ 
+ static void
+ emit_fof_read_vls ()
+ {
+   basic_block bb;
+   rtx_insn *rinsn;
+ 
+   FOR_EACH_BB_FN (bb, cfun)
+     FOR_BB_INSNS (bb, rinsn)
+       {
+ 	if (!NONDEBUG_INSN_P (rinsn))
+ 	  continue;
+ 
+ 	rtx vl_dest = get_fof_set_vl_reg (rinsn);
+ 	if (!vl_dest)
+ 	  continue;
+ 
+ 	if (dump_file)
+ 	  fprintf (dump_file,
+ 		   "  Inserting read_vl after FoF insn %d into r%d\n",
+ 		   INSN_UID (rinsn), REGNO (vl_dest));
+ 
+ 	rtx read_vl_pat = gen_read_vl (Pmode, vl_dest);
+ 	emit_insn_after (read_vl_pat, rinsn);
+       }
+ }
+ 
  /* Return true if the instruction is read vl instruction.  */
  static bool
  read_vl_insn_p (rtx_insn *rinsn)
*************** public:
*** 1188,1193 ****
--- 1269,1281 ----
  		break;
  	      }
  	  }
+ 	/* If no csrr found but this is a _set_vl style fault-only-first
+ 	   load, use the insn itself as the VL source.
+ 	   If we have two identical vector configs that just differ in
+ 	   AVL and the AVL is just "modified" by a read_vl we
+ 	   can consider them equal and elide the second one.  */
+ 	if (!m_read_vl_insn && get_fof_set_vl_reg (insn->rtl ()))
+ 	  m_read_vl_insn = insn;
        }
    }
  
*************** public:
*** 2422,2434 ****
        m_avin (nullptr), m_avout (nullptr), m_kill (nullptr), m_antloc (nullptr),
        m_transp (nullptr), m_insert (nullptr), m_del (nullptr), m_edges (nullptr)
    {
!     /* Initialization of RTL_SSA.  */
!     calculate_dominance_info (CDI_DOMINATORS);
!     loop_optimizer_init (LOOPS_NORMAL);
!     /* Create FAKE edges for infinite loops.  */
!     connect_infinite_loops_to_exit ();
!     df_analyze ();
!     crtl->ssa = new function_info (cfun);
      m_vector_block_infos.safe_grow_cleared (last_basic_block_for_fn (cfun));
      compute_probabilities ();
      m_unknown_info.set_unknown ();
--- 2510,2516 ----
        m_avin (nullptr), m_avout (nullptr), m_kill (nullptr), m_antloc (nullptr),
        m_transp (nullptr), m_insert (nullptr), m_del (nullptr), m_edges (nullptr)
    {
!     init_rtl_ssa ();
      m_vector_block_infos.safe_grow_cleared (last_basic_block_for_fn (cfun));
      compute_probabilities ();
      m_unknown_info.set_unknown ();
*************** public:
*** 2436,2447 ****
  
    void finish ()
    {
!     free_dominance_info (CDI_DOMINATORS);
!     loop_optimizer_finalize ();
!     if (crtl->ssa->perform_pending_updates ())
!       cleanup_cfg (0);
!     delete crtl->ssa;
!     crtl->ssa = nullptr;
  
      if (m_reg_def_loc)
        sbitmap_vector_free (m_reg_def_loc);
--- 2518,2524 ----
  
    void finish ()
    {
!     finish_rtl_ssa ();
  
      if (m_reg_def_loc)
        sbitmap_vector_free (m_reg_def_loc);
*************** pass_vsetvl::simple_vsetvl ()
*** 3612,3617 ****
--- 3689,3699 ----
  	    }
  	}
      }
+ 
+   if (dump_file)
+     fprintf (dump_file, "\nEmit missing read_vl()s for fault-only-first "
+ 	     "loads\n");
+   emit_fof_read_vls ();
  }
  
  /* Lazy vsetvl insertion for optimize > 0. */
*************** pass_vsetvl::lazy_vsetvl ()
*** 3660,3665 ****
--- 3742,3754 ----
  	     "\nPhase 4: Insert, modify and remove vsetvl insns.\n\n");
    pre.emit_vsetvl ();
  
+   /* Phase 4b: Emit read_vl for fault-only-first loads with VL output
+      register.  */
+   if (dump_file)
+     fprintf (dump_file, "\nPhase 4b: Emit missing read_vl()s for "
+ 	     "fault-only-first loads\n");
+   emit_fof_read_vls ();
+ 
    /* Phase 5: Cleanup */
    if (dump_file)
      fprintf (dump_file, "\nPhase 5: Cleanup\n\n");
diff -Nrcpad gcc-15-20260207/gcc/config/riscv/riscv.cc gcc-15-20260214/gcc/config/riscv/riscv.cc
*** gcc-15-20260207/gcc/config/riscv/riscv.cc	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/config/riscv/riscv.cc	Sat Feb 14 22:32:06 2026
*************** extract_base_offset_in_addr (rtx mem, rt
*** 12642,12649 ****
  static bool
  riscv_vector_mode_supported_any_target_p (machine_mode)
  {
-   if (TARGET_XTHEADVECTOR)
-     return false;
    return true;
  }
  
--- 12642,12647 ----
diff -Nrcpad gcc-15-20260207/gcc/config/riscv/vector-iterators.md gcc-15-20260214/gcc/config/riscv/vector-iterators.md
*** gcc-15-20260207/gcc/config/riscv/vector-iterators.md	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/config/riscv/vector-iterators.md	Sat Feb 14 22:32:06 2026
***************
*** 79,84 ****
--- 79,85 ----
    UNSPEC_VCOMPRESS
    UNSPEC_VLEFF
    UNSPEC_MODIFY_VL
+   UNSPEC_READ_VL
  
    UNSPEC_VFFMA
  
diff -Nrcpad gcc-15-20260207/gcc/config/riscv/vector.md gcc-15-20260214/gcc/config/riscv/vector.md
*** gcc-15-20260207/gcc/config/riscv/vector.md	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/config/riscv/vector.md	Sat Feb 14 22:32:06 2026
***************
*** 491,498 ****
  			  vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,\
  			  vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
  	   (const_int INVALID_ATTRIBUTE)
! 	(and (eq_attr "type" "vlde,vste,vlsegde,vssegte,vlsegds,vssegts,\
! 			       vlsegdff,vssegtux,vlsegdox,vlsegdux")
  	      (match_test "TARGET_XTHEADVECTOR"))
  	   (const_int INVALID_ATTRIBUTE)
  	 (eq_attr "mode" "RVVM8QI,RVVM1BI") (const_int 1)
--- 491,498 ----
  			  vaeskf1,vaeskf2,vaesz,vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,\
  			  vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16")
  	   (const_int INVALID_ATTRIBUTE)
! 	(and (eq_attr "type" "vlde,vste,vlds,vsts,vlsegde,vssegte,vlsegds,\
! 			      vssegts,vlsegdff,vssegtux,vlsegdox,vlsegdux")
  	      (match_test "TARGET_XTHEADVECTOR"))
  	   (const_int INVALID_ATTRIBUTE)
  	 (eq_attr "mode" "RVVM8QI,RVVM1BI") (const_int 1)
***************
*** 8318,8338 ****
  ;; - 7.7. Unit-stride Fault-Only-First Loads
  ;; -------------------------------------------------------------------------------
  
! (define_insn "read_vlsi"
!   [(set (match_operand:SI 0 "register_operand" "=r")
! 	(reg:SI VL_REGNUM))]
    "TARGET_VECTOR"
    "csrr\t%0,vl"
    [(set_attr "type" "rdvl")
!    (set_attr "mode" "SI")])
! 
! (define_insn "read_vldi_zero_extend"
!   [(set (match_operand:DI 0 "register_operand" "=r")
! 	(zero_extend:DI (reg:SI VL_REGNUM)))]
!   "TARGET_VECTOR && TARGET_64BIT"
!   "csrr\t%0,vl"
!   [(set_attr "type" "rdvl")
!    (set_attr "mode" "DI")])
  
  (define_insn "@pred_fault_load<mode>"
    [(set (match_operand:V 0 "register_operand"              "=vd,    vd,    vr,    vr")
--- 8318,8330 ----
  ;; - 7.7. Unit-stride Fault-Only-First Loads
  ;; -------------------------------------------------------------------------------
  
! (define_insn "@read_vl<mode>"
!   [(set (match_operand:P 0 "register_operand" "=r")
! 	(unspec:P [(reg:SI VL_REGNUM)] UNSPEC_READ_VL))]
    "TARGET_VECTOR"
    "csrr\t%0,vl"
    [(set_attr "type" "rdvl")
!    (set_attr "mode" "<MODE>")])
  
  (define_insn "@pred_fault_load<mode>"
    [(set (match_operand:V 0 "register_operand"              "=vd,    vd,    vr,    vr")
***************
*** 8362,8367 ****
--- 8354,8389 ----
    [(set_attr "type" "vldff")
     (set_attr "mode" "<MODE>")])
  
+ (define_insn "@pred_fault_load_set_vl<V_VLS:mode><P:mode>"
+   [(set (match_operand:V_VLS 0 "register_operand"	       "=  vd,    vd,    vr,    vr")
+ 	(if_then_else:V_VLS
+ 	  (unspec:<V_VLS:VM>
+ 	    [(match_operand:<V_VLS:VM> 1 "vector_mask_operand" "   vm,    vm,   Wc1,   Wc1")
+ 	     (match_operand 4 "vector_length_operand"          "  rvl,   rvl,   rvl,   rvl")
+ 	     (match_operand 5 "const_int_operand"              "    i,     i,     i,     i")
+ 	     (match_operand 6 "const_int_operand"              "    i,     i,     i,     i")
+ 	     (match_operand 7 "const_int_operand"              "    i,     i,     i,     i")
+ 	     (reg:SI VL_REGNUM)
+ 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ 	  (unspec:V_VLS
+ 	    [(match_operand:V_VLS 3 "memory_operand"           "    m,     m,     m,     m")] UNSPEC_VLEFF)
+ 	  (match_operand:V_VLS 2 "vector_merge_operand"        "   vu,     0,    vu,     0")))
+    (set (reg:SI VL_REGNUM)
+ 	  (unspec:SI
+ 	    [(if_then_else:V_VLS
+ 	       (unspec:<V_VLS:VM>
+ 		[(match_dup 1) (match_dup 4) (match_dup 5)
+ 		 (match_dup 6) (match_dup 7)
+ 		 (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ 	       (unspec:V_VLS [(match_dup 3)] UNSPEC_VLEFF)
+ 	       (match_dup 2))] UNSPEC_MODIFY_VL))
+    (set (match_operand:P 8 "register_operand"		       "=   r,     r,     r,     r")
+ 	(unspec:P [(reg:SI VL_REGNUM)] UNSPEC_READ_VL))]
+   "TARGET_VECTOR"
+   "vle<sew>ff.v\t%0,%3%p1"
+   [(set_attr "type" "vldff")
+    (set_attr "mode" "<V_VLS:MODE>")])
+ 
  
  ;; -------------------------------------------------------------------------------
  ;; ---- Predicated Segment loads/stores
***************
*** 8479,8484 ****
--- 8501,8539 ----
    [(set_attr "type" "vlsegdff")
     (set_attr "mode" "<MODE>")])
  
+ (define_insn "@pred_fault_load_set_vl<VT:mode><P:mode>"
+   [(set (match_operand:VT 0 "register_operand"              "=  vr,    vr,    vd")
+ 	(if_then_else:VT
+ 	  (unspec:<VT:VM>
+ 	    [(match_operand:<VT:VM> 1 "vector_mask_operand" "vmWc1,   Wc1,    vm")
+ 	     (match_operand 4 "vector_length_operand"       "  rvl,   rvl,   rvl")
+ 	     (match_operand 5 "const_int_operand"           "    i,     i,     i")
+ 	     (match_operand 6 "const_int_operand"           "    i,     i,     i")
+ 	     (match_operand 7 "const_int_operand"           "    i,     i,     i")
+ 	     (reg:SI VL_REGNUM)
+ 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ 	  (unspec:VT
+ 	    [(match_operand:VT 3 "memory_operand"	    "    m,     m,     m")
+ 	     (mem:BLK (scratch))] UNSPEC_VLEFF)
+ 	  (match_operand:VT 2 "vector_merge_operand"        "    0,    vu,    vu")))
+    (set (reg:SI VL_REGNUM)
+         (unspec:SI
+           [(if_then_else:VT
+ 	     (unspec:<VT:VM>
+ 	       [(match_dup 1) (match_dup 4) (match_dup 5)
+ 	        (match_dup 6) (match_dup 7)
+ 	        (reg:SI VL_REGNUM)
+ 	        (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
+ 	     (unspec:VT
+ 	        [(match_dup 3) (mem:BLK (scratch))] UNSPEC_VLEFF)
+ 	     (match_dup 2))] UNSPEC_MODIFY_VL))
+    (set (match_operand:P 8 "register_operand"		    "=   r,     r,     r")
+ 	(unspec:P [(reg:SI VL_REGNUM)] UNSPEC_READ_VL))]
+   "TARGET_VECTOR"
+   "vlseg<nf>e<sew>ff.v\t%0,%3%p1"
+   [(set_attr "type" "vlsegdff")
+    (set_attr "mode" "<VT:MODE>")])
+ 
  (define_insn "@pred_indexed_<order>load<V1T:mode><RATIO64I:mode>"
    [(set (match_operand:V1T 0 "register_operand"           "=&vr,  &vr")
  	(if_then_else:V1T
diff -Nrcpad gcc-15-20260207/gcc/config/s390/vector.md gcc-15-20260214/gcc/config/s390/vector.md
*** gcc-15-20260207/gcc/config/s390/vector.md	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/config/s390/vector.md	Sat Feb 14 22:32:06 2026
***************
*** 2181,2187 ****
    [(set (match_operand:VI_HW_T              0 "register_operand" "=v")
  	(gtu:VI_HW_T (match_operand:VI_HW_T 1 "register_operand"  "v")
  		     (match_operand:VI_HW_T 2 "register_operand"  "v")))]
!   "TARGET_VX"
    "#"
    "&& can_create_pseudo_p ()"
    [(set (match_dup 3)
--- 2181,2187 ----
    [(set (match_operand:VI_HW_T              0 "register_operand" "=v")
  	(gtu:VI_HW_T (match_operand:VI_HW_T 1 "register_operand"  "v")
  		     (match_operand:VI_HW_T 2 "register_operand"  "v")))]
!   "TARGET_VX && !TARGET_VXE3"
    "#"
    "&& can_create_pseudo_p ()"
    [(set (match_dup 3)
diff -Nrcpad gcc-15-20260207/gcc/d/ChangeLog gcc-15-20260214/gcc/d/ChangeLog
*** gcc-15-20260207/gcc/d/ChangeLog	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/d/ChangeLog	Sat Feb 14 22:32:06 2026
***************
*** 1,3 ****
--- 1,12 ----
+ 2026-02-08  Iain Buclaw  <ibuclaw@gdcproject.org>
+ 
+ 	Backported from master:
+ 	2026-02-08  Iain Buclaw  <ibuclaw@gdcproject.org>
+ 
+ 	PR d/124026
+ 	* expr.cc (ExprVisitor::visit (FuncExp *)): Always convert function
+ 	literal to a delegate if the expression expects one.
+ 
  2026-01-30  Iain Buclaw  <ibuclaw@gdcproject.org>
  
  	Backported from master:
diff -Nrcpad gcc-15-20260207/gcc/d/expr.cc gcc-15-20260214/gcc/d/expr.cc
*** gcc-15-20260207/gcc/d/expr.cc	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/d/expr.cc	Sat Feb 14 22:32:06 2026
*************** public:
*** 2034,2060 ****
      /* Compile the declaration.  */
      build_lambda_tree (e->fd, e->type->toBasetype ());
  
!     /* If nested, this will be a trampoline.  */
!     if (e->fd->isNested ())
!       {
! 	tree func = build_address (get_symbol_decl (e->fd));
! 	tree object;
  
! 	if (this->constp_)
  	  {
! 	    /* Static delegate variables have no context pointer.  */
! 	    object = null_pointer_node;
! 	    this->result_ = build_method_call (func, object, e->fd->type);
  	    TREE_CONSTANT (this->result_) = 1;
  	  }
  	else
  	  {
! 	    object = get_frame_for_symbol (e->fd);
  	    this->result_ = build_method_call (func, object, e->fd->type);
  	  }
        }
      else
        {
  	this->result_ = build_nop (build_ctype (e->type),
  				   build_address (get_symbol_decl (e->fd)));
        }
--- 2034,2064 ----
      /* Compile the declaration.  */
      build_lambda_tree (e->fd, e->type->toBasetype ());
  
!     tree func = build_address (get_symbol_decl (e->fd));
!     Type *tb = e->type->toBasetype ();
  
!     /* If a delegate is expected, the literal will be inferred as a delegate
!        even if it accesses no variables from an enclosing function.  */
!     if (tb->ty == TY::Tdelegate)
!       {
! 	/* Static delegate variables have no context pointer.  */
! 	if (this->constp_ || !e->fd->isNested ())
  	  {
! 	    this->result_ = build_method_call (func, null_pointer_node,
! 					       e->fd->type);
  	    TREE_CONSTANT (this->result_) = 1;
  	  }
  	else
  	  {
! 	    gcc_assert (e->fd->isNested ());
! 	    tree object = get_frame_for_symbol (e->fd);
  	    this->result_ = build_method_call (func, object, e->fd->type);
  	  }
        }
      else
        {
+ 	/* The function literal is a function pointer.  */
+ 	gcc_assert (tb->ty == TY::Tpointer);
  	this->result_ = build_nop (build_ctype (e->type),
  				   build_address (get_symbol_decl (e->fd)));
        }
diff -Nrcpad gcc-15-20260207/gcc/expr.cc gcc-15-20260214/gcc/expr.cc
*** gcc-15-20260207/gcc/expr.cc	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/expr.cc	Sat Feb 14 22:32:06 2026
*************** expand_expr_real_1 (tree exp, rtx target
*** 12260,12272 ****
  	   and need be, put it there.  */
  	else if (CONSTANT_P (op0) || (!MEM_P (op0) && must_force_mem))
  	  {
  	    poly_int64 size;
  	    if (!poly_int_tree_p (TYPE_SIZE_UNIT (TREE_TYPE (tem)), &size))
  	      size = max_int_size_in_bytes (TREE_TYPE (tem));
! 	    memloc = assign_stack_local (TYPE_MODE (TREE_TYPE (tem)), size,
! 					 TREE_CODE (tem) == SSA_NAME
! 					 ? TYPE_ALIGN (TREE_TYPE (tem))
! 					 : get_object_alignment (tem));
  	    emit_move_insn (memloc, op0);
  	    op0 = memloc;
  	    clear_mem_expr = true;
--- 12260,12285 ----
  	   and need be, put it there.  */
  	else if (CONSTANT_P (op0) || (!MEM_P (op0) && must_force_mem))
  	  {
+ 	    machine_mode tem_mode = TYPE_MODE (TREE_TYPE (tem));
  	    poly_int64 size;
  	    if (!poly_int_tree_p (TYPE_SIZE_UNIT (TREE_TYPE (tem)), &size))
  	      size = max_int_size_in_bytes (TREE_TYPE (tem));
! 	    unsigned int align = TREE_CODE (tem) == SSA_NAME
! 				 ? TYPE_ALIGN (TREE_TYPE (tem))
! 				 : get_object_alignment (tem);
! 	    if (STRICT_ALIGNMENT)
! 	      {
! 		/* For STRICT_ALIGNMENT targets, when we force the operand to
! 		   memory, we may need to increase the alignment to meet the
! 		   expectation in later RTL lowering passes.  The increased
! 		   alignment is capped by MAX_SUPPORTED_STACK_ALIGNMENT.  */
! 		if (tem_mode != BLKmode)
! 		  align = MAX (align, GET_MODE_ALIGNMENT (tem_mode));
! 		else
! 		  align = MAX (align, TYPE_ALIGN (TREE_TYPE (tem)));
! 		align = MIN (align, (unsigned) MAX_SUPPORTED_STACK_ALIGNMENT);
! 	      }
! 	    memloc = assign_stack_local (tem_mode, size, align);
  	    emit_move_insn (memloc, op0);
  	    op0 = memloc;
  	    clear_mem_expr = true;
diff -Nrcpad gcc-15-20260207/gcc/fortran/check.cc gcc-15-20260214/gcc/fortran/check.cc
*** gcc-15-20260207/gcc/fortran/check.cc	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/fortran/check.cc	Sat Feb 14 22:32:06 2026
*************** array_check (gfc_expr *e, int n)
*** 832,837 ****
--- 832,840 ----
    if (e->rank != 0 && e->ts.type != BT_PROCEDURE)
      return true;
  
+   if (gfc_is_class_array_function (e))
+     return true;
+ 
    gfc_error ("%qs argument of %qs intrinsic at %L must be an array",
  	     gfc_current_intrinsic_arg[n]->name, gfc_current_intrinsic,
  	     &e->where);
diff -Nrcpad gcc-15-20260207/gcc/fortran/class.cc gcc-15-20260214/gcc/fortran/class.cc
*** gcc-15-20260207/gcc/fortran/class.cc	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/fortran/class.cc	Sat Feb 14 22:32:06 2026
*************** gfc_add_class_array_ref (gfc_expr *e)
*** 273,279 ****
    for (ref = e->ref; ref; ref = ref->next)
      if (!ref->next)
        break;
!   if (ref->type != REF_ARRAY)
      {
        ref->next = gfc_get_ref ();
        ref = ref->next;
--- 273,279 ----
    for (ref = e->ref; ref; ref = ref->next)
      if (!ref->next)
        break;
!   if (ref && ref->type != REF_ARRAY)
      {
        ref->next = gfc_get_ref ();
        ref = ref->next;
diff -Nrcpad gcc-15-20260207/gcc/modulo-sched.cc gcc-15-20260214/gcc/modulo-sched.cc
*** gcc-15-20260207/gcc/modulo-sched.cc	Sat Feb  7 22:32:07 2026
--- gcc-15-20260214/gcc/modulo-sched.cc	Sat Feb 14 22:32:07 2026
*************** doloop_register_get (rtx_insn *head, rtx
*** 356,362 ****
      reg = XEXP (condition, 0);
    else if (GET_CODE (XEXP (condition, 0)) == PLUS
  	   && REG_P (XEXP (XEXP (condition, 0), 0)))
!     reg = XEXP (XEXP (condition, 0), 0);
    else
      gcc_unreachable ();
  
--- 356,368 ----
      reg = XEXP (condition, 0);
    else if (GET_CODE (XEXP (condition, 0)) == PLUS
  	   && REG_P (XEXP (XEXP (condition, 0), 0)))
!     {
!       if (CONST_INT_P (XEXP (condition, 1))
! 	  && INTVAL (XEXP (condition, 1)) == -1)
! 	reg = XEXP (XEXP (condition, 0), 0);
!       else
! 	return NULL_RTX;
!     }
    else
      gcc_unreachable ();
  
diff -Nrcpad gcc-15-20260207/gcc/testsuite/ChangeLog gcc-15-20260214/gcc/testsuite/ChangeLog
*** gcc-15-20260207/gcc/testsuite/ChangeLog	Sat Feb  7 22:32:08 2026
--- gcc-15-20260214/gcc/testsuite/ChangeLog	Sat Feb 14 22:32:07 2026
***************
*** 1,3 ****
--- 1,100 ----
+ 2026-02-12  Pengfei Li  <Pengfei.Li2@arm.com>
+ 
+ 	PR middle-end/123447
+ 	* gcc.dg/pr123447.c: New test.
+ 
+ 2026-02-11  Alice Carlotti  <alice.carlotti@arm.com>
+ 
+ 	PR target/123624
+ 	* gcc.target/aarch64/sme/sme-shrinkwrap.c: New test.
+ 
+ 2026-02-11  Eric Botcazou  <ebotcazou@adacore.com>
+ 	    Liam Powell  <liam@liampwll.com>
+ 
+ 	* gnat.dg/allocator4.adb: New test.
+ 
+ 2026-02-11  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+ 
+ 	Backported from master:
+ 	2025-04-25  Andre Vieira  <andre.simoesdiasvieira@arm.com>
+ 
+ 	* gcc.dg/pr116479.c: New test.
+ 
+ 2026-02-10  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-02-06  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	PR tree-optimization/123940
+ 	* gcc.target/riscv/rvv/autovec/pr123940.c: New test.
+ 
+ 2026-02-10  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-02-05  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	PR target/123870
+ 	PR target/123969
+ 	* gcc.target/riscv/rvv/xtheadvector/pr123969.c: New test.
+ 
+ 2026-02-10  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-02-05  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	PR target/123971
+ 	* gcc.target/riscv/rvv/xtheadvector/pr123971.c: New test.
+ 
+ 2026-02-10  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-01-29  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	PR target/123806
+ 	* g++.target/riscv/rvv/base/pr123806.C: New test.
+ 	* g++.target/riscv/rvv/base/pr123808.C: New test.
+ 	* g++.target/riscv/rvv/base/pr123808-2.C: New test.
+ 
+ 2026-02-10  Jeff Law  <jeffrey.law@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-01-19  Jeff Law  <jeffrey.law@oss.qualcomm.com>
+ 
+ 	PR rtl-optimization/121787
+ 	* gcc.target/riscv/pr121787-1.c: New test.
+ 	* gcc.target/riscv/pr121787-2.c: New test.
+ 
+ 2026-02-10  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	Backported from master:
+ 	2026-01-22  Robin Dapp  <rdapp@oss.qualcomm.com>
+ 
+ 	PR target/122869
+ 	* gcc.target/riscv/rvv/base/pr122656-1.c: Remove dg-error.
+ 	* gcc.target/riscv/rvv/vsetvl/ffload-3.c: XFAIL for -O2 and -O3.
+ 	* gcc.target/riscv/rvv/base/pr122869.c: New test.
+ 
+ 2026-02-09  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	Backported from master:
+ 	2026-01-21  Stefan Schulze Frielinghaus  <stefansf@gcc.gnu.org>
+ 
+ 	PR target/122781
+ 	* gcc.target/s390/vxe3/vcmp-1.c: New test.
+ 
+ 2026-02-09  Eric Botcazou  <ebotcazou@adacore.com>
+ 	    Liam Powell  <liam@liampwll.com>
+ 
+ 	* gnat.dg/protected_type1.adb: New test.
+ 
+ 2026-02-08  Iain Buclaw  <ibuclaw@gdcproject.org>
+ 
+ 	Backported from master:
+ 	2026-02-08  Iain Buclaw  <ibuclaw@gdcproject.org>
+ 
+ 	PR d/124026
+ 	* gdc.dg/pr124026.d: New test.
+ 
  2026-02-06  Torbjörn SVENSSON  <torbjorn.svensson@foss.st.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20260207/gcc/testsuite/g++.target/riscv/rvv/base/pr123806.C gcc-15-20260214/gcc/testsuite/g++.target/riscv/rvv/base/pr123806.C
*** gcc-15-20260207/gcc/testsuite/g++.target/riscv/rvv/base/pr123806.C	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/g++.target/riscv/rvv/base/pr123806.C	Sat Feb 14 22:32:09 2026
***************
*** 0 ****
--- 1,25 ----
+ /* { dg-do run */
+ /* { dg-require-effective-target riscv_v_ok } */
+ /* { dg-add-options riscv_v } */
+ 
+ #include <riscv_vector.h>
+ #include <vector>
+ 
+ int8_t a[5], d[5], c[5], b[5];
+ int main() {
+   for (size_t e = 0, avl = 1; avl > 0;) {
+     size_t f = __riscv_vsetvl_e8m1(avl);
+     vint8m1_t g = __riscv_vle8_v_i8m1(&a[e], f);
+     vint8mf2_t i = __riscv_vle8ff(
+         __riscv_vlm_v_b16(std::vector<uint8_t>((f + 7) / 8, 5).data(), f),
+         &b[e], &f, f);
+     vint8m1_t j = __riscv_vle8_v_i8m1(&c[e], f);
+     vint8m1_t k = __riscv_vredxor_tu(g, i, j, f);
+     __riscv_vse8_v_i8m1(&d[e], k, f);
+     avl -= f;
+ 
+     if (f != 1 && avl != 0)
+       __builtin_abort ();
+     break;
+   }
+ }
diff -Nrcpad gcc-15-20260207/gcc/testsuite/g++.target/riscv/rvv/base/pr123808-2.C gcc-15-20260214/gcc/testsuite/g++.target/riscv/rvv/base/pr123808-2.C
*** gcc-15-20260207/gcc/testsuite/g++.target/riscv/rvv/base/pr123808-2.C	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/g++.target/riscv/rvv/base/pr123808-2.C	Sat Feb 14 22:32:09 2026
***************
*** 0 ****
--- 1,51 ----
+ /* { dg-do run } */
+ /* { dg-require-effective-target riscv_v_ok } */
+ /* { dg-add-options riscv_v } */
+ /* { dg-additional-options "-O0" } */
+ 
+ #include <riscv_vector.h>
+ #include <vector>
+ #define a 36
+ 
+ uint8_t e[a], x[a];
+ int64_t f[a], g[a], l[a];
+ float j[a], k[a], m[a];
+ 
+ int main() {
+   for (int i = 0; i < a; ++i) { e[i]=1; g[i] = 86; x[i] = 86; }
+   for (size_t n = 0, avl = a; avl;) {
+     size_t o = __riscv_vsetvl_e64m8(avl);
+     vuint8m1_t p = __riscv_vle8_v_u8m1(&e[n], o);
+     vbool8_t q = __riscv_vmseq_vx_u8m1_b8(p, 1, o);
+     vuint64m8_t r = __riscv_vsll_vx_u64m8(__riscv_vid_v_u64m8(o), 3, o);
+     vint64m8_t s = __riscv_vluxei64_v_i64m8_tum(
+         __riscv_vlm_v_b8(std::vector<uint8_t>(o + 7).data(), o),
+         __riscv_vmv_v_x_i64m8(0, __riscv_vsetvlmax_e16m2()), &f[n], r, o);
+     vuint32m4_t t = __riscv_vsll_vx_u32m4(__riscv_vid_v_u32m4(o), 3, o);
+     vint64m8_t u = __riscv_vluxei32(&g[n], t, o);
+     vbool8_t v = __riscv_vlm_v_b8(&x[n], o);
+     __riscv_vle32ff_v_f32m4_mu(q, __riscv_vfmv_v_f_f32m4(0, __riscv_vsetvlmax_e8m1()), &j[n], &o, o);
+     vfloat32m1_t w = __riscv_vfmv_v_f_f32m1(0, __riscv_vsetvlmax_e32m1());
+     vfloat32m1_t aa = __riscv_vle32_v_f32m1_tu(w, &k[n], o);
+     s = __riscv_vcompress_vm_i64m8_tu(s, u, v, o);
+     vfloat32mf2_t ab = __riscv_vlmul_trunc_v_f32m1_f32mf2(aa);
+     vuint64m8_t ac = __riscv_vsll_vx_u64m8(__riscv_vid_v_u64m8(o), 3, o);
+     __riscv_vsuxei64_v_i64m8(&l[n], ac, s, o);
+     __riscv_vse32_v_f32mf2(&m[n], ab, o);
+     avl -= o;
+   }
+ 
+   /* Results are inconsistent between different VLENs.
+      "n" never changes so we will always store into l[0...] with a length of
+      "o".  What differs is "s".
+      At zvl128b and zvl256b we have more than one loop iteration and
+      "s" will be {86, 86, -1, -1} or {86, 86, 0, 0} depending on the
+      tail/mask policy.
+      At zvl512b there is only one iteration and s = {86, 86, 86, ...}.
+      I cross checked with clang and this seems correct.
+      Therefore only check l's fifth element.
+      The actual PR is about fault-only-first loads and the wrong code
+      caused element 5 to be incorrect as well.  */
+   if (l[5] != 86)
+     __builtin_abort ();
+ }
diff -Nrcpad gcc-15-20260207/gcc/testsuite/g++.target/riscv/rvv/base/pr123808.C gcc-15-20260214/gcc/testsuite/g++.target/riscv/rvv/base/pr123808.C
*** gcc-15-20260207/gcc/testsuite/g++.target/riscv/rvv/base/pr123808.C	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/g++.target/riscv/rvv/base/pr123808.C	Sat Feb 14 22:32:09 2026
***************
*** 0 ****
--- 1,50 ----
+ /* { dg-do run } */
+ /* { dg-require-effective-target riscv_v_ok } */
+ /* { dg-add-options riscv_v } */
+ 
+ #include <riscv_vector.h>
+ #include <vector>
+ #define a 36
+ 
+ uint8_t e[a], x[a];
+ int64_t f[a], g[a], l[a];
+ float j[a], k[a], m[a];
+ 
+ int main() {
+   for (int i = 0; i < a; ++i) { e[i]=1; g[i] = 86; x[i] = 86; }
+   for (size_t n = 0, avl = a; avl;) {
+     size_t o = __riscv_vsetvl_e64m8(avl);
+     vuint8m1_t p = __riscv_vle8_v_u8m1(&e[n], o);
+     vbool8_t q = __riscv_vmseq_vx_u8m1_b8(p, 1, o);
+     vuint64m8_t r = __riscv_vsll_vx_u64m8(__riscv_vid_v_u64m8(o), 3, o);
+     vint64m8_t s = __riscv_vluxei64_v_i64m8_tum(
+         __riscv_vlm_v_b8(std::vector<uint8_t>(o + 7).data(), o),
+         __riscv_vmv_v_x_i64m8(0, __riscv_vsetvlmax_e16m2()), &f[n], r, o);
+     vuint32m4_t t = __riscv_vsll_vx_u32m4(__riscv_vid_v_u32m4(o), 3, o);
+     vint64m8_t u = __riscv_vluxei32(&g[n], t, o);
+     vbool8_t v = __riscv_vlm_v_b8(&x[n], o);
+     __riscv_vle32ff_v_f32m4_mu(q, __riscv_vfmv_v_f_f32m4(0, __riscv_vsetvlmax_e8m1()), &j[n], &o, o);
+     vfloat32m1_t w = __riscv_vfmv_v_f_f32m1(0, __riscv_vsetvlmax_e32m1());
+     vfloat32m1_t aa = __riscv_vle32_v_f32m1_tu(w, &k[n], o);
+     s = __riscv_vcompress_vm_i64m8_tu(s, u, v, o);
+     vfloat32mf2_t ab = __riscv_vlmul_trunc_v_f32m1_f32mf2(aa);
+     vuint64m8_t ac = __riscv_vsll_vx_u64m8(__riscv_vid_v_u64m8(o), 3, o);
+     __riscv_vsuxei64_v_i64m8(&l[n], ac, s, o);
+     __riscv_vse32_v_f32mf2(&m[n], ab, o);
+     avl -= o;
+   }
+ 
+   /* Results are inconsistent between different VLENs.
+      "n" never changes so we will always store into l[0...] with a length of
+      "o".  What differs is "s".
+      At zvl128b and zvl256b we have more than one loop iteration and
+      "s" will be {86, 86, -1, -1} or {86, 86, 0, 0} depending on the
+      tail/mask policy.
+      At zvl512b there is only one iteration and s = {86, 86, 86, ...}.
+      I cross checked with clang and this seems correct.
+      Therefore only check l's fifth element.
+      The actual PR is about fault-only-first loads and the wrong code
+      caused element 5 to be incorrect as well.  */
+   if (l[5] != 86)
+     __builtin_abort ();
+ }
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gcc.dg/pr116479.c gcc-15-20260214/gcc/testsuite/gcc.dg/pr116479.c
*** gcc-15-20260207/gcc/testsuite/gcc.dg/pr116479.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/gcc.dg/pr116479.c	Sat Feb 14 22:32:12 2026
***************
*** 0 ****
--- 1,26 ----
+ /* PR 116479 */
+ /* { dg-do run { target { bitint } } } */
+ /* { dg-additional-options "-O -funroll-loops -finline-stringops -fmodulo-sched --param=max-iterations-computation-cost=637924687 -std=c23" } */
+ 
+ #if __BITINT_MAXWIDTH__ >= 13577
+ _BitInt (13577) b;
+ 
+ void
+ foo (char *ret)
+ {
+   __builtin_memset (&b, 4, 697);
+   *ret = 0;
+ }
+ #endif
+ 
+ int
+ main ()
+ {
+ #if __BITINT_MAXWIDTH__ >= 13577
+   char x;
+   foo (&x);
+   for (unsigned i = 0; i < sizeof (x); i++)
+     if (x != 0)
+       __builtin_abort ();
+ #endif
+ }
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gcc.dg/pr123447.c gcc-15-20260214/gcc/testsuite/gcc.dg/pr123447.c
*** gcc-15-20260207/gcc/testsuite/gcc.dg/pr123447.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/gcc.dg/pr123447.c	Sat Feb 14 22:32:12 2026
***************
*** 0 ****
--- 1,19 ----
+ /* PR middle-end/123447 */
+ /* { dg-do compile { target aarch64*-*-* } } */
+ /* { dg-options "-O2 -mstrict-align" } */
+ 
+ typedef __attribute__((__vector_size__(32))) _Decimal64 D;
+ typedef __attribute__((__vector_size__(64))) int V;
+ typedef __attribute__((__vector_size__(64))) _Decimal64 D64;
+ 
+ D d;
+ 
+ void foo1 () {
+   D _4;
+   D64 _5;
+   V _1;
+   _1 = (V) { 9, -64497, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
+   _5 = (D64) _1;
+   _4 = __builtin_shufflevector (_5, _5, 0, 1, 2, 3);
+   d = _4;
+ }
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gcc.target/aarch64/sme/sme-shrinkwrap.c gcc-15-20260214/gcc/testsuite/gcc.target/aarch64/sme/sme-shrinkwrap.c
*** gcc-15-20260207/gcc/testsuite/gcc.target/aarch64/sme/sme-shrinkwrap.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/gcc.target/aarch64/sme/sme-shrinkwrap.c	Sat Feb 14 22:32:12 2026
***************
*** 0 ****
--- 1,78 ----
+ /* { dg-options "-O3 -fshrink-wrap" } */
+ /* { dg-do run { target { aarch64_sme_hw && aarch64_sve_hw } } } */
+ /* { dg-do compile { target { ! { aarch64_sme_hw && aarch64_sve_hw } } } } */
+ /* { dg-final { check-function-bodies "**" "" } } */
+ 
+ #include <arm_sme.h>
+ 
+ #pragma GCC target "+sve"
+ 
+ [[gnu::noipa]]
+ __arm_streaming
+ int callee (int x)
+ {
+   return 0;
+ }
+ 
+ /*
+ ** foo:
+ **	cbnz	w0, [^\n]*
+ **	cntd	x0
+ **	ret
+ **	...
+ */
+ __arm_streaming
+ int foo(int x)
+ {
+     if (x)
+         return callee(3);
+     return svcntd();
+ }
+ 
+ /*
+ ** bar:
+ **	...
+ **	smstart	[^\n]*
+ **	...
+ ** (
+ **	cntd	[^\n]*
+ **	...
+ **	cbn?z	[^\n]*
+ ** |
+ **	cbn?z	[^\n]*
+ **	...
+ **	cntd	[^\n]*
+ ** )
+ **	...
+ */
+ 
+ __arm_locally_streaming
+ int bar(int x)
+ {
+     if (x)
+         return callee(3);
+     return svcntd();
+ }
+ 
+ /*
+ ** baz:
+ **	cbnz	w0, [^\n]*
+ **	cntd	x0
+ **	ret
+ **	...
+ */
+ __arm_streaming
+ int baz(int x)
+ {
+     if (x)
+         return callee(3);
+     return svcntd();
+ }
+ 
+ [[gnu::noipa]]
+ int main()
+ {
+   if (bar(0) != svcntsd())
+     __builtin_abort();
+   return 0;
+ }
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gcc.target/riscv/pr121787-1.c gcc-15-20260214/gcc/testsuite/gcc.target/riscv/pr121787-1.c
*** gcc-15-20260207/gcc/testsuite/gcc.target/riscv/pr121787-1.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/gcc.target/riscv/pr121787-1.c	Sat Feb 14 22:32:14 2026
***************
*** 0 ****
--- 1,20 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv -mabi=lp64 -O" { target rv64 } } */
+ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O" { target rv32 } } */
+ 
+ #include <stdint-gcc.h>
+ typedef int a;
+ int32_t b, e;
+ int32_t **c;
+ uint8_t d(int32_t *, int32_t *, uint16_t, const int32_t *, int32_t **);
+ uint32_t f() {
+   uint16_t g;
+   d(0, &b, g, &b, c);
+   e = (__attribute__((__vector_size__(sizeof(a)))) a){}[4];
+ }
+ uint8_t d(int32_t *, int32_t *, uint16_t, const int32_t *, int32_t **) {
+   asm goto("" : : : : i);
+ i:
+ j:
+   asm goto("" : : : : j);
+ }
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gcc.target/riscv/pr121787-2.c gcc-15-20260214/gcc/testsuite/gcc.target/riscv/pr121787-2.c
*** gcc-15-20260207/gcc/testsuite/gcc.target/riscv/pr121787-2.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/gcc.target/riscv/pr121787-2.c	Sat Feb 14 22:32:14 2026
***************
*** 0 ****
--- 1,20 ----
+ /* { dg-do compile } */
+ /* { dg-options "-march=rv64gcv -mabi=lp64 -O" { target rv64 } } */
+ /* { dg-options "-march=rv32gcv -mabi=ilp32 -O" { target rv32 } } */
+ 
+ #include <stdint-gcc.h>
+ typedef int a;
+ int32_t b, e;
+ int32_t **c;
+ uint8_t d(int32_t *, int32_t *, uint16_t, const int32_t *, int32_t **);
+ uint32_t f(int a1) {
+   uint16_t g;
+   d(0, &b, g, &b, c);
+   e = (__attribute__((__vector_size__(sizeof(a)*16))) a){}[a1];
+ }
+ uint8_t d(int32_t *, int32_t *, uint16_t, const int32_t *, int32_t **) {
+   asm goto("#asm1" : : : : i);
+ i:
+ j:
+   asm goto("#asm2" : : : : j);
+ }
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123940.c gcc-15-20260214/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123940.c
*** gcc-15-20260207/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123940.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr123940.c	Sat Feb 14 22:32:14 2026
***************
*** 0 ****
--- 1,25 ----
+ /* { dg-do run } */
+ /* { dg-options "-O3 -march=rv64gcv -mabi=lp64d -std=gnu99 -fdump-tree-widening_mul" } */
+ 
+ long a;
+ long long b;
+ _Bool c[16];
+ char d[16];
+ char e = 0;
+ int f = 1;
+ 
+ int main ()
+ {
+   for (long i = 0; i < 16; ++i)
+     c[i] = 40;
+   for (int j = 0; j < 16; j++)
+     {
+       e = (c[j] ? j : d[j]) + d[j];
+       a = f * c[j] ?: ~0;
+     }
+   b = (int) e;
+   if (b != 15)
+     __builtin_abort ();
+ }
+ 
+ /* { dg-final { scan-tree-dump-not "FMA" "widening_mul" } } */
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gcc.target/riscv/rvv/base/pr122656-1.c gcc-15-20260214/gcc/testsuite/gcc.target/riscv/rvv/base/pr122656-1.c
*** gcc-15-20260207/gcc/testsuite/gcc.target/riscv/rvv/base/pr122656-1.c	Sat Feb  7 22:32:12 2026
--- gcc-15-20260214/gcc/testsuite/gcc.target/riscv/rvv/base/pr122656-1.c	Sat Feb 14 22:32:14 2026
***************
*** 4,7 ****
  #include "riscv_vector.h"
  int a;
  long b, c;
! void d() { __riscv_vlseg2e32ff_v_i32mf2x2(&a, &c, b); } /* { dg-error "invalid argument to built-in function" } */
--- 4,7 ----
  #include "riscv_vector.h"
  int a;
  long b, c;
! void d() { __riscv_vlseg2e32ff_v_i32mf2x2(&a, &c, b); }
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gcc.target/riscv/rvv/base/pr122869.c gcc-15-20260214/gcc/testsuite/gcc.target/riscv/rvv/base/pr122869.c
*** gcc-15-20260207/gcc/testsuite/gcc.target/riscv/rvv/base/pr122869.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/gcc.target/riscv/rvv/base/pr122869.c	Sat Feb 14 22:32:14 2026
***************
*** 0 ****
--- 1,22 ----
+ /* { dg-do run } */
+ /* { dg-additional-options "-O0 -std=gnu99" } */
+ /* We used to generate a separate riscv_read_vl () after the FoF load.
+    In case of -O0 (or otherwise) it could happen that "g" wouldn't
+    get a hard reg and we'd need to store it, clobbering VL.
+    This leads to an infinite loop or a segfault.  */
+ 
+ #include <riscv_vector.h>
+ 
+ uint8_t a[1];
+ int16_t b[1];
+ 
+ int main ()
+ {
+   for (size_t c = 0, avl = 1; avl > 0;)
+     {
+       size_t d = avl;
+       vint16mf2_t g = __riscv_vle16ff_v_i16mf2 (&b[c], &d, d);
+       avl -= d;
+       c += d; // Segmentation fault
+     }
+ }
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c gcc-15-20260214/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c
*** gcc-15-20260207/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c	Sat Feb  7 22:32:12 2026
--- gcc-15-20260214/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/ffload-3.c	Sat Feb 14 22:32:14 2026
*************** void f (int8_t * restrict in, int8_t * r
*** 25,28 ****
      }
  }
  
! /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
--- 25,29 ----
      }
  }
  
! /* -O2 and -O3 fail now, see PR target/122869.  */
! /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } xfail { any-opts "-O2" "-O3" } } } } */
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr123969.c gcc-15-20260214/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr123969.c
*** gcc-15-20260207/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr123969.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr123969.c	Sat Feb 14 22:32:14 2026
***************
*** 0 ****
--- 1,19 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O3 -march=rv64gcxtheadvector -mabi=lp64d -mtune=rocket" } */
+ 
+ /* In order to trigger the issue strided broadcast must be enabled
+    and we must broadcast integer memory operands via strided load.
+    This is disabled and there is currently no param to change it
+    so the test will pass either way.  */
+ 
+ #include <riscv_vector.h>
+ 
+ void test(int16_t *dst, long vl) {
+   vuint16m1_t v6 = __riscv_vmv_v_x_u16m1(*dst, vl);
+   vfloat32m2_t s0 = __riscv_vfmv_v_f_f32m2(0, vl);
+   __riscv_vse16_v_u16m1(dst, v6, vl);
+   __riscv_vse32_v_f32m2((float*)dst, s0, vl);
+ }
+ 
+ /* { dg-final { scan-assembler-times "th.vsetvli\tzero,a1,e16,m1" 2 } } */
+ /* { dg-final { scan-assembler-times "th.vsetvli\tzero,a1,e32,m2" 2 } } */
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr123971.c gcc-15-20260214/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr123971.c
*** gcc-15-20260207/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr123971.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr123971.c	Sat Feb 14 22:32:14 2026
***************
*** 0 ****
--- 1,12 ----
+ /* { dg-do compile } */
+ /* { dg-options "-O -mcpu=xt-c920 -mrvv-vector-bits=zvl" } */
+ 
+ __attribute__((__vector_size__(sizeof(int)))) int u;
+ __attribute__((__vector_size__(4 * sizeof(int)))) int v;
+ __attribute__((__vector_size__(8 * sizeof(int)))) int w;
+ 
+ void
+ foo()
+ {
+   v ^= __builtin_shufflevector(u, w % 3, 4, 3, 4, 1);
+ }
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gcc.target/s390/vxe3/vcmp-1.c gcc-15-20260214/gcc/testsuite/gcc.target/s390/vxe3/vcmp-1.c
*** gcc-15-20260207/gcc/testsuite/gcc.target/s390/vxe3/vcmp-1.c	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/gcc.target/s390/vxe3/vcmp-1.c	Sat Feb 14 22:32:14 2026
***************
*** 0 ****
--- 1,42 ----
+ /* { dg-do compile } */
+ /* { dg-require-effective-target int128 } */
+ /* { dg-final { check-function-bodies "**" "" "" } } */
+ 
+ typedef __int128 __attribute__ ((vector_size (16))) V1TI;
+ typedef unsigned __int128 __attribute__ ((vector_size (16))) UV1TI;
+ 
+ /*
+ ** cmpeq:
+ **	vceqq	%v24,%v24,%v26
+ **	br	%r14
+ */
+ 
+ V1TI
+ cmpeq (V1TI x, V1TI y)
+ {
+   return x == y;
+ }
+ 
+ /*
+ ** cmpgt:
+ **	vchq	%v24,%v24,%v26
+ **	br	%r14
+ */
+ 
+ V1TI
+ cmpgt (V1TI x, V1TI y)
+ {
+   return x > y;
+ }
+ 
+ /*
+ ** cmpgtu:
+ **	vchlq	%v24,%v24,%v26
+ **	br	%r14
+ */
+ 
+ V1TI
+ cmpgtu (UV1TI x, UV1TI y)
+ {
+   return x > y;
+ }
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gdc.dg/pr124026.d gcc-15-20260214/gcc/testsuite/gdc.dg/pr124026.d
*** gcc-15-20260207/gcc/testsuite/gdc.dg/pr124026.d	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/gdc.dg/pr124026.d	Sat Feb 14 22:32:14 2026
***************
*** 0 ****
--- 1,21 ----
+ // { dg-do compile }
+ struct UDA
+ {
+     int delegate() foo;
+ }
+ 
+ static UDA getUDA(alias S)()
+ {
+     return __traits(getAttributes, S)[0];
+ }
+ 
+ struct S124026
+ {
+     @UDA({ return 42; }) int a;
+ }
+ 
+ void f124026()
+ {
+     S124026 m;
+     enum uda = getUDA!(m.a);
+ }
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gfortran.dg/class_array_24.f90 gcc-15-20260214/gcc/testsuite/gfortran.dg/class_array_24.f90
*** gcc-15-20260207/gcc/testsuite/gfortran.dg/class_array_24.f90	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/gfortran.dg/class_array_24.f90	Sat Feb 14 22:32:15 2026
***************
*** 0 ****
--- 1,58 ----
+ ! { dg-do run }
+ ! { dg-additional-options "-O2 -fdump-tree-optimized" }
+ !
+ ! PR fortran/123961 - SIZE and class array valued constructors and functions
+ 
+ module test_overload_m
+   implicit none
+ 
+   type :: foo_t
+   end type foo_t
+ 
+   interface foo_t
+      module procedure foo_t_0_
+      module procedure foo_t_1_
+      module procedure foo_c_0_
+      module procedure foo_c_1_
+   end interface foo_t
+ 
+ contains
+ 
+   function foo_t_0_(i) result(foo)
+     integer, intent(in)      :: i
+     type(foo_t), allocatable :: foo
+     allocate (foo)
+   end function foo_t_0_
+ 
+   function foo_t_1_(i) result(foo)
+     integer, intent(in)      :: i(:)
+     type(foo_t), allocatable :: foo(:)
+ 
+     allocate (foo(size (i)))
+   end function foo_t_1_
+ 
+   function foo_c_0_(r) result(foo)
+     real, intent(in)          :: r
+     class(foo_t), allocatable :: foo
+     allocate (foo)
+   end function foo_c_0_
+ 
+   function foo_c_1_(r) result(foo)
+     real, intent(in)          :: r(:)
+     class(foo_t), allocatable :: foo(:)
+ 
+     allocate (foo(size (r)))
+   end function foo_c_1_
+ 
+ end module test_overload_m
+ 
+ program test_overload
+    use test_overload_m
+    implicit none
+ 
+    if (size (foo_t([1,2,3])) /= 3) stop 1   ! Optimized
+    if (size (foo_t([1.,2.])) /= 2) stop 2   ! Optimized
+ 
+ end program test_overload
+ 
+ ! { dg-final { scan-tree-dump-not "_gfortran_error_stop_numeric" "optimized" } }
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gnat.dg/allocator4.adb gcc-15-20260214/gcc/testsuite/gnat.dg/allocator4.adb
*** gcc-15-20260207/gcc/testsuite/gnat.dg/allocator4.adb	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/gnat.dg/allocator4.adb	Sat Feb 14 22:32:15 2026
***************
*** 0 ****
--- 1,23 ----
+ --  { dg-do compile }
+ --  { dg-options "-gnatws" }
+ 
+ with System.Storage_Pools.Subpools; use System.Storage_Pools.Subpools;
+ with Ada.Finalization;              use Ada.Finalization;
+ 
+ procedure Allocator4 is
+ 
+    type My_Subpool_Type is new Root_Subpool with null record;
+    type My_Subpool_Access_Type is access all My_Subpool_Type;
+ 
+    My_Subpool        : aliased My_Subpool_Type;
+    My_Subpool_Access : Subpool_Handle := My_Subpool'Unchecked_Access;
+ 
+    type T is new Ada.Finalization.Controlled with null record;
+ 
+    A : access T := new (Subpool_Handle'(My_Subpool'Unchecked_Access)) T;
+    B : access T := new (My_Subpool_Access) T;
+    C : access T := new (My_Subpool'Access) T;
+ 
+ begin
+    null;
+ end;
diff -Nrcpad gcc-15-20260207/gcc/testsuite/gnat.dg/protected_type1.adb gcc-15-20260214/gcc/testsuite/gnat.dg/protected_type1.adb
*** gcc-15-20260207/gcc/testsuite/gnat.dg/protected_type1.adb	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/gcc/testsuite/gnat.dg/protected_type1.adb	Sat Feb 14 22:32:15 2026
***************
*** 0 ****
--- 1,25 ----
+ --  { dg-do compile }
+ 
+ with Ada.Finalization;
+ 
+ procedure Protected_Type1 is
+ 
+   type T is new Ada.Finalization.Controlled with null record;
+ 
+   protected type Queue is
+     entry Get_Next_Line (Line : out String);
+   private
+     A : T;
+   end Queue;
+ 
+   protected body Queue is
+     entry Get_Next_Line (Line : out String)
+       when A /= (Ada.Finalization.Controlled with null record) is
+     begin
+       null;
+     end Get_Next_Line;
+   end Queue;
+ 
+ begin
+   null;
+ end;
diff -Nrcpad gcc-15-20260207/gcc/tree-ssa-math-opts.cc gcc-15-20260214/gcc/tree-ssa-math-opts.cc
*** gcc-15-20260207/gcc/tree-ssa-math-opts.cc	Sat Feb  7 22:32:14 2026
--- gcc-15-20260214/gcc/tree-ssa-math-opts.cc	Sat Feb 14 22:32:15 2026
*************** convert_mult_to_fma (gimple *mul_stmt, t
*** 3464,3469 ****
--- 3464,3473 ----
  					      &else_value, &len, &bias))
  	return false;
  
+       /* The multiplication result must be one of the addition operands.  */
+       if (ops[0] != result && ops[1] != result)
+ 	return false;
+ 
        switch (code)
  	{
  	case MINUS_EXPR:
diff -Nrcpad gcc-15-20260207/libstdc++-v3/ChangeLog gcc-15-20260214/libstdc++-v3/ChangeLog
*** gcc-15-20260207/libstdc++-v3/ChangeLog	Sat Feb  7 22:32:16 2026
--- gcc-15-20260214/libstdc++-v3/ChangeLog	Sat Feb 14 22:32:17 2026
***************
*** 1,3 ****
--- 1,51 ----
+ 2026-02-10  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-11-24  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	* python/libstdcxx/v6/xmethods.py (ListMethodsMatcher.match):
+ 	Fix lookup for node type.
+ 
+ 2026-02-10  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2025-11-24  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	PR libstdc++/122821
+ 	* python/libstdcxx/v6/xmethods.py (_versioned_namespace): Remove
+ 	global variable.
+ 	(is_specialization_of): Do not use _versioned_namespace. Add
+ 	__debug:: to regex.
+ 
+ 2026-02-10  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-02-10  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	PR libstdc++/123991
+ 	* include/bits/basic_string.h (compare(size_type, size_type, T)):
+ 	Remove noexcept-specifier.
+ 	(compare(size_type, size_type, T, size_type, size_type)):
+ 	Likewise.
+ 	* include/bits/cow_string.h (compare(size_type, size_type, T)):
+ 	Remove noexcept-specifier.
+ 	(compare(size_type, size_type, T, size_type, size_type)):
+ 	Likewise.
+ 	* testsuite/21_strings/basic_string/operations/compare/char/123991.cc:
+ 	New test.
+ 	* testsuite/21_strings/basic_string/operations/compare/wchar_t/123991.cc:
+ 	New test.
+ 
+ 2026-02-09  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	Backported from master:
+ 	2026-02-09  Jonathan Wakely  <jwakely@redhat.com>
+ 
+ 	PR libstdc++/124024
+ 	* include/bits/out_ptr.h (out_ptr): Fix doxygen comment to refer
+ 	to the right function.
+ 	(inout_ptr): Improve markup in doxygen comment.
+ 
  2026-02-06  Tomasz Kamiński  <tkaminsk@redhat.com>
  
  	Backported from master:
diff -Nrcpad gcc-15-20260207/libstdc++-v3/include/bits/basic_string.h gcc-15-20260214/libstdc++-v3/include/bits/basic_string.h
*** gcc-15-20260207/libstdc++-v3/include/bits/basic_string.h	Sat Feb  7 22:32:16 2026
--- gcc-15-20260214/libstdc++-v3/include/bits/basic_string.h	Sat Feb 14 22:32:17 2026
*************** _GLIBCXX_BEGIN_NAMESPACE_CXX11
*** 3505,3511 ****
  	_GLIBCXX_NODISCARD _GLIBCXX20_CONSTEXPR
  	_If_sv<_Tp, int>
  	compare(size_type __pos, size_type __n, const _Tp& __svt) const
- 	noexcept(is_same<_Tp, __sv_type>::value)
  	{
  	  __sv_type __sv = __svt;
  	  return __sv_type(*this).substr(__pos, __n).compare(__sv);
--- 3505,3510 ----
*************** _GLIBCXX_BEGIN_NAMESPACE_CXX11
*** 3526,3532 ****
  	_If_sv<_Tp, int>
  	compare(size_type __pos1, size_type __n1, const _Tp& __svt,
  		size_type __pos2, size_type __n2 = npos) const
- 	noexcept(is_same<_Tp, __sv_type>::value)
  	{
  	  __sv_type __sv = __svt;
  	  return __sv_type(*this)
--- 3525,3530 ----
diff -Nrcpad gcc-15-20260207/libstdc++-v3/include/bits/cow_string.h gcc-15-20260214/libstdc++-v3/include/bits/cow_string.h
*** gcc-15-20260207/libstdc++-v3/include/bits/cow_string.h	Sat Feb  7 22:32:16 2026
--- gcc-15-20260214/libstdc++-v3/include/bits/cow_string.h	Sat Feb 14 22:32:17 2026
*************** _GLIBCXX_BEGIN_NAMESPACE_VERSION
*** 2979,2985 ****
        template<typename _Tp>
  	_If_sv<_Tp, int>
  	compare(size_type __pos, size_type __n, const _Tp& __svt) const
- 	noexcept(is_same<_Tp, __sv_type>::value)
  	{
  	  __sv_type __sv = __svt;
  	  return __sv_type(*this).substr(__pos, __n).compare(__sv);
--- 2979,2984 ----
*************** _GLIBCXX_BEGIN_NAMESPACE_VERSION
*** 2999,3005 ****
  	_If_sv<_Tp, int>
  	compare(size_type __pos1, size_type __n1, const _Tp& __svt,
  		size_type __pos2, size_type __n2 = npos) const
- 	noexcept(is_same<_Tp, __sv_type>::value)
  	{
  	  __sv_type __sv = __svt;
  	  return __sv_type(*this)
--- 2998,3003 ----
diff -Nrcpad gcc-15-20260207/libstdc++-v3/include/bits/out_ptr.h gcc-15-20260214/libstdc++-v3/include/bits/out_ptr.h
*** gcc-15-20260207/libstdc++-v3/include/bits/out_ptr.h	Sat Feb  7 22:32:16 2026
--- gcc-15-20260214/libstdc++-v3/include/bits/out_ptr.h	Sat Feb 14 22:32:17 2026
*************** namespace __detail
*** 397,403 ****
     * @tparam _Pointer The type of pointer to convert to.
     * @param __s The pointer that should take ownership of the result.
     * @param __args... Arguments to use when resetting the smart pointer.
!    * @return A std::inout_ptr_t referring to `__s`.
     * @since C++23
     * @headerfile <memory>
     */
--- 397,403 ----
     * @tparam _Pointer The type of pointer to convert to.
     * @param __s The pointer that should take ownership of the result.
     * @param __args... Arguments to use when resetting the smart pointer.
!    * @return A `std::out_ptr_t` referring to `__s`.
     * @since C++23
     * @headerfile <memory>
     */
*************** namespace __detail
*** 418,424 ****
     * @tparam _Pointer The type of pointer to convert to.
     * @param __s The pointer that should take ownership of the result.
     * @param __args... Arguments to use when resetting the smart pointer.
!    * @return A std::inout_ptr_t referring to `__s`.
     * @since C++23
     * @headerfile <memory>
     */
--- 418,424 ----
     * @tparam _Pointer The type of pointer to convert to.
     * @param __s The pointer that should take ownership of the result.
     * @param __args... Arguments to use when resetting the smart pointer.
!    * @return A `std::inout_ptr_t` referring to `__s`.
     * @since C++23
     * @headerfile <memory>
     */
diff -Nrcpad gcc-15-20260207/libstdc++-v3/python/libstdcxx/v6/xmethods.py gcc-15-20260214/libstdc++-v3/python/libstdcxx/v6/xmethods.py
*** gcc-15-20260207/libstdc++-v3/python/libstdcxx/v6/xmethods.py	Sat Feb  7 22:32:16 2026
--- gcc-15-20260214/libstdc++-v3/python/libstdcxx/v6/xmethods.py	Sat Feb 14 22:32:17 2026
*************** def get_bool_type():
*** 28,35 ****
  def get_std_size_type():
      return gdb.lookup_type('std::size_t')
  
- _versioned_namespace = '__8::'
- 
  def is_specialization_of(x, template_name):
      """
      Test whether a type is a specialization of the named class template.
--- 28,33 ----
*************** def is_specialization_of(x, template_nam
*** 39,46 ****
      """
      if isinstance(x, gdb.Type):
          x = x.tag
!     template_name = '(%s)?%s' % (_versioned_namespace, template_name)
!     return re.match(r'^std::(__\d::)?%s<.*>$' % template_name, x) is not None
  
  class LibStdCxxXMethod(gdb.xmethod.XMethod):
      def __init__(self, name, worker_class):
--- 37,43 ----
      """
      if isinstance(x, gdb.Type):
          x = x.tag
!     return re.match(r'^std::(__\d::|__debug::)?%s<.*>$' % template_name, x) is not None
  
  class LibStdCxxXMethod(gdb.xmethod.XMethod):
      def __init__(self, name, worker_class):
*************** class ListMethodsMatcher(gdb.xmethod.XMe
*** 445,451 ****
          if method is None or not method.enabled:
              return None
          val_type = class_type.template_argument(0)
!         node_type = gdb.lookup_type(str(class_type) + '::_Node').pointer()
          return method.worker_class(val_type, node_type)
  
  # Xmethods for std::vector
--- 442,448 ----
          if method is None or not method.enabled:
              return None
          val_type = class_type.template_argument(0)
!         node_type = gdb.lookup_type(str(class_type) + '::_Node_ptr')
          return method.worker_class(val_type, node_type)
  
  # Xmethods for std::vector
diff -Nrcpad gcc-15-20260207/libstdc++-v3/testsuite/21_strings/basic_string/operations/compare/char/123991.cc gcc-15-20260214/libstdc++-v3/testsuite/21_strings/basic_string/operations/compare/char/123991.cc
*** gcc-15-20260207/libstdc++-v3/testsuite/21_strings/basic_string/operations/compare/char/123991.cc	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/libstdc++-v3/testsuite/21_strings/basic_string/operations/compare/char/123991.cc	Sat Feb 14 22:32:18 2026
***************
*** 0 ****
--- 1,56 ----
+ // { dg-do run { target c++17 } }
+ 
+ // Bug 123991 - std::string::compare crashes instead of throwing
+ 
+ #include <string>
+ #include <string_view>
+ #include <stdexcept>
+ #include <testsuite_hooks.h>
+ 
+ void
+ test_compare_3arg()
+ {
+   std::string_view sv;
+   std::string s;
+   static_assert( ! noexcept(s.compare(0, 0, sv)) );
+ #ifdef __cpp_exceptions
+   try
+   {
+     (void) s.compare(1, 0, sv);
+     VERIFY(false);
+   }
+   catch (const std::out_of_range&)
+   { }
+ #endif
+ }
+ 
+ void
+ test_compare_5arg()
+ {
+   std::string_view sv;
+   std::string s;
+   static_assert( ! noexcept(s.compare(0, 0, sv, 0, 0)) );
+ #ifdef __cpp_exceptions
+   try
+   {
+     (void) s.compare(1, 0, sv, 0, 0);
+     VERIFY(false);
+   }
+   catch (const std::out_of_range&)
+   { }
+ 
+   try
+   {
+     (void) s.compare(0, 0, sv, 1, 0);
+     VERIFY(false);
+   }
+   catch (const std::out_of_range&)
+   { }
+ #endif
+ }
+ 
+ int main()
+ {
+   test_compare_3arg();
+   test_compare_5arg();
+ }
diff -Nrcpad gcc-15-20260207/libstdc++-v3/testsuite/21_strings/basic_string/operations/compare/wchar_t/123991.cc gcc-15-20260214/libstdc++-v3/testsuite/21_strings/basic_string/operations/compare/wchar_t/123991.cc
*** gcc-15-20260207/libstdc++-v3/testsuite/21_strings/basic_string/operations/compare/wchar_t/123991.cc	Thu Jan  1 00:00:00 1970
--- gcc-15-20260214/libstdc++-v3/testsuite/21_strings/basic_string/operations/compare/wchar_t/123991.cc	Sat Feb 14 22:32:18 2026
***************
*** 0 ****
--- 1,56 ----
+ // { dg-do run { target c++17 } }
+ 
+ // Bug 123991 - std::string::compare crashes instead of throwing
+ 
+ #include <string>
+ #include <string_view>
+ #include <stdexcept>
+ #include <testsuite_hooks.h>
+ 
+ void
+ test_compare_3arg()
+ {
+   std::wstring_view sv;
+   std::wstring s;
+   static_assert( ! noexcept(s.compare(0, 0, sv)) );
+ #ifdef __cpp_exceptions
+   try
+   {
+     (void) s.compare(1, 0, sv);
+     VERIFY(false);
+   }
+   catch (const std::out_of_range&)
+   { }
+ #endif
+ }
+ 
+ void
+ test_compare_5arg()
+ {
+   std::wstring_view sv;
+   std::wstring s;
+   static_assert( ! noexcept(s.compare(0, 0, sv, 0, 0)) );
+ #ifdef __cpp_exceptions
+   try
+   {
+     (void) s.compare(1, 0, sv, 0, 0);
+     VERIFY(false);
+   }
+   catch (const std::out_of_range&)
+   { }
+ 
+   try
+   {
+     (void) s.compare(0, 0, sv, 1, 0);
+     VERIFY(false);
+   }
+   catch (const std::out_of_range&)
+   { }
+ #endif
+ }
+ 
+ int main()
+ {
+   test_compare_3arg();
+   test_compare_5arg();
+ }
